[mirror_qemu.git] / hw / sun4u.c

/*
 * QEMU Sun4u System Emulator
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
#include "m48t59.h"

#define KERNEL_LOAD_ADDR     0x00404000
#define CMDLINE_ADDR         0x003ff000
#define INITRD_LOAD_ADDR     0x00300000
#define PROM_SIZE_MAX        (512 * 1024)
#define PROM_ADDR            0x1fff0000000ULL
#define PROM_VADDR           0x000ffd00000ULL
#define APB_SPECIAL_BASE     0x1fe00000000ULL
#define APB_MEM_BASE         0x1ff00000000ULL
#define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
#define PROM_FILENAME        "openbios-sparc64"
#define NVRAM_SIZE           0x2000

/* TSC handling */

uint64_t cpu_get_tsc()
{
    return qemu_get_clock(vm_clock);
}

int DMA_get_channel_mode (int nchan)
{
    return 0;
}
int DMA_read_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
int DMA_write_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(int nchan) {}
void DMA_run (void) {}
void DMA_init (int high_page_enable) {}
void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler,
                           void *opaque)
{
}

/* NVRAM helpers */
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
{
    m48t59_write(nvram, addr, value);
}

uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
{
    return m48t59_read(nvram, addr);
}

void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
{
    m48t59_write(nvram, addr, value >> 8);
    m48t59_write(nvram, addr + 1, value & 0xFF);
}

uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
{
    uint16_t tmp;

    tmp = m48t59_read(nvram, addr) << 8;
    tmp |= m48t59_read(nvram, addr + 1);

    return tmp;
}

void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
{
    m48t59_write(nvram, addr, value >> 24);
    m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
    m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
    m48t59_write(nvram, addr + 3, value & 0xFF);
}

uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
{
    uint32_t tmp;

    tmp = m48t59_read(nvram, addr) << 24;
    tmp |= m48t59_read(nvram, addr + 1) << 16;
    tmp |= m48t59_read(nvram, addr + 2) << 8;
    tmp |= m48t59_read(nvram, addr + 3);

    return tmp;
}

void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
                       const unsigned char *str, uint32_t max)
{
    int i;

    for (i = 0; i < max && str[i] != '\0'; i++) {
        m48t59_write(nvram, addr + i, str[i]);
    }
    m48t59_write(nvram, addr + max - 1, '\0');
}

int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
{
    int i;

    memset(dst, 0, max);
    for (i = 0; i < max; i++) {
        dst[i] = NVRAM_get_byte(nvram, addr + i);
        if (dst[i] == '\0')
            break;
    }

    return i;
}

static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
{
    uint16_t tmp;
    uint16_t pd, pd1, pd2;

    tmp = prev >> 8;
    pd = prev ^ value;
    pd1 = pd & 0x000F;
    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
    tmp ^= (pd1 << 3) | (pd1 << 8);
    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);

    return tmp;
}

uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
{
    uint32_t i;
    uint16_t crc = 0xFFFF;
    int odd;

    odd = count & 1;
    count &= ~1;
    for (i = 0; i != count; i++) {
        crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
    }
    if (odd) {
        crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
    }

    return crc;
}

static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
                                const unsigned char *str)
{
    uint32_t len;

    len = strlen(str) + 1;
    NVRAM_set_string(nvram, addr, str, len);

    return addr + len;
}

static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
                                    uint32_t end)
{
    unsigned int i, sum;

    // Length divided by 16
    m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
    m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
    // Checksum
    sum = m48t59_read(nvram, start);
    for (i = 0; i < 14; i++) {
        sum += m48t59_read(nvram, start + 2 + i);
        sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
    }
    m48t59_write(nvram, start + 1, sum & 0xff);
}

extern int nographic;

int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
                          const unsigned char *arch,
                          uint32_t RAM_size, int boot_device,
                          uint32_t kernel_image, uint32_t kernel_size,
                          const char *cmdline,
                          uint32_t initrd_image, uint32_t initrd_size,
                          uint32_t NVRAM_image,
                          int width, int height, int depth)
{
    uint16_t crc;
    unsigned int i;
    uint32_t start, end;

    /* Set parameters for Open Hack'Ware BIOS */
    NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
    NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
    NVRAM_set_word(nvram,   0x14, NVRAM_size);
    NVRAM_set_string(nvram, 0x20, arch, 16);
    NVRAM_set_byte(nvram,   0x2f, nographic & 0xff);
    NVRAM_set_lword(nvram,  0x30, RAM_size);
    NVRAM_set_byte(nvram,   0x34, boot_device);
    NVRAM_set_lword(nvram,  0x38, kernel_image);
    NVRAM_set_lword(nvram,  0x3C, kernel_size);
    if (cmdline) {
        /* XXX: put the cmdline in NVRAM too ? */
        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
        NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
        NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
    } else {
        NVRAM_set_lword(nvram,  0x40, 0);
        NVRAM_set_lword(nvram,  0x44, 0);
    }
    NVRAM_set_lword(nvram,  0x48, initrd_image);
    NVRAM_set_lword(nvram,  0x4C, initrd_size);
    NVRAM_set_lword(nvram,  0x50, NVRAM_image);

    NVRAM_set_word(nvram,   0x54, width);
    NVRAM_set_word(nvram,   0x56, height);
    NVRAM_set_word(nvram,   0x58, depth);
    crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
    NVRAM_set_word(nvram,  0xFC, crc);

    // OpenBIOS nvram variables
    // Variable partition
    start = 256;
    m48t59_write(nvram, start, 0x70);
    NVRAM_set_string(nvram, start + 4, "system", 12);

    end = start + 16;
    for (i = 0; i < nb_prom_envs; i++)
        end = nvram_set_var(nvram, end, prom_envs[i]);

    m48t59_write(nvram, end++ , 0);
    end = start + ((end - start + 15) & ~15);
    nvram_finish_partition(nvram, start, end);

    // free partition
    start = end;
    m48t59_write(nvram, start, 0x7f);
    NVRAM_set_string(nvram, start + 4, "free", 12);

    end = 0x1fd0;
    nvram_finish_partition(nvram, start, end);

    return 0;
}

void pic_info()
{
}

void irq_info()
{
}

void qemu_system_powerdown(void)
{
}

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;

    cpu_reset(env);
    ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->tick, 0);
    ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->stick, 0);
    ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->hstick, 0);
}

void tick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

void stick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

void hstick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

static void dummy_cpu_set_irq(void *opaque, int irq, int level)
{
}

static const int ide_iobase[2] = { 0x1f0, 0x170 };
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 14, 15 };

static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };

static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };

static fdctrl_t *floppy_controller;

/* Sun4u hardware initialisation */
static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_device,
             DisplayState *ds, const char **fd_filename, int snapshot,
             const char *kernel_filename, const char *kernel_cmdline,
             const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    char buf[1024];
    m48t59_t *nvram;
    int ret, linux_boot;
    unsigned int i;
    long prom_offset, initrd_size, kernel_size;
    PCIBus *pci_bus;
    const sparc_def_t *def;
    QEMUBH *bh;
    qemu_irq *irq;

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    if (cpu_model == NULL)
        cpu_model = "TI UltraSparc II";
    sparc_find_by_name(cpu_model, &def);
    if (def == NULL) {
        fprintf(stderr, "Unable to find Sparc CPU definition\n");
        exit(1);
    }
    env = cpu_init();
    cpu_sparc_register(env, def, 0);
    bh = qemu_bh_new(tick_irq, env);
    env->tick = ptimer_init(bh);
    ptimer_set_period(env->tick, 1ULL);

    bh = qemu_bh_new(stick_irq, env);
    env->stick = ptimer_init(bh);
    ptimer_set_period(env->stick, 1ULL);

    bh = qemu_bh_new(hstick_irq, env);
    env->hstick = ptimer_init(bh);
    ptimer_set_period(env->hstick, 1ULL);
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
    qemu_register_reset(main_cpu_reset, env);
    main_cpu_reset(env);

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, 0);

    prom_offset = ram_size + vga_ram_size;
    cpu_register_physical_memory(PROM_ADDR,
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
                                 prom_offset | IO_MEM_ROM);

    if (bios_name == NULL)
        bios_name = PROM_FILENAME;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
    ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
    if (ret < 0) {
        fprintf(stderr, "qemu: could not load prom '%s'\n",
                buf);
        exit(1);
    }

    kernel_size = 0;
    initrd_size = 0;
    if (linux_boot) {
        /* XXX: put correct offset */
        kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
        if (kernel_size < 0)
            kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        if (kernel_size < 0)
            kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }

        /* load initrd */
        if (initrd_filename) {
            initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                        initrd_filename);
                exit(1);
            }
        }
        if (initrd_size > 0) {
            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
                if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
                    == 0x48647253) { // HdrS
                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
                    break;
                }
            }
        }
    }
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
    isa_mem_base = VGA_BASE;
    pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);

    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
        if (serial_hds[i]) {
            serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
        }
    }

    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
        if (parallel_hds[i]) {
            parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
        }
    }

    for(i = 0; i < nb_nics; i++) {
        if (!nd_table[i].model)
            nd_table[i].model = "ne2k_pci";
        pci_nic_init(pci_bus, &nd_table[i], -1);
    }

    irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
    // XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
    pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
    /* FIXME: wire up interrupts.  */
    i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
    floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
    nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device[0],
                         KERNEL_LOAD_ADDR, kernel_size,
                         kernel_cmdline,
                         INITRD_LOAD_ADDR, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0,
                         graphic_width, graphic_height, graphic_depth);

}

QEMUMachine sun4u_machine = {
    "sun4u",
    "Sun4u platform",
    sun4u_init,
};
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sun4u System Emulator
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
83469015	25	#include "m48t59.h"
3475187d	26
83469015 FB	27	#define KERNEL_LOAD_ADDR 0x00404000
	28	#define CMDLINE_ADDR 0x003ff000
	29	#define INITRD_LOAD_ADDR 0x00300000
75956cf0	30	#define PROM_SIZE_MAX (512 * 1024)
f930d07e BS	31	#define PROM_ADDR 0x1fff0000000ULL
f930d07e BS	32	#define PROM_VADDR 0x000ffd00000ULL
83469015	33	#define APB_SPECIAL_BASE 0x1fe00000000ULL
f930d07e BS	34	#define APB_MEM_BASE 0x1ff00000000ULL
	35	#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
	36	#define PROM_FILENAME "openbios-sparc64"
83469015	37	#define NVRAM_SIZE 0x2000
3475187d FB	38
	39	/* TSC handling */
	40
	41	uint64_t cpu_get_tsc()
	42	{
	43	return qemu_get_clock(vm_clock);
	44	}
	45
	46	int DMA_get_channel_mode (int nchan)
	47	{
	48	return 0;
	49	}
	50	int DMA_read_memory (int nchan, void *buf, int pos, int size)
	51	{
	52	return 0;
	53	}
	54	int DMA_write_memory (int nchan, void *buf, int pos, int size)
	55	{
	56	return 0;
	57	}
	58	void DMA_hold_DREQ (int nchan) {}
	59	void DMA_release_DREQ (int nchan) {}
	60	void DMA_schedule(int nchan) {}
	61	void DMA_run (void) {}
	62	void DMA_init (int high_page_enable) {}
	63	void DMA_register_channel (int nchan,
	64	DMA_transfer_handler transfer_handler,
	65	void *opaque)
	66	{
	67	}
	68
83469015 FB	69	/* NVRAM helpers */
83469015 FB	70	void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
3475187d	71	{
819385c5	72	m48t59_write(nvram, addr, value);
3475187d FB	73	}
3475187d FB	74
83469015	75	uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
3475187d	76	{
819385c5	77	return m48t59_read(nvram, addr);
3475187d FB	78	}
3475187d FB	79
83469015 FB	80	void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
83469015 FB	81	{
819385c5 FB	82	m48t59_write(nvram, addr, value >> 8);
819385c5 FB	83	m48t59_write(nvram, addr + 1, value & 0xFF);
83469015 FB	84	}
	85
	86	uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
	87	{
	88	uint16_t tmp;
	89
819385c5 FB	90	tmp = m48t59_read(nvram, addr) << 8;
819385c5 FB	91	tmp \|= m48t59_read(nvram, addr + 1);
83469015 FB	92
	93	return tmp;
	94	}
	95
	96	void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
	97	{
819385c5 FB	98	m48t59_write(nvram, addr, value >> 24);
	99	m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
	100	m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
	101	m48t59_write(nvram, addr + 3, value & 0xFF);
83469015 FB	102	}
	103
	104	uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
	105	{
	106	uint32_t tmp;
	107
819385c5 FB	108	tmp = m48t59_read(nvram, addr) << 24;
	109	tmp \|= m48t59_read(nvram, addr + 1) << 16;
	110	tmp \|= m48t59_read(nvram, addr + 2) << 8;
	111	tmp \|= m48t59_read(nvram, addr + 3);
83469015 FB	112
	113	return tmp;
	114	}
	115
	116	void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
3475187d FB	117	const unsigned char *str, uint32_t max)
3475187d FB	118	{
83469015	119	int i;
3475187d FB	120
3475187d FB	121	for (i = 0; i < max && str[i] != '\0'; i++) {
819385c5	122	m48t59_write(nvram, addr + i, str[i]);
3475187d	123	}
819385c5	124	m48t59_write(nvram, addr + max - 1, '\0');
3475187d FB	125	}
3475187d FB	126
83469015 FB	127	int NVRAM_get_string (m48t59_t nvram, uint8_t dst, uint16_t addr, int max)
	128	{
	129	int i;
	130
	131	memset(dst, 0, max);
	132	for (i = 0; i < max; i++) {
	133	dst[i] = NVRAM_get_byte(nvram, addr + i);
	134	if (dst[i] == '\0')
	135	break;
	136	}
	137
	138	return i;
	139	}
	140
	141	static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
	142	{
	143	uint16_t tmp;
	144	uint16_t pd, pd1, pd2;
	145
	146	tmp = prev >> 8;
	147	pd = prev ^ value;
	148	pd1 = pd & 0x000F;
	149	pd2 = ((pd >> 4) & 0x000F) ^ pd1;
	150	tmp ^= (pd1 << 3) \| (pd1 << 8);
	151	tmp ^= pd2 \| (pd2 << 7) \| (pd2 << 12);
	152
	153	return tmp;
	154	}
	155
	156	uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
	157	{
	158	uint32_t i;
	159	uint16_t crc = 0xFFFF;
	160	int odd;
	161
	162	odd = count & 1;
	163	count &= ~1;
	164	for (i = 0; i != count; i++) {
f930d07e	165	crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
83469015 FB	166	}
83469015 FB	167	if (odd) {
f930d07e	168	crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
83469015 FB	169	}
	170
	171	return crc;
	172	}
3475187d	173
66508601 BS	174	static uint32_t nvram_set_var (m48t59_t *nvram, uint32_t addr,
	175	const unsigned char *str)
	176	{
	177	uint32_t len;
	178
	179	len = strlen(str) + 1;
	180	NVRAM_set_string(nvram, addr, str, len);
	181
	182	return addr + len;
	183	}
	184
	185	static void nvram_finish_partition (m48t59_t *nvram, uint32_t start,
	186	uint32_t end)
	187	{
	188	unsigned int i, sum;
	189
	190	// Length divided by 16
	191	m48t59_write(nvram, start + 2, ((end - start) >> 12) & 0xff);
	192	m48t59_write(nvram, start + 3, ((end - start) >> 4) & 0xff);
	193	// Checksum
	194	sum = m48t59_read(nvram, start);
	195	for (i = 0; i < 14; i++) {
	196	sum += m48t59_read(nvram, start + 2 + i);
	197	sum = (sum + ((sum & 0xff00) >> 8)) & 0xff;
	198	}
	199	m48t59_write(nvram, start + 1, sum & 0xff);
	200	}
	201
3475187d FB	202	extern int nographic;
3475187d FB	203
83469015 FB	204	int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
	205	const unsigned char *arch,
	206	uint32_t RAM_size, int boot_device,
	207	uint32_t kernel_image, uint32_t kernel_size,
	208	const char *cmdline,
	209	uint32_t initrd_image, uint32_t initrd_size,
	210	uint32_t NVRAM_image,
	211	int width, int height, int depth)
	212	{
	213	uint16_t crc;
66508601 BS	214	unsigned int i;
66508601 BS	215	uint32_t start, end;
83469015 FB	216
	217	/* Set parameters for Open Hack'Ware BIOS */
	218	NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
	219	NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
	220	NVRAM_set_word(nvram, 0x14, NVRAM_size);
	221	NVRAM_set_string(nvram, 0x20, arch, 16);
	222	NVRAM_set_byte(nvram, 0x2f, nographic & 0xff);
	223	NVRAM_set_lword(nvram, 0x30, RAM_size);
	224	NVRAM_set_byte(nvram, 0x34, boot_device);
	225	NVRAM_set_lword(nvram, 0x38, kernel_image);
	226	NVRAM_set_lword(nvram, 0x3C, kernel_size);
3475187d	227	if (cmdline) {
83469015 FB	228	/* XXX: put the cmdline in NVRAM too ? */
	229	strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
	230	NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
	231	NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
	232	} else {
	233	NVRAM_set_lword(nvram, 0x40, 0);
	234	NVRAM_set_lword(nvram, 0x44, 0);
3475187d	235	}
83469015 FB	236	NVRAM_set_lword(nvram, 0x48, initrd_image);
	237	NVRAM_set_lword(nvram, 0x4C, initrd_size);
	238	NVRAM_set_lword(nvram, 0x50, NVRAM_image);
	239
	240	NVRAM_set_word(nvram, 0x54, width);
	241	NVRAM_set_word(nvram, 0x56, height);
	242	NVRAM_set_word(nvram, 0x58, depth);
	243	crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
	244	NVRAM_set_word(nvram, 0xFC, crc);
	245
66508601 BS	246	// OpenBIOS nvram variables
66508601 BS	247	// Variable partition
f19e918d	248	start = 256;
66508601 BS	249	m48t59_write(nvram, start, 0x70);
	250	NVRAM_set_string(nvram, start + 4, "system", 12);
	251
	252	end = start + 16;
	253	for (i = 0; i < nb_prom_envs; i++)
	254	end = nvram_set_var(nvram, end, prom_envs[i]);
	255
	256	m48t59_write(nvram, end++ , 0);
	257	end = start + ((end - start + 15) & ~15);
	258	nvram_finish_partition(nvram, start, end);
	259
	260	// free partition
	261	start = end;
	262	m48t59_write(nvram, start, 0x7f);
	263	NVRAM_set_string(nvram, start + 4, "free", 12);
	264
	265	end = 0x1fd0;
	266	nvram_finish_partition(nvram, start, end);
	267
83469015	268	return 0;
3475187d FB	269	}
	270
	271	void pic_info()
	272	{
	273	}
	274
	275	void irq_info()
	276	{
	277	}
	278
83469015	279	void qemu_system_powerdown(void)
3475187d FB	280	{
	281	}
	282
c68ea704 FB	283	static void main_cpu_reset(void *opaque)
	284	{
	285	CPUState *env = opaque;
20c9f095	286
c68ea704	287	cpu_reset(env);
20c9f095 BS	288	ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
	289	ptimer_run(env->tick, 0);
	290	ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
	291	ptimer_run(env->stick, 0);
	292	ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
	293	ptimer_run(env->hstick, 0);
	294	}
	295
	296	void tick_irq(void *opaque)
	297	{
	298	CPUState *env = opaque;
	299
	300	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
	301	}
	302
	303	void stick_irq(void *opaque)
	304	{
	305	CPUState *env = opaque;
	306
	307	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
	308	}
	309
	310	void hstick_irq(void *opaque)
	311	{
	312	CPUState *env = opaque;
	313
	314	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
c68ea704 FB	315	}
c68ea704 FB	316
f19e918d BS	317	static void dummy_cpu_set_irq(void *opaque, int irq, int level)
	318	{
	319	}
	320
83469015 FB	321	static const int ide_iobase[2] = { 0x1f0, 0x170 };
	322	static const int ide_iobase2[2] = { 0x3f6, 0x376 };
	323	static const int ide_irq[2] = { 14, 15 };
3475187d	324
83469015 FB	325	static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
	326	static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
	327
	328	static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
	329	static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
	330
	331	static fdctrl_t *floppy_controller;
3475187d FB	332
3475187d FB	333	/* Sun4u hardware initialisation */
6ac0e82d	334	static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_device,
3475187d FB	335	DisplayState ds, const char *fd_filename, int snapshot,
3475187d FB	336	const char kernel_filename, const char kernel_cmdline,
94fc95cd	337	const char initrd_filename, const char cpu_model)
3475187d	338	{
c68ea704	339	CPUState *env;
3475187d	340	char buf[1024];
83469015	341	m48t59_t *nvram;
3475187d FB	342	int ret, linux_boot;
3475187d FB	343	unsigned int i;
83469015 FB	344	long prom_offset, initrd_size, kernel_size;
83469015 FB	345	PCIBus *pci_bus;
62724a37	346	const sparc_def_t *def;
20c9f095	347	QEMUBH *bh;
f19e918d	348	qemu_irq *irq;
3475187d FB	349
	350	linux_boot = (kernel_filename != NULL);
	351
62724a37 BS	352	/* init CPUs */
	353	if (cpu_model == NULL)
	354	cpu_model = "TI UltraSparc II";
	355	sparc_find_by_name(cpu_model, &def);
	356	if (def == NULL) {
	357	fprintf(stderr, "Unable to find Sparc CPU definition\n");
	358	exit(1);
	359	}
c68ea704	360	env = cpu_init();
952a328f	361	cpu_sparc_register(env, def, 0);
20c9f095 BS	362	bh = qemu_bh_new(tick_irq, env);
	363	env->tick = ptimer_init(bh);
	364	ptimer_set_period(env->tick, 1ULL);
	365
	366	bh = qemu_bh_new(stick_irq, env);
	367	env->stick = ptimer_init(bh);
	368	ptimer_set_period(env->stick, 1ULL);
	369
	370	bh = qemu_bh_new(hstick_irq, env);
	371	env->hstick = ptimer_init(bh);
	372	ptimer_set_period(env->hstick, 1ULL);
c68ea704 FB	373	register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
c68ea704 FB	374	qemu_register_reset(main_cpu_reset, env);
20c9f095	375	main_cpu_reset(env);
c68ea704	376
3475187d FB	377	/* allocate RAM */
	378	cpu_register_physical_memory(0, ram_size, 0);
	379
83469015	380	prom_offset = ram_size + vga_ram_size;
5fafdf24 TS	381	cpu_register_physical_memory(PROM_ADDR,
5fafdf24 TS	382	(PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
b3783731	383	prom_offset \| IO_MEM_ROM);
3475187d	384
1192dad8 JM	385	if (bios_name == NULL)
	386	bios_name = PROM_FILENAME;
	387	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
f19e918d	388	ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
3475187d	389	if (ret < 0) {
f930d07e BS	390	fprintf(stderr, "qemu: could not load prom '%s'\n",
	391	buf);
	392	exit(1);
3475187d	393	}
3475187d FB	394
3475187d FB	395	kernel_size = 0;
83469015	396	initrd_size = 0;
3475187d	397	if (linux_boot) {
b3783731	398	/* XXX: put correct offset */
74287114	399	kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
3475187d	400	if (kernel_size < 0)
f930d07e BS	401	kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
	402	if (kernel_size < 0)
	403	kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
3475187d	404	if (kernel_size < 0) {
5fafdf24	405	fprintf(stderr, "qemu: could not load kernel '%s'\n",
3475187d	406	kernel_filename);
f930d07e	407	exit(1);
3475187d FB	408	}
	409
	410	/* load initrd */
3475187d FB	411	if (initrd_filename) {
	412	initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
	413	if (initrd_size < 0) {
5fafdf24	414	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
3475187d FB	415	initrd_filename);
	416	exit(1);
	417	}
	418	}
	419	if (initrd_size > 0) {
f930d07e BS	420	for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
	421	if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
	422	== 0x48647253) { // HdrS
	423	stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
	424	stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
	425	break;
	426	}
	427	}
3475187d FB	428	}
3475187d FB	429	}
502a5395	430	pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
83469015	431	isa_mem_base = VGA_BASE;
75956cf0	432	pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
83469015 FB	433
	434	for(i = 0; i < MAX_SERIAL_PORTS; i++) {
	435	if (serial_hds[i]) {
d537cf6c	436	serial_init(serial_io[i], NULL/serial_irq[i]/, serial_hds[i]);
83469015 FB	437	}
	438	}
	439
	440	for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
	441	if (parallel_hds[i]) {
d537cf6c	442	parallel_init(parallel_io[i], NULL/parallel_irq[i]/, parallel_hds[i]);
83469015 FB	443	}
	444	}
	445
	446	for(i = 0; i < nb_nics; i++) {
a41b2ff2 PB	447	if (!nd_table[i].model)
a41b2ff2 PB	448	nd_table[i].model = "ne2k_pci";
f930d07e	449	pci_nic_init(pci_bus, &nd_table[i], -1);
83469015 FB	450	}
83469015 FB	451
f19e918d BS	452	irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
	453	// XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
	454	pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
d537cf6c PB	455	/* FIXME: wire up interrupts. */
	456	i8042_init(NULL/1/, NULL/12/, 0x60);
	457	floppy_controller = fdctrl_init(NULL/6/, 2, 0, 0x3f0, fd_table);
	458	nvram = m48t59_init(NULL/8/, 0, 0x0074, NVRAM_SIZE, 59);
6ac0e82d	459	sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device[0],
83469015 FB	460	KERNEL_LOAD_ADDR, kernel_size,
	461	kernel_cmdline,
	462	INITRD_LOAD_ADDR, initrd_size,
	463	/* XXX: need an option to load a NVRAM image */
	464	0,
	465	graphic_width, graphic_height, graphic_depth);
	466
3475187d FB	467	}
	468
	469	QEMUMachine sun4u_machine = {
	470	"sun4u",
	471	"Sun4u platform",
	472	sun4u_init,
	473	};