]>
Commit | Line | Data |
---|---|---|
3475187d FB |
1 | /* |
2 | * QEMU Sun4u System Emulator | |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
26 | #include "pc.h" | |
27 | #include "nvram.h" | |
28 | #include "fdc.h" | |
29 | #include "net.h" | |
30 | #include "qemu-timer.h" | |
31 | #include "sysemu.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
3475187d | 34 | |
83469015 FB |
35 | #define KERNEL_LOAD_ADDR 0x00404000 |
36 | #define CMDLINE_ADDR 0x003ff000 | |
37 | #define INITRD_LOAD_ADDR 0x00300000 | |
ac2e9d66 | 38 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e BS |
39 | #define PROM_ADDR 0x1fff0000000ULL |
40 | #define PROM_VADDR 0x000ffd00000ULL | |
83469015 | 41 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e BS |
42 | #define APB_MEM_BASE 0x1ff00000000ULL |
43 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) | |
44 | #define PROM_FILENAME "openbios-sparc64" | |
83469015 | 45 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 46 | #define MAX_IDE_BUS 2 |
3475187d | 47 | |
3475187d FB |
48 | int DMA_get_channel_mode (int nchan) |
49 | { | |
50 | return 0; | |
51 | } | |
52 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
53 | { | |
54 | return 0; | |
55 | } | |
56 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
57 | { | |
58 | return 0; | |
59 | } | |
60 | void DMA_hold_DREQ (int nchan) {} | |
61 | void DMA_release_DREQ (int nchan) {} | |
62 | void DMA_schedule(int nchan) {} | |
63 | void DMA_run (void) {} | |
64 | void DMA_init (int high_page_enable) {} | |
65 | void DMA_register_channel (int nchan, | |
66 | DMA_transfer_handler transfer_handler, | |
67 | void *opaque) | |
68 | { | |
69 | } | |
70 | ||
3475187d FB |
71 | extern int nographic; |
72 | ||
d2c63fc1 BS |
73 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
74 | const unsigned char *arch, | |
6ef05b95 | 75 | ram_addr_t RAM_size, const char *boot_devices, |
d2c63fc1 BS |
76 | uint32_t kernel_image, uint32_t kernel_size, |
77 | const char *cmdline, | |
78 | uint32_t initrd_image, uint32_t initrd_size, | |
79 | uint32_t NVRAM_image, | |
80 | int width, int height, int depth) | |
83469015 | 81 | { |
66508601 BS |
82 | unsigned int i; |
83 | uint32_t start, end; | |
d2c63fc1 BS |
84 | uint8_t image[0x1ff0]; |
85 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ | |
86 | struct sparc_arch_cfg *sparc_header; | |
87 | struct OpenBIOS_nvpart_v1 *part_header; | |
88 | ||
89 | memset(image, '\0', sizeof(image)); | |
90 | ||
91 | // Try to match PPC NVRAM | |
92 | strcpy(header->struct_ident, "QEMU_BIOS"); | |
93 | header->struct_version = cpu_to_be32(3); /* structure v3 */ | |
94 | ||
95 | header->nvram_size = cpu_to_be16(NVRAM_size); | |
96 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t)); | |
97 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); | |
98 | strcpy(header->arch, arch); | |
99 | header->nb_cpus = smp_cpus & 0xff; | |
100 | header->RAM0_base = 0; | |
101 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); | |
102 | strcpy(header->boot_devices, boot_devices); | |
103 | header->nboot_devices = strlen(boot_devices) & 0xff; | |
104 | header->kernel_image = cpu_to_be64((uint64_t)kernel_image); | |
105 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); | |
3475187d | 106 | if (cmdline) { |
83469015 | 107 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
d2c63fc1 BS |
108 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
109 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); | |
3475187d | 110 | } |
d2c63fc1 BS |
111 | header->initrd_image = cpu_to_be64((uint64_t)initrd_image); |
112 | header->initrd_size = cpu_to_be64((uint64_t)initrd_size); | |
113 | header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image); | |
114 | ||
115 | header->width = cpu_to_be16(width); | |
116 | header->height = cpu_to_be16(height); | |
117 | header->depth = cpu_to_be16(depth); | |
118 | if (nographic) | |
119 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); | |
83469015 | 120 | |
d2c63fc1 BS |
121 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); |
122 | ||
123 | // Architecture specific header | |
124 | start = sizeof(ohwcfg_v3_t); | |
125 | sparc_header = (struct sparc_arch_cfg *)&image[start]; | |
126 | sparc_header->valid = 0; | |
127 | start += sizeof(struct sparc_arch_cfg); | |
83469015 | 128 | |
66508601 BS |
129 | // OpenBIOS nvram variables |
130 | // Variable partition | |
d2c63fc1 BS |
131 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
132 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
133 | strcpy(part_header->name, "system"); | |
66508601 | 134 | |
d2c63fc1 | 135 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 136 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
137 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
138 | ||
139 | // End marker | |
140 | image[end++] = '\0'; | |
66508601 | 141 | |
66508601 | 142 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 143 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
144 | |
145 | // free partition | |
146 | start = end; | |
d2c63fc1 BS |
147 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
148 | part_header->signature = OPENBIOS_PART_FREE; | |
149 | strcpy(part_header->name, "free"); | |
66508601 BS |
150 | |
151 | end = 0x1fd0; | |
d2c63fc1 BS |
152 | OpenBIOS_finish_partition(part_header, end - start); |
153 | ||
154 | for (i = 0; i < sizeof(image); i++) | |
155 | m48t59_write(nvram, i, image[i]); | |
66508601 | 156 | |
83469015 | 157 | return 0; |
3475187d FB |
158 | } |
159 | ||
22548760 | 160 | void pic_info(void) |
3475187d FB |
161 | { |
162 | } | |
163 | ||
22548760 | 164 | void irq_info(void) |
3475187d FB |
165 | { |
166 | } | |
167 | ||
83469015 | 168 | void qemu_system_powerdown(void) |
3475187d FB |
169 | { |
170 | } | |
171 | ||
c68ea704 FB |
172 | static void main_cpu_reset(void *opaque) |
173 | { | |
174 | CPUState *env = opaque; | |
20c9f095 | 175 | |
c68ea704 | 176 | cpu_reset(env); |
20c9f095 BS |
177 | ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); |
178 | ptimer_run(env->tick, 0); | |
179 | ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); | |
180 | ptimer_run(env->stick, 0); | |
181 | ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); | |
182 | ptimer_run(env->hstick, 0); | |
183 | } | |
184 | ||
22548760 | 185 | static void tick_irq(void *opaque) |
20c9f095 BS |
186 | { |
187 | CPUState *env = opaque; | |
188 | ||
189 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
190 | } | |
191 | ||
22548760 | 192 | static void stick_irq(void *opaque) |
20c9f095 BS |
193 | { |
194 | CPUState *env = opaque; | |
195 | ||
196 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
197 | } | |
198 | ||
22548760 | 199 | static void hstick_irq(void *opaque) |
20c9f095 BS |
200 | { |
201 | CPUState *env = opaque; | |
202 | ||
203 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
c68ea704 FB |
204 | } |
205 | ||
f19e918d BS |
206 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) |
207 | { | |
208 | } | |
209 | ||
83469015 FB |
210 | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
211 | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; | |
212 | static const int ide_irq[2] = { 14, 15 }; | |
3475187d | 213 | |
83469015 FB |
214 | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
215 | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; | |
216 | ||
217 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; | |
218 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
219 | ||
220 | static fdctrl_t *floppy_controller; | |
3475187d FB |
221 | |
222 | /* Sun4u hardware initialisation */ | |
22548760 | 223 | static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size, |
b881c2c6 BS |
224 | const char *boot_devices, DisplayState *ds, |
225 | const char *kernel_filename, const char *kernel_cmdline, | |
226 | const char *initrd_filename, const char *cpu_model) | |
3475187d | 227 | { |
c68ea704 | 228 | CPUState *env; |
3475187d | 229 | char buf[1024]; |
83469015 | 230 | m48t59_t *nvram; |
3475187d FB |
231 | int ret, linux_boot; |
232 | unsigned int i; | |
83469015 FB |
233 | long prom_offset, initrd_size, kernel_size; |
234 | PCIBus *pci_bus; | |
20c9f095 | 235 | QEMUBH *bh; |
f19e918d | 236 | qemu_irq *irq; |
22548760 | 237 | int drive_index; |
e4bcb14c TS |
238 | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
239 | BlockDriverState *fd[MAX_FD]; | |
3475187d FB |
240 | |
241 | linux_boot = (kernel_filename != NULL); | |
242 | ||
62724a37 BS |
243 | /* init CPUs */ |
244 | if (cpu_model == NULL) | |
245 | cpu_model = "TI UltraSparc II"; | |
aaed909a FB |
246 | env = cpu_init(cpu_model); |
247 | if (!env) { | |
62724a37 BS |
248 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); |
249 | exit(1); | |
250 | } | |
20c9f095 BS |
251 | bh = qemu_bh_new(tick_irq, env); |
252 | env->tick = ptimer_init(bh); | |
253 | ptimer_set_period(env->tick, 1ULL); | |
254 | ||
255 | bh = qemu_bh_new(stick_irq, env); | |
256 | env->stick = ptimer_init(bh); | |
257 | ptimer_set_period(env->stick, 1ULL); | |
258 | ||
259 | bh = qemu_bh_new(hstick_irq, env); | |
260 | env->hstick = ptimer_init(bh); | |
261 | ptimer_set_period(env->hstick, 1ULL); | |
c68ea704 FB |
262 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
263 | qemu_register_reset(main_cpu_reset, env); | |
20c9f095 | 264 | main_cpu_reset(env); |
c68ea704 | 265 | |
3475187d | 266 | /* allocate RAM */ |
22548760 | 267 | cpu_register_physical_memory(0, RAM_size, 0); |
3475187d | 268 | |
22548760 | 269 | prom_offset = RAM_size + vga_ram_size; |
5fafdf24 TS |
270 | cpu_register_physical_memory(PROM_ADDR, |
271 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, | |
b3783731 | 272 | prom_offset | IO_MEM_ROM); |
3475187d | 273 | |
1192dad8 JM |
274 | if (bios_name == NULL) |
275 | bios_name = PROM_FILENAME; | |
276 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
f19e918d | 277 | ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL); |
3475187d | 278 | if (ret < 0) { |
f930d07e BS |
279 | fprintf(stderr, "qemu: could not load prom '%s'\n", |
280 | buf); | |
281 | exit(1); | |
3475187d | 282 | } |
3475187d FB |
283 | |
284 | kernel_size = 0; | |
83469015 | 285 | initrd_size = 0; |
3475187d | 286 | if (linux_boot) { |
b3783731 | 287 | /* XXX: put correct offset */ |
74287114 | 288 | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
3475187d | 289 | if (kernel_size < 0) |
f930d07e BS |
290 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); |
291 | if (kernel_size < 0) | |
292 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
3475187d | 293 | if (kernel_size < 0) { |
5fafdf24 | 294 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
3475187d | 295 | kernel_filename); |
f930d07e | 296 | exit(1); |
3475187d FB |
297 | } |
298 | ||
299 | /* load initrd */ | |
3475187d FB |
300 | if (initrd_filename) { |
301 | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); | |
302 | if (initrd_size < 0) { | |
5fafdf24 | 303 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
3475187d FB |
304 | initrd_filename); |
305 | exit(1); | |
306 | } | |
307 | } | |
308 | if (initrd_size > 0) { | |
f930d07e BS |
309 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
310 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) | |
311 | == 0x48647253) { // HdrS | |
312 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
313 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
314 | break; | |
315 | } | |
316 | } | |
3475187d FB |
317 | } |
318 | } | |
502a5395 | 319 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL); |
83469015 | 320 | isa_mem_base = VGA_BASE; |
22548760 | 321 | pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size, vga_ram_size); |
83469015 FB |
322 | |
323 | for(i = 0; i < MAX_SERIAL_PORTS; i++) { | |
324 | if (serial_hds[i]) { | |
cbf5c748 BS |
325 | serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
326 | serial_hds[i]); | |
83469015 FB |
327 | } |
328 | } | |
329 | ||
330 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
331 | if (parallel_hds[i]) { | |
d537cf6c | 332 | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]); |
83469015 FB |
333 | } |
334 | } | |
335 | ||
336 | for(i = 0; i < nb_nics; i++) { | |
a41b2ff2 PB |
337 | if (!nd_table[i].model) |
338 | nd_table[i].model = "ne2k_pci"; | |
f930d07e | 339 | pci_nic_init(pci_bus, &nd_table[i], -1); |
83469015 FB |
340 | } |
341 | ||
f19e918d | 342 | irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32); |
e4bcb14c TS |
343 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
344 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
345 | exit(1); | |
346 | } | |
347 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
22548760 BS |
348 | drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, |
349 | i % MAX_IDE_DEVS); | |
350 | if (drive_index != -1) | |
351 | hd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
352 | else |
353 | hd[i] = NULL; | |
354 | } | |
355 | ||
356 | // XXX pci_cmd646_ide_init(pci_bus, hd, 1); | |
357 | pci_piix3_ide_init(pci_bus, hd, -1, irq); | |
d537cf6c PB |
358 | /* FIXME: wire up interrupts. */ |
359 | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); | |
e4bcb14c | 360 | for(i = 0; i < MAX_FD; i++) { |
22548760 BS |
361 | drive_index = drive_get_index(IF_FLOPPY, 0, i); |
362 | if (drive_index != -1) | |
363 | fd[i] = drives_table[drive_index].bdrv; | |
e4bcb14c TS |
364 | else |
365 | fd[i] = NULL; | |
366 | } | |
367 | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd); | |
d537cf6c | 368 | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
22548760 | 369 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices, |
83469015 FB |
370 | KERNEL_LOAD_ADDR, kernel_size, |
371 | kernel_cmdline, | |
372 | INITRD_LOAD_ADDR, initrd_size, | |
373 | /* XXX: need an option to load a NVRAM image */ | |
374 | 0, | |
375 | graphic_width, graphic_height, graphic_depth); | |
376 | ||
3475187d FB |
377 | } |
378 | ||
379 | QEMUMachine sun4u_machine = { | |
380 | "sun4u", | |
381 | "Sun4u platform", | |
382 | sun4u_init, | |
7fb4fdcf | 383 | PROM_SIZE_MAX + VGA_RAM_SIZE, |
3475187d | 384 | }; |