[mirror_qemu.git] / hw / sun4u.c

/*
 * QEMU Sun4u System Emulator
 * 
 * Copyright (c) 2005 Fabrice Bellard
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
#include "m48t59.h"

#define KERNEL_LOAD_ADDR     0x00404000
#define CMDLINE_ADDR         0x003ff000
#define INITRD_LOAD_ADDR     0x00300000
#define PROM_SIZE_MAX        (512 * 1024)
#define PROM_ADDR	     0x1fff0000000ULL
#define APB_SPECIAL_BASE     0x1fe00000000ULL
#define APB_MEM_BASE	     0x1ff00000000ULL
#define VGA_BASE	     (APB_MEM_BASE + 0x400000ULL)
#define PROM_FILENAME	     "openbios-sparc64"
#define NVRAM_SIZE           0x2000

/* TSC handling */

uint64_t cpu_get_tsc()
{
    return qemu_get_clock(vm_clock);
}

int DMA_get_channel_mode (int nchan)
{
    return 0;
}
int DMA_read_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
int DMA_write_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(int nchan) {}
void DMA_run (void) {}
void DMA_init (int high_page_enable) {}
void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler,
                           void *opaque)
{
}

/* NVRAM helpers */
void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
{
    m48t59_write(nvram, addr, value);
}

uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
{
    return m48t59_read(nvram, addr);
}

void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
{
    m48t59_write(nvram, addr, value >> 8);
    m48t59_write(nvram, addr + 1, value & 0xFF);
}

uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
{
    uint16_t tmp;

    tmp = m48t59_read(nvram, addr) << 8;
    tmp |= m48t59_read(nvram, addr + 1);

    return tmp;
}

void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
{
    m48t59_write(nvram, addr, value >> 24);
    m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
    m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
    m48t59_write(nvram, addr + 3, value & 0xFF);
}

uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
{
    uint32_t tmp;

    tmp = m48t59_read(nvram, addr) << 24;
    tmp |= m48t59_read(nvram, addr + 1) << 16;
    tmp |= m48t59_read(nvram, addr + 2) << 8;
    tmp |= m48t59_read(nvram, addr + 3);

    return tmp;
}

void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
                       const unsigned char *str, uint32_t max)
{
    int i;

    for (i = 0; i < max && str[i] != '\0'; i++) {
        m48t59_write(nvram, addr + i, str[i]);
    }
    m48t59_write(nvram, addr + max - 1, '\0');
}

int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max)
{
    int i;

    memset(dst, 0, max);
    for (i = 0; i < max; i++) {
        dst[i] = NVRAM_get_byte(nvram, addr + i);
        if (dst[i] == '\0')
            break;
    }

    return i;
}

static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
{
    uint16_t tmp;
    uint16_t pd, pd1, pd2;

    tmp = prev >> 8;
    pd = prev ^ value;
    pd1 = pd & 0x000F;
    pd2 = ((pd >> 4) & 0x000F) ^ pd1;
    tmp ^= (pd1 << 3) | (pd1 << 8);
    tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);

    return tmp;
}

uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
{
    uint32_t i;
    uint16_t crc = 0xFFFF;
    int odd;

    odd = count & 1;
    count &= ~1;
    for (i = 0; i != count; i++) {
	crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
    }
    if (odd) {
	crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
    }

    return crc;
}

extern int nographic;

int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
                          const unsigned char *arch,
                          uint32_t RAM_size, int boot_device,
                          uint32_t kernel_image, uint32_t kernel_size,
                          const char *cmdline,
                          uint32_t initrd_image, uint32_t initrd_size,
                          uint32_t NVRAM_image,
                          int width, int height, int depth)
{
    uint16_t crc;

    /* Set parameters for Open Hack'Ware BIOS */
    NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
    NVRAM_set_lword(nvram,  0x10, 0x00000002); /* structure v2 */
    NVRAM_set_word(nvram,   0x14, NVRAM_size);
    NVRAM_set_string(nvram, 0x20, arch, 16);
    NVRAM_set_byte(nvram,   0x2f, nographic & 0xff);
    NVRAM_set_lword(nvram,  0x30, RAM_size);
    NVRAM_set_byte(nvram,   0x34, boot_device);
    NVRAM_set_lword(nvram,  0x38, kernel_image);
    NVRAM_set_lword(nvram,  0x3C, kernel_size);
    if (cmdline) {
        /* XXX: put the cmdline in NVRAM too ? */
        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
        NVRAM_set_lword(nvram,  0x40, CMDLINE_ADDR);
        NVRAM_set_lword(nvram,  0x44, strlen(cmdline));
    } else {
        NVRAM_set_lword(nvram,  0x40, 0);
        NVRAM_set_lword(nvram,  0x44, 0);
    }
    NVRAM_set_lword(nvram,  0x48, initrd_image);
    NVRAM_set_lword(nvram,  0x4C, initrd_size);
    NVRAM_set_lword(nvram,  0x50, NVRAM_image);

    NVRAM_set_word(nvram,   0x54, width);
    NVRAM_set_word(nvram,   0x56, height);
    NVRAM_set_word(nvram,   0x58, depth);
    crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
    NVRAM_set_word(nvram,  0xFC, crc);

    return 0;
}

void pic_info()
{
}

void irq_info()
{
}

void qemu_system_powerdown(void)
{
}

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;
    cpu_reset(env);
}

static const int ide_iobase[2] = { 0x1f0, 0x170 };
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 14, 15 };

static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };

static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };

static fdctrl_t *floppy_controller;

/* Sun4u hardware initialisation */
static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
             DisplayState *ds, const char **fd_filename, int snapshot,
             const char *kernel_filename, const char *kernel_cmdline,
             const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    char buf[1024];
    m48t59_t *nvram;
    int ret, linux_boot;
    unsigned int i;
    long prom_offset, initrd_size, kernel_size;
    PCIBus *pci_bus;
    const sparc_def_t *def;

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    if (cpu_model == NULL)
        cpu_model = "TI UltraSparc II";
    sparc_find_by_name(cpu_model, &def);
    if (def == NULL) {
        fprintf(stderr, "Unable to find Sparc CPU definition\n");
        exit(1);
    }
    env = cpu_init();
    cpu_sparc_register(env, def);
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
    qemu_register_reset(main_cpu_reset, env);

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, 0);

    prom_offset = ram_size + vga_ram_size;
    cpu_register_physical_memory(PROM_ADDR, 
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, 
                                 prom_offset | IO_MEM_ROM);

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
    ret = load_elf(buf, 0, NULL, NULL, NULL);
    if (ret < 0) {
	fprintf(stderr, "qemu: could not load prom '%s'\n", 
		buf);
	exit(1);
    }

    kernel_size = 0;
    initrd_size = 0;
    if (linux_boot) {
        /* XXX: put correct offset */
        kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
        if (kernel_size < 0)
	    kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
	if (kernel_size < 0)
	    kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n", 
                    kernel_filename);
	    exit(1);
        }

        /* load initrd */
        if (initrd_filename) {
            initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
                        initrd_filename);
                exit(1);
            }
        }
        if (initrd_size > 0) {
	    for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
		if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
		    == 0x48647253) { // HdrS
		    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
		    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
		    break;
		}
	    }
        }
    }
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
    isa_mem_base = VGA_BASE;
    pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);

    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
        if (serial_hds[i]) {
            serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
        }
    }

    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
        if (parallel_hds[i]) {
            parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
        }
    }

    for(i = 0; i < nb_nics; i++) {
        if (!nd_table[i].model)
            nd_table[i].model = "ne2k_pci";
	pci_nic_init(pci_bus, &nd_table[i], -1);
    }

    pci_cmd646_ide_init(pci_bus, bs_table, 1);
    /* FIXME: wire up interrupts.  */
    i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
    floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
    nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
                         KERNEL_LOAD_ADDR, kernel_size,
                         kernel_cmdline,
                         INITRD_LOAD_ADDR, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0,
                         graphic_width, graphic_height, graphic_depth);

}

QEMUMachine sun4u_machine = {
    "sun4u",
    "Sun4u platform",
    sun4u_init,
};
Commit	Line	Data
3475187d FB	1	/*
	2	* QEMU Sun4u System Emulator
	3	*
	4	* Copyright (c) 2005 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
83469015	25	#include "m48t59.h"
3475187d	26
83469015 FB	27	#define KERNEL_LOAD_ADDR 0x00404000
	28	#define CMDLINE_ADDR 0x003ff000
	29	#define INITRD_LOAD_ADDR 0x00300000
75956cf0	30	#define PROM_SIZE_MAX (512 * 1024)
83469015 FB	31	#define PROM_ADDR 0x1fff0000000ULL
	32	#define APB_SPECIAL_BASE 0x1fe00000000ULL
	33	#define APB_MEM_BASE 0x1ff00000000ULL
	34	#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
0986ac3b	35	#define PROM_FILENAME "openbios-sparc64"
83469015	36	#define NVRAM_SIZE 0x2000
3475187d FB	37
	38	/* TSC handling */
	39
	40	uint64_t cpu_get_tsc()
	41	{
	42	return qemu_get_clock(vm_clock);
	43	}
	44
	45	int DMA_get_channel_mode (int nchan)
	46	{
	47	return 0;
	48	}
	49	int DMA_read_memory (int nchan, void *buf, int pos, int size)
	50	{
	51	return 0;
	52	}
	53	int DMA_write_memory (int nchan, void *buf, int pos, int size)
	54	{
	55	return 0;
	56	}
	57	void DMA_hold_DREQ (int nchan) {}
	58	void DMA_release_DREQ (int nchan) {}
	59	void DMA_schedule(int nchan) {}
	60	void DMA_run (void) {}
	61	void DMA_init (int high_page_enable) {}
	62	void DMA_register_channel (int nchan,
	63	DMA_transfer_handler transfer_handler,
	64	void *opaque)
	65	{
	66	}
	67
83469015 FB	68	/* NVRAM helpers */
83469015 FB	69	void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value)
3475187d	70	{
819385c5	71	m48t59_write(nvram, addr, value);
3475187d FB	72	}
3475187d FB	73
83469015	74	uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr)
3475187d	75	{
819385c5	76	return m48t59_read(nvram, addr);
3475187d FB	77	}
3475187d FB	78
83469015 FB	79	void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
83469015 FB	80	{
819385c5 FB	81	m48t59_write(nvram, addr, value >> 8);
819385c5 FB	82	m48t59_write(nvram, addr + 1, value & 0xFF);
83469015 FB	83	}
	84
	85	uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr)
	86	{
	87	uint16_t tmp;
	88
819385c5 FB	89	tmp = m48t59_read(nvram, addr) << 8;
819385c5 FB	90	tmp \|= m48t59_read(nvram, addr + 1);
83469015 FB	91
	92	return tmp;
	93	}
	94
	95	void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
	96	{
819385c5 FB	97	m48t59_write(nvram, addr, value >> 24);
	98	m48t59_write(nvram, addr + 1, (value >> 16) & 0xFF);
	99	m48t59_write(nvram, addr + 2, (value >> 8) & 0xFF);
	100	m48t59_write(nvram, addr + 3, value & 0xFF);
83469015 FB	101	}
	102
	103	uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr)
	104	{
	105	uint32_t tmp;
	106
819385c5 FB	107	tmp = m48t59_read(nvram, addr) << 24;
	108	tmp \|= m48t59_read(nvram, addr + 1) << 16;
	109	tmp \|= m48t59_read(nvram, addr + 2) << 8;
	110	tmp \|= m48t59_read(nvram, addr + 3);
83469015 FB	111
	112	return tmp;
	113	}
	114
	115	void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
3475187d FB	116	const unsigned char *str, uint32_t max)
3475187d FB	117	{
83469015	118	int i;
3475187d FB	119
3475187d FB	120	for (i = 0; i < max && str[i] != '\0'; i++) {
819385c5	121	m48t59_write(nvram, addr + i, str[i]);
3475187d	122	}
819385c5	123	m48t59_write(nvram, addr + max - 1, '\0');
3475187d FB	124	}
3475187d FB	125
83469015 FB	126	int NVRAM_get_string (m48t59_t nvram, uint8_t dst, uint16_t addr, int max)
	127	{
	128	int i;
	129
	130	memset(dst, 0, max);
	131	for (i = 0; i < max; i++) {
	132	dst[i] = NVRAM_get_byte(nvram, addr + i);
	133	if (dst[i] == '\0')
	134	break;
	135	}
	136
	137	return i;
	138	}
	139
	140	static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
	141	{
	142	uint16_t tmp;
	143	uint16_t pd, pd1, pd2;
	144
	145	tmp = prev >> 8;
	146	pd = prev ^ value;
	147	pd1 = pd & 0x000F;
	148	pd2 = ((pd >> 4) & 0x000F) ^ pd1;
	149	tmp ^= (pd1 << 3) \| (pd1 << 8);
	150	tmp ^= pd2 \| (pd2 << 7) \| (pd2 << 12);
	151
	152	return tmp;
	153	}
	154
	155	uint16_t NVRAM_compute_crc (m48t59_t *nvram, uint32_t start, uint32_t count)
	156	{
	157	uint32_t i;
	158	uint16_t crc = 0xFFFF;
	159	int odd;
	160
	161	odd = count & 1;
	162	count &= ~1;
	163	for (i = 0; i != count; i++) {
	164	crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
	165	}
	166	if (odd) {
	167	crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
	168	}
	169
	170	return crc;
	171	}
3475187d FB	172
	173	extern int nographic;
	174
83469015 FB	175	int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
	176	const unsigned char *arch,
	177	uint32_t RAM_size, int boot_device,
	178	uint32_t kernel_image, uint32_t kernel_size,
	179	const char *cmdline,
	180	uint32_t initrd_image, uint32_t initrd_size,
	181	uint32_t NVRAM_image,
	182	int width, int height, int depth)
	183	{
	184	uint16_t crc;
	185
	186	/* Set parameters for Open Hack'Ware BIOS */
	187	NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
	188	NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
	189	NVRAM_set_word(nvram, 0x14, NVRAM_size);
	190	NVRAM_set_string(nvram, 0x20, arch, 16);
	191	NVRAM_set_byte(nvram, 0x2f, nographic & 0xff);
	192	NVRAM_set_lword(nvram, 0x30, RAM_size);
	193	NVRAM_set_byte(nvram, 0x34, boot_device);
	194	NVRAM_set_lword(nvram, 0x38, kernel_image);
	195	NVRAM_set_lword(nvram, 0x3C, kernel_size);
3475187d	196	if (cmdline) {
83469015 FB	197	/* XXX: put the cmdline in NVRAM too ? */
	198	strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
	199	NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
	200	NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
	201	} else {
	202	NVRAM_set_lword(nvram, 0x40, 0);
	203	NVRAM_set_lword(nvram, 0x44, 0);
3475187d	204	}
83469015 FB	205	NVRAM_set_lword(nvram, 0x48, initrd_image);
	206	NVRAM_set_lword(nvram, 0x4C, initrd_size);
	207	NVRAM_set_lword(nvram, 0x50, NVRAM_image);
	208
	209	NVRAM_set_word(nvram, 0x54, width);
	210	NVRAM_set_word(nvram, 0x56, height);
	211	NVRAM_set_word(nvram, 0x58, depth);
	212	crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
	213	NVRAM_set_word(nvram, 0xFC, crc);
	214
	215	return 0;
3475187d FB	216	}
	217
	218	void pic_info()
	219	{
	220	}
	221
	222	void irq_info()
	223	{
	224	}
	225
83469015	226	void qemu_system_powerdown(void)
3475187d FB	227	{
	228	}
	229
c68ea704 FB	230	static void main_cpu_reset(void *opaque)
	231	{
	232	CPUState *env = opaque;
	233	cpu_reset(env);
	234	}
	235
83469015 FB	236	static const int ide_iobase[2] = { 0x1f0, 0x170 };
	237	static const int ide_iobase2[2] = { 0x3f6, 0x376 };
	238	static const int ide_irq[2] = { 14, 15 };
3475187d	239
83469015 FB	240	static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
	241	static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
	242
	243	static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
	244	static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
	245
	246	static fdctrl_t *floppy_controller;
3475187d FB	247
	248	/* Sun4u hardware initialisation */
	249	static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,
	250	DisplayState ds, const char *fd_filename, int snapshot,
	251	const char kernel_filename, const char kernel_cmdline,
94fc95cd	252	const char initrd_filename, const char cpu_model)
3475187d	253	{
c68ea704	254	CPUState *env;
3475187d	255	char buf[1024];
83469015	256	m48t59_t *nvram;
3475187d FB	257	int ret, linux_boot;
3475187d FB	258	unsigned int i;
83469015 FB	259	long prom_offset, initrd_size, kernel_size;
83469015 FB	260	PCIBus *pci_bus;
62724a37	261	const sparc_def_t *def;
3475187d FB	262
	263	linux_boot = (kernel_filename != NULL);
	264
62724a37 BS	265	/* init CPUs */
	266	if (cpu_model == NULL)
	267	cpu_model = "TI UltraSparc II";
	268	sparc_find_by_name(cpu_model, &def);
	269	if (def == NULL) {
	270	fprintf(stderr, "Unable to find Sparc CPU definition\n");
	271	exit(1);
	272	}
c68ea704	273	env = cpu_init();
62724a37	274	cpu_sparc_register(env, def);
c68ea704 FB	275	register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
	276	qemu_register_reset(main_cpu_reset, env);
	277
3475187d FB	278	/* allocate RAM */
	279	cpu_register_physical_memory(0, ram_size, 0);
	280
83469015	281	prom_offset = ram_size + vga_ram_size;
b3783731 FB	282	cpu_register_physical_memory(PROM_ADDR,
	283	(PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
	284	prom_offset \| IO_MEM_ROM);
3475187d	285
0986ac3b	286	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAME);
74287114	287	ret = load_elf(buf, 0, NULL, NULL, NULL);
3475187d FB	288	if (ret < 0) {
	289	fprintf(stderr, "qemu: could not load prom '%s'\n",
	290	buf);
	291	exit(1);
	292	}
3475187d FB	293
3475187d FB	294	kernel_size = 0;
83469015	295	initrd_size = 0;
3475187d	296	if (linux_boot) {
b3783731	297	/* XXX: put correct offset */
74287114	298	kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
3475187d FB	299	if (kernel_size < 0)
	300	kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
	301	if (kernel_size < 0)
	302	kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
	303	if (kernel_size < 0) {
	304	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	305	kernel_filename);
	306	exit(1);
	307	}
	308
	309	/* load initrd */
3475187d FB	310	if (initrd_filename) {
	311	initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
	312	if (initrd_size < 0) {
	313	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	314	initrd_filename);
	315	exit(1);
	316	}
	317	}
	318	if (initrd_size > 0) {
	319	for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
	320	if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
	321	== 0x48647253) { // HdrS
	322	stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
	323	stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
	324	break;
	325	}
	326	}
	327	}
	328	}
502a5395	329	pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
83469015	330	isa_mem_base = VGA_BASE;
75956cf0	331	pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
83469015 FB	332
	333	for(i = 0; i < MAX_SERIAL_PORTS; i++) {
	334	if (serial_hds[i]) {
d537cf6c	335	serial_init(serial_io[i], NULL/serial_irq[i]/, serial_hds[i]);
83469015 FB	336	}
	337	}
	338
	339	for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
	340	if (parallel_hds[i]) {
d537cf6c	341	parallel_init(parallel_io[i], NULL/parallel_irq[i]/, parallel_hds[i]);
83469015 FB	342	}
	343	}
	344
	345	for(i = 0; i < nb_nics; i++) {
a41b2ff2 PB	346	if (!nd_table[i].model)
a41b2ff2 PB	347	nd_table[i].model = "ne2k_pci";
abcebc7e	348	pci_nic_init(pci_bus, &nd_table[i], -1);
83469015 FB	349	}
	350
	351	pci_cmd646_ide_init(pci_bus, bs_table, 1);
d537cf6c PB	352	/* FIXME: wire up interrupts. */
	353	i8042_init(NULL/1/, NULL/12/, 0x60);
	354	floppy_controller = fdctrl_init(NULL/6/, 2, 0, 0x3f0, fd_table);
	355	nvram = m48t59_init(NULL/8/, 0, 0x0074, NVRAM_SIZE, 59);
83469015 FB	356	sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_device,
	357	KERNEL_LOAD_ADDR, kernel_size,
	358	kernel_cmdline,
	359	INITRD_LOAD_ADDR, initrd_size,
	360	/* XXX: need an option to load a NVRAM image */
	361	0,
	362	graphic_width, graphic_height, graphic_depth);
	363
3475187d FB	364	}
	365
	366	QEMUMachine sun4u_machine = {
	367	"sun4u",
	368	"Sun4u platform",
	369	sun4u_init,
	370	};