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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "pci.h" | |
26 | #include "pc.h" | |
27 | #include "nvram.h" | |
28 | #include "fdc.h" | |
29 | #include "net.h" | |
30 | #include "qemu-timer.h" | |
31 | #include "sysemu.h" | |
32 | #include "boards.h" | |
d2c63fc1 | 33 | #include "firmware_abi.h" |
3cce6243 | 34 | #include "fw_cfg.h" |
1baffa46 | 35 | #include "sysbus.h" |
977e1244 | 36 | #include "ide.h" |
ca20cf32 BS |
37 | #include "loader.h" |
38 | #include "elf.h" | |
3475187d | 39 | |
9d926598 BS |
40 | //#define DEBUG_IRQ |
41 | ||
42 | #ifdef DEBUG_IRQ | |
001faf32 BS |
43 | #define DPRINTF(fmt, ...) \ |
44 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) | |
9d926598 | 45 | #else |
001faf32 | 46 | #define DPRINTF(fmt, ...) |
9d926598 BS |
47 | #endif |
48 | ||
83469015 FB |
49 | #define KERNEL_LOAD_ADDR 0x00404000 |
50 | #define CMDLINE_ADDR 0x003ff000 | |
51 | #define INITRD_LOAD_ADDR 0x00300000 | |
ac2e9d66 | 52 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 53 | #define PROM_VADDR 0x000ffd00000ULL |
83469015 | 54 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e BS |
55 | #define APB_MEM_BASE 0x1ff00000000ULL |
56 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) | |
57 | #define PROM_FILENAME "openbios-sparc64" | |
83469015 | 58 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 59 | #define MAX_IDE_BUS 2 |
3cce6243 | 60 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
61 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
62 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
63 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 64 | |
9d926598 BS |
65 | #define MAX_PILS 16 |
66 | ||
8fa211e8 BS |
67 | #define TICK_INT_DIS 0x8000000000000000ULL |
68 | #define TICK_MAX 0x7fffffffffffffffULL | |
69 | ||
c7ba218d BS |
70 | struct hwdef { |
71 | const char * const default_cpu_model; | |
905fdcb5 | 72 | uint16_t machine_id; |
e87231d4 BS |
73 | uint64_t prom_addr; |
74 | uint64_t console_serial_base; | |
c7ba218d BS |
75 | }; |
76 | ||
3475187d FB |
77 | int DMA_get_channel_mode (int nchan) |
78 | { | |
79 | return 0; | |
80 | } | |
81 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
82 | { | |
83 | return 0; | |
84 | } | |
85 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
86 | { | |
87 | return 0; | |
88 | } | |
89 | void DMA_hold_DREQ (int nchan) {} | |
90 | void DMA_release_DREQ (int nchan) {} | |
91 | void DMA_schedule(int nchan) {} | |
3475187d FB |
92 | void DMA_init (int high_page_enable) {} |
93 | void DMA_register_channel (int nchan, | |
94 | DMA_transfer_handler transfer_handler, | |
95 | void *opaque) | |
96 | { | |
97 | } | |
98 | ||
513f789f | 99 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
81864572 | 100 | { |
513f789f | 101 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
102 | return 0; |
103 | } | |
104 | ||
c227f099 | 105 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
e7fb1406 | 106 | const char *arch, |
c227f099 | 107 | ram_addr_t RAM_size, |
77f193da | 108 | const char *boot_devices, |
d2c63fc1 BS |
109 | uint32_t kernel_image, uint32_t kernel_size, |
110 | const char *cmdline, | |
111 | uint32_t initrd_image, uint32_t initrd_size, | |
112 | uint32_t NVRAM_image, | |
0d31cb99 BS |
113 | int width, int height, int depth, |
114 | const uint8_t *macaddr) | |
83469015 | 115 | { |
66508601 BS |
116 | unsigned int i; |
117 | uint32_t start, end; | |
d2c63fc1 | 118 | uint8_t image[0x1ff0]; |
d2c63fc1 BS |
119 | struct OpenBIOS_nvpart_v1 *part_header; |
120 | ||
121 | memset(image, '\0', sizeof(image)); | |
122 | ||
513f789f | 123 | start = 0; |
83469015 | 124 | |
66508601 BS |
125 | // OpenBIOS nvram variables |
126 | // Variable partition | |
d2c63fc1 BS |
127 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
128 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 129 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 130 | |
d2c63fc1 | 131 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 132 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
133 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
134 | ||
135 | // End marker | |
136 | image[end++] = '\0'; | |
66508601 | 137 | |
66508601 | 138 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 139 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
140 | |
141 | // free partition | |
142 | start = end; | |
d2c63fc1 BS |
143 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
144 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 145 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
146 | |
147 | end = 0x1fd0; | |
d2c63fc1 BS |
148 | OpenBIOS_finish_partition(part_header, end - start); |
149 | ||
0d31cb99 BS |
150 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
151 | ||
d2c63fc1 BS |
152 | for (i = 0; i < sizeof(image); i++) |
153 | m48t59_write(nvram, i, image[i]); | |
66508601 | 154 | |
83469015 | 155 | return 0; |
3475187d | 156 | } |
636aa70a BS |
157 | static unsigned long sun4u_load_kernel(const char *kernel_filename, |
158 | const char *initrd_filename, | |
c227f099 | 159 | ram_addr_t RAM_size, long *initrd_size) |
636aa70a BS |
160 | { |
161 | int linux_boot; | |
162 | unsigned int i; | |
163 | long kernel_size; | |
164 | ||
165 | linux_boot = (kernel_filename != NULL); | |
166 | ||
167 | kernel_size = 0; | |
168 | if (linux_boot) { | |
ca20cf32 BS |
169 | int bswap_needed; |
170 | ||
171 | #ifdef BSWAP_NEEDED | |
172 | bswap_needed = 1; | |
173 | #else | |
174 | bswap_needed = 0; | |
175 | #endif | |
176 | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL, | |
177 | 1, ELF_MACHINE, 0); | |
636aa70a BS |
178 | if (kernel_size < 0) |
179 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, | |
ca20cf32 BS |
180 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
181 | TARGET_PAGE_SIZE); | |
636aa70a BS |
182 | if (kernel_size < 0) |
183 | kernel_size = load_image_targphys(kernel_filename, | |
184 | KERNEL_LOAD_ADDR, | |
185 | RAM_size - KERNEL_LOAD_ADDR); | |
186 | if (kernel_size < 0) { | |
187 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
188 | kernel_filename); | |
189 | exit(1); | |
190 | } | |
191 | ||
192 | /* load initrd */ | |
193 | *initrd_size = 0; | |
194 | if (initrd_filename) { | |
195 | *initrd_size = load_image_targphys(initrd_filename, | |
196 | INITRD_LOAD_ADDR, | |
197 | RAM_size - INITRD_LOAD_ADDR); | |
198 | if (*initrd_size < 0) { | |
199 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
200 | initrd_filename); | |
201 | exit(1); | |
202 | } | |
203 | } | |
204 | if (*initrd_size > 0) { | |
205 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
206 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS | |
207 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
208 | stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size); | |
209 | break; | |
210 | } | |
211 | } | |
212 | } | |
213 | } | |
214 | return kernel_size; | |
215 | } | |
3475187d | 216 | |
b4950060 | 217 | void pic_info(Monitor *mon) |
3475187d FB |
218 | { |
219 | } | |
220 | ||
b4950060 | 221 | void irq_info(Monitor *mon) |
3475187d FB |
222 | { |
223 | } | |
224 | ||
9d926598 BS |
225 | void cpu_check_irqs(CPUState *env) |
226 | { | |
227 | uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | | |
228 | ((env->softint & SOFTINT_TIMER) << 14); | |
229 | ||
230 | if (pil && (env->interrupt_index == 0 || | |
231 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
232 | unsigned int i; | |
233 | ||
234 | for (i = 15; i > 0; i--) { | |
235 | if (pil & (1 << i)) { | |
236 | int old_interrupt = env->interrupt_index; | |
237 | ||
238 | env->interrupt_index = TT_EXTINT | i; | |
239 | if (old_interrupt != env->interrupt_index) { | |
240 | DPRINTF("Set CPU IRQ %d\n", i); | |
241 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
242 | } | |
243 | break; | |
244 | } | |
245 | } | |
246 | } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) { | |
247 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); | |
248 | env->interrupt_index = 0; | |
249 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
250 | } | |
251 | } | |
252 | ||
253 | static void cpu_set_irq(void *opaque, int irq, int level) | |
254 | { | |
255 | CPUState *env = opaque; | |
256 | ||
257 | if (level) { | |
258 | DPRINTF("Raise CPU IRQ %d\n", irq); | |
259 | env->halted = 0; | |
260 | env->pil_in |= 1 << irq; | |
261 | cpu_check_irqs(env); | |
262 | } else { | |
263 | DPRINTF("Lower CPU IRQ %d\n", irq); | |
264 | env->pil_in &= ~(1 << irq); | |
265 | cpu_check_irqs(env); | |
266 | } | |
267 | } | |
268 | ||
e87231d4 BS |
269 | typedef struct ResetData { |
270 | CPUState *env; | |
271 | uint64_t reset_addr; | |
272 | } ResetData; | |
273 | ||
c68ea704 FB |
274 | static void main_cpu_reset(void *opaque) |
275 | { | |
e87231d4 BS |
276 | ResetData *s = (ResetData *)opaque; |
277 | CPUState *env = s->env; | |
20c9f095 | 278 | |
c68ea704 | 279 | cpu_reset(env); |
8fa211e8 BS |
280 | env->tick_cmpr = TICK_INT_DIS | 0; |
281 | ptimer_set_limit(env->tick, TICK_MAX, 1); | |
2f43e00e | 282 | ptimer_run(env->tick, 1); |
8fa211e8 BS |
283 | env->stick_cmpr = TICK_INT_DIS | 0; |
284 | ptimer_set_limit(env->stick, TICK_MAX, 1); | |
2f43e00e | 285 | ptimer_run(env->stick, 1); |
8fa211e8 BS |
286 | env->hstick_cmpr = TICK_INT_DIS | 0; |
287 | ptimer_set_limit(env->hstick, TICK_MAX, 1); | |
2f43e00e | 288 | ptimer_run(env->hstick, 1); |
e87231d4 BS |
289 | env->gregs[1] = 0; // Memory start |
290 | env->gregs[2] = ram_size; // Memory size | |
291 | env->gregs[3] = 0; // Machine description XXX | |
292 | env->pc = s->reset_addr; | |
293 | env->npc = env->pc + 4; | |
20c9f095 BS |
294 | } |
295 | ||
22548760 | 296 | static void tick_irq(void *opaque) |
20c9f095 BS |
297 | { |
298 | CPUState *env = opaque; | |
299 | ||
8fa211e8 BS |
300 | if (!(env->tick_cmpr & TICK_INT_DIS)) { |
301 | env->softint |= SOFTINT_TIMER; | |
302 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
303 | } | |
20c9f095 BS |
304 | } |
305 | ||
22548760 | 306 | static void stick_irq(void *opaque) |
20c9f095 BS |
307 | { |
308 | CPUState *env = opaque; | |
309 | ||
8fa211e8 BS |
310 | if (!(env->stick_cmpr & TICK_INT_DIS)) { |
311 | env->softint |= SOFTINT_STIMER; | |
312 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
313 | } | |
20c9f095 BS |
314 | } |
315 | ||
22548760 | 316 | static void hstick_irq(void *opaque) |
20c9f095 BS |
317 | { |
318 | CPUState *env = opaque; | |
319 | ||
8fa211e8 BS |
320 | if (!(env->hstick_cmpr & TICK_INT_DIS)) { |
321 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); | |
322 | } | |
c68ea704 FB |
323 | } |
324 | ||
f4b1a842 BS |
325 | void cpu_tick_set_count(void *opaque, uint64_t count) |
326 | { | |
327 | ptimer_set_count(opaque, -count); | |
328 | } | |
329 | ||
330 | uint64_t cpu_tick_get_count(void *opaque) | |
331 | { | |
332 | return -ptimer_get_count(opaque); | |
333 | } | |
334 | ||
335 | void cpu_tick_set_limit(void *opaque, uint64_t limit) | |
336 | { | |
337 | ptimer_set_limit(opaque, -limit, 0); | |
338 | } | |
339 | ||
83469015 FB |
340 | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
341 | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; | |
342 | ||
c190ea07 BS |
343 | static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
344 | uint32_t addr, uint32_t size, int type) | |
345 | { | |
346 | DPRINTF("Mapping region %d registers at %08x\n", region_num, addr); | |
347 | switch (region_num) { | |
348 | case 0: | |
349 | isa_mmio_init(addr, 0x1000000); | |
350 | break; | |
351 | case 1: | |
352 | isa_mmio_init(addr, 0x800000); | |
353 | break; | |
354 | } | |
355 | } | |
356 | ||
1387fe4a BS |
357 | static void dummy_isa_irq_handler(void *opaque, int n, int level) |
358 | { | |
359 | } | |
360 | ||
c190ea07 BS |
361 | /* EBUS (Eight bit bus) bridge */ |
362 | static void | |
363 | pci_ebus_init(PCIBus *bus, int devfn) | |
364 | { | |
1387fe4a BS |
365 | qemu_irq *isa_irq; |
366 | ||
53e3c4f9 | 367 | pci_create_simple(bus, devfn, "ebus"); |
1387fe4a BS |
368 | isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16); |
369 | isa_bus_irqs(isa_irq); | |
53e3c4f9 | 370 | } |
c190ea07 | 371 | |
81a322d4 | 372 | static int |
53e3c4f9 BS |
373 | pci_ebus_init1(PCIDevice *s) |
374 | { | |
0c5b8d83 BS |
375 | isa_bus_new(&s->qdev); |
376 | ||
deb54399 AL |
377 | pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); |
378 | pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS); | |
c190ea07 BS |
379 | s->config[0x04] = 0x06; // command = bus master, pci mem |
380 | s->config[0x05] = 0x00; | |
381 | s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
382 | s->config[0x07] = 0x03; // status = medium devsel | |
383 | s->config[0x08] = 0x01; // revision | |
384 | s->config[0x09] = 0x00; // programming i/f | |
173a543b | 385 | pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); |
c190ea07 | 386 | s->config[0x0D] = 0x0a; // latency_timer |
6407f373 | 387 | s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type |
c190ea07 | 388 | |
28c2c264 | 389 | pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM, |
c190ea07 | 390 | ebus_mmio_mapfunc); |
28c2c264 | 391 | pci_register_bar(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM, |
c190ea07 | 392 | ebus_mmio_mapfunc); |
81a322d4 | 393 | return 0; |
c190ea07 BS |
394 | } |
395 | ||
53e3c4f9 BS |
396 | static PCIDeviceInfo ebus_info = { |
397 | .qdev.name = "ebus", | |
398 | .qdev.size = sizeof(PCIDevice), | |
399 | .init = pci_ebus_init1, | |
400 | }; | |
401 | ||
402 | static void pci_ebus_register(void) | |
403 | { | |
404 | pci_qdev_register(&ebus_info); | |
405 | } | |
406 | ||
407 | device_init(pci_ebus_register); | |
408 | ||
1baffa46 | 409 | /* Boot PROM (OpenBIOS) */ |
c227f099 | 410 | static void prom_init(target_phys_addr_t addr, const char *bios_name) |
1baffa46 BS |
411 | { |
412 | DeviceState *dev; | |
413 | SysBusDevice *s; | |
414 | char *filename; | |
415 | int ret; | |
416 | ||
417 | dev = qdev_create(NULL, "openprom"); | |
418 | qdev_init(dev); | |
419 | s = sysbus_from_qdev(dev); | |
420 | ||
421 | sysbus_mmio_map(s, 0, addr); | |
422 | ||
423 | /* load boot prom */ | |
424 | if (bios_name == NULL) { | |
425 | bios_name = PROM_FILENAME; | |
426 | } | |
427 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
428 | if (filename) { | |
ca20cf32 BS |
429 | ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL, |
430 | 1, ELF_MACHINE, 0); | |
1baffa46 BS |
431 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
432 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
433 | } | |
434 | qemu_free(filename); | |
435 | } else { | |
436 | ret = -1; | |
437 | } | |
438 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
439 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
440 | exit(1); | |
441 | } | |
442 | } | |
443 | ||
81a322d4 | 444 | static int prom_init1(SysBusDevice *dev) |
1baffa46 | 445 | { |
c227f099 | 446 | ram_addr_t prom_offset; |
1baffa46 BS |
447 | |
448 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); | |
449 | sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); | |
81a322d4 | 450 | return 0; |
1baffa46 BS |
451 | } |
452 | ||
453 | static SysBusDeviceInfo prom_info = { | |
454 | .init = prom_init1, | |
455 | .qdev.name = "openprom", | |
456 | .qdev.size = sizeof(SysBusDevice), | |
457 | .qdev.props = (Property[]) { | |
458 | {/* end of property list */} | |
459 | } | |
460 | }; | |
461 | ||
462 | static void prom_register_devices(void) | |
463 | { | |
464 | sysbus_register_withprop(&prom_info); | |
465 | } | |
466 | ||
467 | device_init(prom_register_devices); | |
468 | ||
bda42033 BS |
469 | |
470 | typedef struct RamDevice | |
471 | { | |
472 | SysBusDevice busdev; | |
04843626 | 473 | uint64_t size; |
bda42033 BS |
474 | } RamDevice; |
475 | ||
476 | /* System RAM */ | |
81a322d4 | 477 | static int ram_init1(SysBusDevice *dev) |
bda42033 | 478 | { |
c227f099 | 479 | ram_addr_t RAM_size, ram_offset; |
bda42033 BS |
480 | RamDevice *d = FROM_SYSBUS(RamDevice, dev); |
481 | ||
482 | RAM_size = d->size; | |
483 | ||
484 | ram_offset = qemu_ram_alloc(RAM_size); | |
485 | sysbus_init_mmio(dev, RAM_size, ram_offset); | |
81a322d4 | 486 | return 0; |
bda42033 BS |
487 | } |
488 | ||
c227f099 | 489 | static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size) |
bda42033 BS |
490 | { |
491 | DeviceState *dev; | |
492 | SysBusDevice *s; | |
493 | RamDevice *d; | |
494 | ||
495 | /* allocate RAM */ | |
496 | dev = qdev_create(NULL, "memory"); | |
497 | s = sysbus_from_qdev(dev); | |
498 | ||
499 | d = FROM_SYSBUS(RamDevice, s); | |
500 | d->size = RAM_size; | |
501 | qdev_init(dev); | |
502 | ||
503 | sysbus_mmio_map(s, 0, addr); | |
504 | } | |
505 | ||
506 | static SysBusDeviceInfo ram_info = { | |
507 | .init = ram_init1, | |
508 | .qdev.name = "memory", | |
509 | .qdev.size = sizeof(RamDevice), | |
510 | .qdev.props = (Property[]) { | |
32a7ee98 GH |
511 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), |
512 | DEFINE_PROP_END_OF_LIST(), | |
bda42033 BS |
513 | } |
514 | }; | |
515 | ||
516 | static void ram_register_devices(void) | |
517 | { | |
518 | sysbus_register_withprop(&ram_info); | |
519 | } | |
520 | ||
521 | device_init(ram_register_devices); | |
522 | ||
7b833f5b | 523 | static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
3475187d | 524 | { |
c68ea704 | 525 | CPUState *env; |
20c9f095 | 526 | QEMUBH *bh; |
e87231d4 | 527 | ResetData *reset_info; |
3475187d | 528 | |
c7ba218d BS |
529 | if (!cpu_model) |
530 | cpu_model = hwdef->default_cpu_model; | |
aaed909a FB |
531 | env = cpu_init(cpu_model); |
532 | if (!env) { | |
62724a37 BS |
533 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); |
534 | exit(1); | |
535 | } | |
20c9f095 BS |
536 | bh = qemu_bh_new(tick_irq, env); |
537 | env->tick = ptimer_init(bh); | |
538 | ptimer_set_period(env->tick, 1ULL); | |
539 | ||
540 | bh = qemu_bh_new(stick_irq, env); | |
541 | env->stick = ptimer_init(bh); | |
542 | ptimer_set_period(env->stick, 1ULL); | |
543 | ||
544 | bh = qemu_bh_new(hstick_irq, env); | |
545 | env->hstick = ptimer_init(bh); | |
546 | ptimer_set_period(env->hstick, 1ULL); | |
e87231d4 BS |
547 | |
548 | reset_info = qemu_mallocz(sizeof(ResetData)); | |
549 | reset_info->env = env; | |
550 | reset_info->reset_addr = hwdef->prom_addr + 0x40ULL; | |
a08d4367 | 551 | qemu_register_reset(main_cpu_reset, reset_info); |
e87231d4 BS |
552 | main_cpu_reset(reset_info); |
553 | // Override warm reset address with cold start address | |
554 | env->pc = hwdef->prom_addr + 0x20ULL; | |
555 | env->npc = env->pc + 4; | |
c68ea704 | 556 | |
7b833f5b BS |
557 | return env; |
558 | } | |
559 | ||
c227f099 | 560 | static void sun4uv_init(ram_addr_t RAM_size, |
7b833f5b BS |
561 | const char *boot_devices, |
562 | const char *kernel_filename, const char *kernel_cmdline, | |
563 | const char *initrd_filename, const char *cpu_model, | |
564 | const struct hwdef *hwdef) | |
565 | { | |
566 | CPUState *env; | |
c227f099 | 567 | m48t59_t *nvram; |
7b833f5b BS |
568 | unsigned int i; |
569 | long initrd_size, kernel_size; | |
570 | PCIBus *pci_bus, *pci_bus2, *pci_bus3; | |
571 | qemu_irq *irq; | |
f455e98c | 572 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 573 | DriveInfo *fd[MAX_FD]; |
7b833f5b BS |
574 | void *fw_cfg; |
575 | ||
7b833f5b BS |
576 | /* init CPUs */ |
577 | env = cpu_devinit(cpu_model, hwdef); | |
578 | ||
bda42033 BS |
579 | /* set up devices */ |
580 | ram_init(0, RAM_size); | |
3475187d | 581 | |
1baffa46 | 582 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 583 | |
7d55273f IK |
584 | |
585 | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | |
586 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, | |
c190ea07 | 587 | &pci_bus3); |
83469015 | 588 | isa_mem_base = VGA_BASE; |
fbe1b595 | 589 | pci_vga_init(pci_bus, 0, 0); |
83469015 | 590 | |
c190ea07 BS |
591 | // XXX Should be pci_bus3 |
592 | pci_ebus_init(pci_bus, -1); | |
593 | ||
e87231d4 BS |
594 | i = 0; |
595 | if (hwdef->console_serial_base) { | |
596 | serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, | |
597 | serial_hds[i], 1); | |
598 | i++; | |
599 | } | |
600 | for(; i < MAX_SERIAL_PORTS; i++) { | |
83469015 | 601 | if (serial_hds[i]) { |
ac0be998 | 602 | serial_isa_init(i, serial_hds[i]); |
83469015 FB |
603 | } |
604 | } | |
605 | ||
606 | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { | |
607 | if (parallel_hds[i]) { | |
021f0674 | 608 | parallel_init(i, parallel_hds[i]); |
83469015 FB |
609 | } |
610 | } | |
611 | ||
cb457d76 | 612 | for(i = 0; i < nb_nics; i++) |
6d53bfd1 | 613 | pci_nic_init(&nd_table[i], "ne2k_pci", NULL); |
83469015 | 614 | |
e4bcb14c TS |
615 | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) { |
616 | fprintf(stderr, "qemu: too many IDE bus\n"); | |
617 | exit(1); | |
618 | } | |
619 | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { | |
f455e98c | 620 | hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, |
751c6a17 | 621 | i % MAX_IDE_DEVS); |
e4bcb14c TS |
622 | } |
623 | ||
3b898dda BS |
624 | pci_cmd646_ide_init(pci_bus, hd, 1); |
625 | ||
2e15e23b | 626 | isa_create_simple("i8042"); |
e4bcb14c | 627 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 628 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 629 | } |
86c86157 | 630 | fdctrl_init_isa(fd); |
f80237d4 | 631 | nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59); |
636aa70a BS |
632 | |
633 | initrd_size = 0; | |
634 | kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename, | |
635 | ram_size, &initrd_size); | |
636 | ||
22548760 | 637 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices, |
0d31cb99 BS |
638 | KERNEL_LOAD_ADDR, kernel_size, |
639 | kernel_cmdline, | |
640 | INITRD_LOAD_ADDR, initrd_size, | |
641 | /* XXX: need an option to load a NVRAM image */ | |
642 | 0, | |
643 | graphic_width, graphic_height, graphic_depth, | |
644 | (uint8_t *)&nd_table[0].macaddr); | |
83469015 | 645 | |
3cce6243 BS |
646 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
647 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); | |
905fdcb5 BS |
648 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
649 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
513f789f BS |
650 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
651 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
652 | if (kernel_cmdline) { | |
653 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); | |
654 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); | |
655 | } else { | |
656 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
657 | } | |
658 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
659 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
660 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]); | |
7589690c BS |
661 | |
662 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
663 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
664 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
665 | ||
513f789f | 666 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
667 | } |
668 | ||
905fdcb5 BS |
669 | enum { |
670 | sun4u_id = 0, | |
671 | sun4v_id = 64, | |
e87231d4 | 672 | niagara_id, |
905fdcb5 BS |
673 | }; |
674 | ||
c7ba218d BS |
675 | static const struct hwdef hwdefs[] = { |
676 | /* Sun4u generic PC-like machine */ | |
677 | { | |
678 | .default_cpu_model = "TI UltraSparc II", | |
905fdcb5 | 679 | .machine_id = sun4u_id, |
e87231d4 BS |
680 | .prom_addr = 0x1fff0000000ULL, |
681 | .console_serial_base = 0, | |
c7ba218d BS |
682 | }, |
683 | /* Sun4v generic PC-like machine */ | |
684 | { | |
685 | .default_cpu_model = "Sun UltraSparc T1", | |
905fdcb5 | 686 | .machine_id = sun4v_id, |
e87231d4 BS |
687 | .prom_addr = 0x1fff0000000ULL, |
688 | .console_serial_base = 0, | |
689 | }, | |
690 | /* Sun4v generic Niagara machine */ | |
691 | { | |
692 | .default_cpu_model = "Sun UltraSparc T1", | |
693 | .machine_id = niagara_id, | |
694 | .prom_addr = 0xfff0000000ULL, | |
695 | .console_serial_base = 0xfff0c2c000ULL, | |
c7ba218d BS |
696 | }, |
697 | }; | |
698 | ||
699 | /* Sun4u hardware initialisation */ | |
c227f099 | 700 | static void sun4u_init(ram_addr_t RAM_size, |
3023f332 | 701 | const char *boot_devices, |
c7ba218d BS |
702 | const char *kernel_filename, const char *kernel_cmdline, |
703 | const char *initrd_filename, const char *cpu_model) | |
704 | { | |
fbe1b595 | 705 | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
c7ba218d BS |
706 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]); |
707 | } | |
708 | ||
709 | /* Sun4v hardware initialisation */ | |
c227f099 | 710 | static void sun4v_init(ram_addr_t RAM_size, |
3023f332 | 711 | const char *boot_devices, |
c7ba218d BS |
712 | const char *kernel_filename, const char *kernel_cmdline, |
713 | const char *initrd_filename, const char *cpu_model) | |
714 | { | |
fbe1b595 | 715 | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
c7ba218d BS |
716 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]); |
717 | } | |
718 | ||
e87231d4 | 719 | /* Niagara hardware initialisation */ |
c227f099 | 720 | static void niagara_init(ram_addr_t RAM_size, |
3023f332 | 721 | const char *boot_devices, |
e87231d4 BS |
722 | const char *kernel_filename, const char *kernel_cmdline, |
723 | const char *initrd_filename, const char *cpu_model) | |
724 | { | |
fbe1b595 | 725 | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
e87231d4 BS |
726 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]); |
727 | } | |
728 | ||
f80f9ec9 | 729 | static QEMUMachine sun4u_machine = { |
66de733b BS |
730 | .name = "sun4u", |
731 | .desc = "Sun4u platform", | |
732 | .init = sun4u_init, | |
1bcee014 | 733 | .max_cpus = 1, // XXX for now |
0c257437 | 734 | .is_default = 1, |
3475187d | 735 | }; |
c7ba218d | 736 | |
f80f9ec9 | 737 | static QEMUMachine sun4v_machine = { |
66de733b BS |
738 | .name = "sun4v", |
739 | .desc = "Sun4v platform", | |
740 | .init = sun4v_init, | |
1bcee014 | 741 | .max_cpus = 1, // XXX for now |
c7ba218d | 742 | }; |
e87231d4 | 743 | |
f80f9ec9 | 744 | static QEMUMachine niagara_machine = { |
e87231d4 BS |
745 | .name = "Niagara", |
746 | .desc = "Sun4v platform, Niagara", | |
747 | .init = niagara_init, | |
1bcee014 | 748 | .max_cpus = 1, // XXX for now |
e87231d4 | 749 | }; |
f80f9ec9 AL |
750 | |
751 | static void sun4u_machine_init(void) | |
752 | { | |
753 | qemu_register_machine(&sun4u_machine); | |
754 | qemu_register_machine(&sun4v_machine); | |
755 | qemu_register_machine(&niagara_machine); | |
756 | } | |
757 | ||
758 | machine_init(sun4u_machine_init); |