[mirror_qemu.git] / hw / sun4u.c

/*
 * QEMU Sun4u System Emulator
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
#include "m48t59.h"
#include "firmware_abi.h"

#define KERNEL_LOAD_ADDR     0x00404000
#define CMDLINE_ADDR         0x003ff000
#define INITRD_LOAD_ADDR     0x00300000
#define PROM_SIZE_MAX        (512 * 1024)
#define PROM_ADDR            0x1fff0000000ULL
#define PROM_VADDR           0x000ffd00000ULL
#define APB_SPECIAL_BASE     0x1fe00000000ULL
#define APB_MEM_BASE         0x1ff00000000ULL
#define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
#define PROM_FILENAME        "openbios-sparc64"
#define NVRAM_SIZE           0x2000

/* TSC handling */

uint64_t cpu_get_tsc()
{
    return qemu_get_clock(vm_clock);
}

int DMA_get_channel_mode (int nchan)
{
    return 0;
}
int DMA_read_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
int DMA_write_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(int nchan) {}
void DMA_run (void) {}
void DMA_init (int high_page_enable) {}
void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler,
                           void *opaque)
{
}

extern int nographic;

static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
                                   const unsigned char *arch,
                                   uint32_t RAM_size, const char *boot_devices,
                                   uint32_t kernel_image, uint32_t kernel_size,
                                   const char *cmdline,
                                   uint32_t initrd_image, uint32_t initrd_size,
                                   uint32_t NVRAM_image,
                                   int width, int height, int depth)
{
    unsigned int i;
    uint32_t start, end;
    uint8_t image[0x1ff0];
    ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
    struct sparc_arch_cfg *sparc_header;
    struct OpenBIOS_nvpart_v1 *part_header;

    memset(image, '\0', sizeof(image));

    // Try to match PPC NVRAM
    strcpy(header->struct_ident, "QEMU_BIOS");
    header->struct_version = cpu_to_be32(3); /* structure v3 */

    header->nvram_size = cpu_to_be16(NVRAM_size);
    header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
    header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
    strcpy(header->arch, arch);
    header->nb_cpus = smp_cpus & 0xff;
    header->RAM0_base = 0;
    header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
    strcpy(header->boot_devices, boot_devices);
    header->nboot_devices = strlen(boot_devices) & 0xff;
    header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
    header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
    if (cmdline) {
        strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
        header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
        header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
    }
    header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
    header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
    header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);

    header->width = cpu_to_be16(width);
    header->height = cpu_to_be16(height);
    header->depth = cpu_to_be16(depth);
    if (nographic)
        header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);

    header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));

    // Architecture specific header
    start = sizeof(ohwcfg_v3_t);
    sparc_header = (struct sparc_arch_cfg *)&image[start];
    sparc_header->valid = 0;
    start += sizeof(struct sparc_arch_cfg);

    // OpenBIOS nvram variables
    // Variable partition
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
    part_header->signature = OPENBIOS_PART_SYSTEM;
    strcpy(part_header->name, "system");

    end = start + sizeof(struct OpenBIOS_nvpart_v1);
    for (i = 0; i < nb_prom_envs; i++)
        end = OpenBIOS_set_var(image, end, prom_envs[i]);

    // End marker
    image[end++] = '\0';

    end = start + ((end - start + 15) & ~15);
    OpenBIOS_finish_partition(part_header, end - start);

    // free partition
    start = end;
    part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
    part_header->signature = OPENBIOS_PART_FREE;
    strcpy(part_header->name, "free");

    end = 0x1fd0;
    OpenBIOS_finish_partition(part_header, end - start);

    for (i = 0; i < sizeof(image); i++)
        m48t59_write(nvram, i, image[i]);

    return 0;
}

void pic_info()
{
}

void irq_info()
{
}

void qemu_system_powerdown(void)
{
}

static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;

    cpu_reset(env);
    ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->tick, 0);
    ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->stick, 0);
    ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
    ptimer_run(env->hstick, 0);
}

void tick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

void stick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

void hstick_irq(void *opaque)
{
    CPUState *env = opaque;

    cpu_interrupt(env, CPU_INTERRUPT_TIMER);
}

static void dummy_cpu_set_irq(void *opaque, int irq, int level)
{
}

static const int ide_iobase[2] = { 0x1f0, 0x170 };
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
static const int ide_irq[2] = { 14, 15 };

static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };

static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };

static fdctrl_t *floppy_controller;

/* Sun4u hardware initialisation */
static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_devices,
             DisplayState *ds, const char **fd_filename, int snapshot,
             const char *kernel_filename, const char *kernel_cmdline,
             const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    char buf[1024];
    m48t59_t *nvram;
    int ret, linux_boot;
    unsigned int i;
    long prom_offset, initrd_size, kernel_size;
    PCIBus *pci_bus;
    QEMUBH *bh;
    qemu_irq *irq;

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    if (cpu_model == NULL)
        cpu_model = "TI UltraSparc II";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find Sparc CPU definition\n");
        exit(1);
    }
    bh = qemu_bh_new(tick_irq, env);
    env->tick = ptimer_init(bh);
    ptimer_set_period(env->tick, 1ULL);

    bh = qemu_bh_new(stick_irq, env);
    env->stick = ptimer_init(bh);
    ptimer_set_period(env->stick, 1ULL);

    bh = qemu_bh_new(hstick_irq, env);
    env->hstick = ptimer_init(bh);
    ptimer_set_period(env->hstick, 1ULL);
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
    qemu_register_reset(main_cpu_reset, env);
    main_cpu_reset(env);

    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, 0);

    prom_offset = ram_size + vga_ram_size;
    cpu_register_physical_memory(PROM_ADDR,
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
                                 prom_offset | IO_MEM_ROM);

    if (bios_name == NULL)
        bios_name = PROM_FILENAME;
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
    ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
    if (ret < 0) {
        fprintf(stderr, "qemu: could not load prom '%s'\n",
                buf);
        exit(1);
    }

    kernel_size = 0;
    initrd_size = 0;
    if (linux_boot) {
        /* XXX: put correct offset */
        kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
        if (kernel_size < 0)
            kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        if (kernel_size < 0)
            kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }

        /* load initrd */
        if (initrd_filename) {
            initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                        initrd_filename);
                exit(1);
            }
        }
        if (initrd_size > 0) {
            for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
                if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
                    == 0x48647253) { // HdrS
                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
                    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
                    break;
                }
            }
        }
    }
    pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
    isa_mem_base = VGA_BASE;
    pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);

    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
        if (serial_hds[i]) {
            serial_init(serial_io[i], NULL/*serial_irq[i]*/, serial_hds[i]);
        }
    }

    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
        if (parallel_hds[i]) {
            parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, parallel_hds[i]);
        }
    }

    for(i = 0; i < nb_nics; i++) {
        if (!nd_table[i].model)
            nd_table[i].model = "ne2k_pci";
        pci_nic_init(pci_bus, &nd_table[i], -1);
    }

    irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
    // XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
    pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
    /* FIXME: wire up interrupts.  */
    i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
    floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd_table);
    nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
    sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_devices,
                         KERNEL_LOAD_ADDR, kernel_size,
                         kernel_cmdline,
                         INITRD_LOAD_ADDR, initrd_size,
                         /* XXX: need an option to load a NVRAM image */
                         0,
                         graphic_width, graphic_height, graphic_depth);

}

QEMUMachine sun4u_machine = {
    "sun4u",
    "Sun4u platform",
    sun4u_init,
};
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sun4u System Emulator
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
83469015	25	#include "m48t59.h"
d2c63fc1	26	#include "firmware_abi.h"
3475187d	27
83469015 FB	28	#define KERNEL_LOAD_ADDR 0x00404000
	29	#define CMDLINE_ADDR 0x003ff000
	30	#define INITRD_LOAD_ADDR 0x00300000
75956cf0	31	#define PROM_SIZE_MAX (512 * 1024)
f930d07e BS	32	#define PROM_ADDR 0x1fff0000000ULL
f930d07e BS	33	#define PROM_VADDR 0x000ffd00000ULL
83469015	34	#define APB_SPECIAL_BASE 0x1fe00000000ULL
f930d07e BS	35	#define APB_MEM_BASE 0x1ff00000000ULL
	36	#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
	37	#define PROM_FILENAME "openbios-sparc64"
83469015	38	#define NVRAM_SIZE 0x2000
3475187d FB	39
	40	/* TSC handling */
	41
	42	uint64_t cpu_get_tsc()
	43	{
	44	return qemu_get_clock(vm_clock);
	45	}
	46
	47	int DMA_get_channel_mode (int nchan)
	48	{
	49	return 0;
	50	}
	51	int DMA_read_memory (int nchan, void *buf, int pos, int size)
	52	{
	53	return 0;
	54	}
	55	int DMA_write_memory (int nchan, void *buf, int pos, int size)
	56	{
	57	return 0;
	58	}
	59	void DMA_hold_DREQ (int nchan) {}
	60	void DMA_release_DREQ (int nchan) {}
	61	void DMA_schedule(int nchan) {}
	62	void DMA_run (void) {}
	63	void DMA_init (int high_page_enable) {}
	64	void DMA_register_channel (int nchan,
	65	DMA_transfer_handler transfer_handler,
	66	void *opaque)
	67	{
	68	}
	69
3475187d FB	70	extern int nographic;
3475187d FB	71
d2c63fc1 BS	72	static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
	73	const unsigned char *arch,
	74	uint32_t RAM_size, const char *boot_devices,
	75	uint32_t kernel_image, uint32_t kernel_size,
	76	const char *cmdline,
	77	uint32_t initrd_image, uint32_t initrd_size,
	78	uint32_t NVRAM_image,
	79	int width, int height, int depth)
83469015	80	{
66508601 BS	81	unsigned int i;
66508601 BS	82	uint32_t start, end;
d2c63fc1 BS	83	uint8_t image[0x1ff0];
	84	ohwcfg_v3_t header = (ohwcfg_v3_t )&image;
	85	struct sparc_arch_cfg *sparc_header;
	86	struct OpenBIOS_nvpart_v1 *part_header;
	87
	88	memset(image, '\0', sizeof(image));
	89
	90	// Try to match PPC NVRAM
	91	strcpy(header->struct_ident, "QEMU_BIOS");
	92	header->struct_version = cpu_to_be32(3); /* structure v3 */
	93
	94	header->nvram_size = cpu_to_be16(NVRAM_size);
	95	header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
	96	header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
	97	strcpy(header->arch, arch);
	98	header->nb_cpus = smp_cpus & 0xff;
	99	header->RAM0_base = 0;
	100	header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
	101	strcpy(header->boot_devices, boot_devices);
	102	header->nboot_devices = strlen(boot_devices) & 0xff;
	103	header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
	104	header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
3475187d	105	if (cmdline) {
83469015	106	strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
d2c63fc1 BS	107	header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
d2c63fc1 BS	108	header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
3475187d	109	}
d2c63fc1 BS	110	header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
	111	header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
	112	header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
	113
	114	header->width = cpu_to_be16(width);
	115	header->height = cpu_to_be16(height);
	116	header->depth = cpu_to_be16(depth);
	117	if (nographic)
	118	header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
83469015	119
d2c63fc1 BS	120	header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
	121
	122	// Architecture specific header
	123	start = sizeof(ohwcfg_v3_t);
	124	sparc_header = (struct sparc_arch_cfg *)&image[start];
	125	sparc_header->valid = 0;
	126	start += sizeof(struct sparc_arch_cfg);
83469015	127
66508601 BS	128	// OpenBIOS nvram variables
66508601 BS	129	// Variable partition
d2c63fc1 BS	130	part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
	131	part_header->signature = OPENBIOS_PART_SYSTEM;
	132	strcpy(part_header->name, "system");
66508601	133
d2c63fc1	134	end = start + sizeof(struct OpenBIOS_nvpart_v1);
66508601	135	for (i = 0; i < nb_prom_envs; i++)
d2c63fc1 BS	136	end = OpenBIOS_set_var(image, end, prom_envs[i]);
	137
	138	// End marker
	139	image[end++] = '\0';
66508601	140
66508601	141	end = start + ((end - start + 15) & ~15);
d2c63fc1	142	OpenBIOS_finish_partition(part_header, end - start);
66508601 BS	143
	144	// free partition
	145	start = end;
d2c63fc1 BS	146	part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
	147	part_header->signature = OPENBIOS_PART_FREE;
	148	strcpy(part_header->name, "free");
66508601 BS	149
66508601 BS	150	end = 0x1fd0;
d2c63fc1 BS	151	OpenBIOS_finish_partition(part_header, end - start);
	152
	153	for (i = 0; i < sizeof(image); i++)
	154	m48t59_write(nvram, i, image[i]);
66508601	155
83469015	156	return 0;
3475187d FB	157	}
	158
	159	void pic_info()
	160	{
	161	}
	162
	163	void irq_info()
	164	{
	165	}
	166
83469015	167	void qemu_system_powerdown(void)
3475187d FB	168	{
	169	}
	170
c68ea704 FB	171	static void main_cpu_reset(void *opaque)
	172	{
	173	CPUState *env = opaque;
20c9f095	174
c68ea704	175	cpu_reset(env);
20c9f095 BS	176	ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
	177	ptimer_run(env->tick, 0);
	178	ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
	179	ptimer_run(env->stick, 0);
	180	ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
	181	ptimer_run(env->hstick, 0);
	182	}
	183
	184	void tick_irq(void *opaque)
	185	{
	186	CPUState *env = opaque;
	187
	188	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
	189	}
	190
	191	void stick_irq(void *opaque)
	192	{
	193	CPUState *env = opaque;
	194
	195	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
	196	}
	197
	198	void hstick_irq(void *opaque)
	199	{
	200	CPUState *env = opaque;
	201
	202	cpu_interrupt(env, CPU_INTERRUPT_TIMER);
c68ea704 FB	203	}
c68ea704 FB	204
f19e918d BS	205	static void dummy_cpu_set_irq(void *opaque, int irq, int level)
	206	{
	207	}
	208
83469015 FB	209	static const int ide_iobase[2] = { 0x1f0, 0x170 };
	210	static const int ide_iobase2[2] = { 0x3f6, 0x376 };
	211	static const int ide_irq[2] = { 14, 15 };
3475187d	212
83469015 FB	213	static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
	214	static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
	215
	216	static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
	217	static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
	218
	219	static fdctrl_t *floppy_controller;
3475187d FB	220
3475187d FB	221	/* Sun4u hardware initialisation */
d2c63fc1	222	static void sun4u_init(int ram_size, int vga_ram_size, const char *boot_devices,
3475187d FB	223	DisplayState ds, const char *fd_filename, int snapshot,
3475187d FB	224	const char kernel_filename, const char kernel_cmdline,
94fc95cd	225	const char initrd_filename, const char cpu_model)
3475187d	226	{
c68ea704	227	CPUState *env;
3475187d	228	char buf[1024];
83469015	229	m48t59_t *nvram;
3475187d FB	230	int ret, linux_boot;
3475187d FB	231	unsigned int i;
83469015 FB	232	long prom_offset, initrd_size, kernel_size;
83469015 FB	233	PCIBus *pci_bus;
20c9f095	234	QEMUBH *bh;
f19e918d	235	qemu_irq *irq;
3475187d FB	236
	237	linux_boot = (kernel_filename != NULL);
	238
62724a37 BS	239	/* init CPUs */
	240	if (cpu_model == NULL)
	241	cpu_model = "TI UltraSparc II";
aaed909a FB	242	env = cpu_init(cpu_model);
aaed909a FB	243	if (!env) {
62724a37 BS	244	fprintf(stderr, "Unable to find Sparc CPU definition\n");
	245	exit(1);
	246	}
20c9f095 BS	247	bh = qemu_bh_new(tick_irq, env);
	248	env->tick = ptimer_init(bh);
	249	ptimer_set_period(env->tick, 1ULL);
	250
	251	bh = qemu_bh_new(stick_irq, env);
	252	env->stick = ptimer_init(bh);
	253	ptimer_set_period(env->stick, 1ULL);
	254
	255	bh = qemu_bh_new(hstick_irq, env);
	256	env->hstick = ptimer_init(bh);
	257	ptimer_set_period(env->hstick, 1ULL);
c68ea704 FB	258	register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
c68ea704 FB	259	qemu_register_reset(main_cpu_reset, env);
20c9f095	260	main_cpu_reset(env);
c68ea704	261
3475187d FB	262	/* allocate RAM */
	263	cpu_register_physical_memory(0, ram_size, 0);
	264
83469015	265	prom_offset = ram_size + vga_ram_size;
5fafdf24 TS	266	cpu_register_physical_memory(PROM_ADDR,
5fafdf24 TS	267	(PROM_SIZE_MAX + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK,
b3783731	268	prom_offset \| IO_MEM_ROM);
3475187d	269
1192dad8 JM	270	if (bios_name == NULL)
	271	bios_name = PROM_FILENAME;
	272	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
f19e918d	273	ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
3475187d	274	if (ret < 0) {
f930d07e BS	275	fprintf(stderr, "qemu: could not load prom '%s'\n",
	276	buf);
	277	exit(1);
3475187d	278	}
3475187d FB	279
3475187d FB	280	kernel_size = 0;
83469015	281	initrd_size = 0;
3475187d	282	if (linux_boot) {
b3783731	283	/* XXX: put correct offset */
74287114	284	kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
3475187d	285	if (kernel_size < 0)
f930d07e BS	286	kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
	287	if (kernel_size < 0)
	288	kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
3475187d	289	if (kernel_size < 0) {
5fafdf24	290	fprintf(stderr, "qemu: could not load kernel '%s'\n",
3475187d	291	kernel_filename);
f930d07e	292	exit(1);
3475187d FB	293	}
	294
	295	/* load initrd */
3475187d FB	296	if (initrd_filename) {
	297	initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
	298	if (initrd_size < 0) {
5fafdf24	299	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
3475187d FB	300	initrd_filename);
	301	exit(1);
	302	}
	303	}
	304	if (initrd_size > 0) {
f930d07e BS	305	for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
	306	if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
	307	== 0x48647253) { // HdrS
	308	stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
	309	stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
	310	break;
	311	}
	312	}
3475187d FB	313	}
3475187d FB	314	}
502a5395	315	pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
83469015	316	isa_mem_base = VGA_BASE;
75956cf0	317	pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
83469015 FB	318
	319	for(i = 0; i < MAX_SERIAL_PORTS; i++) {
	320	if (serial_hds[i]) {
d537cf6c	321	serial_init(serial_io[i], NULL/serial_irq[i]/, serial_hds[i]);
83469015 FB	322	}
	323	}
	324
	325	for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
	326	if (parallel_hds[i]) {
d537cf6c	327	parallel_init(parallel_io[i], NULL/parallel_irq[i]/, parallel_hds[i]);
83469015 FB	328	}
	329	}
	330
	331	for(i = 0; i < nb_nics; i++) {
a41b2ff2 PB	332	if (!nd_table[i].model)
a41b2ff2 PB	333	nd_table[i].model = "ne2k_pci";
f930d07e	334	pci_nic_init(pci_bus, &nd_table[i], -1);
83469015 FB	335	}
83469015 FB	336
f19e918d BS	337	irq = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, 32);
	338	// XXX pci_cmd646_ide_init(pci_bus, bs_table, 1);
	339	pci_piix3_ide_init(pci_bus, bs_table, -1, irq);
d537cf6c PB	340	/* FIXME: wire up interrupts. */
	341	i8042_init(NULL/1/, NULL/12/, 0x60);
	342	floppy_controller = fdctrl_init(NULL/6/, 2, 0, 0x3f0, fd_table);
	343	nvram = m48t59_init(NULL/8/, 0, 0x0074, NVRAM_SIZE, 59);
d2c63fc1	344	sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", ram_size, boot_devices,
83469015 FB	345	KERNEL_LOAD_ADDR, kernel_size,
	346	kernel_cmdline,
	347	INITRD_LOAD_ADDR, initrd_size,
	348	/* XXX: need an option to load a NVRAM image */
	349	0,
	350	graphic_width, graphic_height, graphic_depth);
	351
3475187d FB	352	}
	353
	354	QEMUMachine sun4u_machine = {
	355	"sun4u",
	356	"Sun4u platform",
	357	sun4u_init,
	358	};