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Commit | Line | Data |
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7880febd PB |
1 | /* |
2 | * Toshiba TC6393XB I/O Controller. | |
3 | * Found in Sharp Zaurus SL-6000 (tosa) or some | |
4 | * Toshiba e-Series PDAs. | |
5 | * | |
6 | * Most features are currently unsupported!!! | |
7 | * | |
8 | * This code is licensed under the GNU GPL v2. | |
9 | */ | |
88d2c950 AZ |
10 | #include "hw.h" |
11 | #include "pxa.h" | |
12 | #include "devices.h" | |
a6569fc5 AZ |
13 | #include "flash.h" |
14 | ||
15 | #define IRQ_TC6393_NAND 0 | |
16 | #define IRQ_TC6393_MMC 1 | |
17 | #define IRQ_TC6393_OHCI 2 | |
18 | #define IRQ_TC6393_SERIAL 3 | |
19 | #define IRQ_TC6393_FB 4 | |
20 | ||
21 | #define TC6393XB_NR_IRQS 8 | |
88d2c950 AZ |
22 | |
23 | #define TC6393XB_GPIOS 16 | |
24 | ||
25 | #define SCR_REVID 0x08 /* b Revision ID */ | |
26 | #define SCR_ISR 0x50 /* b Interrupt Status */ | |
27 | #define SCR_IMR 0x52 /* b Interrupt Mask */ | |
28 | #define SCR_IRR 0x54 /* b Interrupt Routing */ | |
29 | #define SCR_GPER 0x60 /* w GP Enable */ | |
30 | #define SCR_GPI_SR(i) (0x64 + (i)) /* b3 GPI Status */ | |
31 | #define SCR_GPI_IMR(i) (0x68 + (i)) /* b3 GPI INT Mask */ | |
32 | #define SCR_GPI_EDER(i) (0x6c + (i)) /* b3 GPI Edge Detect Enable */ | |
33 | #define SCR_GPI_LIR(i) (0x70 + (i)) /* b3 GPI Level Invert */ | |
34 | #define SCR_GPO_DSR(i) (0x78 + (i)) /* b3 GPO Data Set */ | |
35 | #define SCR_GPO_DOECR(i) (0x7c + (i)) /* b3 GPO Data OE Control */ | |
36 | #define SCR_GP_IARCR(i) (0x80 + (i)) /* b3 GP Internal Active Register Control */ | |
37 | #define SCR_GP_IARLCR(i) (0x84 + (i)) /* b3 GP INTERNAL Active Register Level Control */ | |
38 | #define SCR_GPI_BCR(i) (0x88 + (i)) /* b3 GPI Buffer Control */ | |
39 | #define SCR_GPA_IARCR 0x8c /* w GPa Internal Active Register Control */ | |
40 | #define SCR_GPA_IARLCR 0x90 /* w GPa Internal Active Register Level Control */ | |
41 | #define SCR_GPA_BCR 0x94 /* w GPa Buffer Control */ | |
42 | #define SCR_CCR 0x98 /* w Clock Control */ | |
43 | #define SCR_PLL2CR 0x9a /* w PLL2 Control */ | |
44 | #define SCR_PLL1CR 0x9c /* l PLL1 Control */ | |
45 | #define SCR_DIARCR 0xa0 /* b Device Internal Active Register Control */ | |
46 | #define SCR_DBOCR 0xa1 /* b Device Buffer Off Control */ | |
47 | #define SCR_FER 0xe0 /* b Function Enable */ | |
48 | #define SCR_MCR 0xe4 /* w Mode Control */ | |
49 | #define SCR_CONFIG 0xfc /* b Configuration Control */ | |
50 | #define SCR_DEBUG 0xff /* b Debug */ | |
51 | ||
a6569fc5 AZ |
52 | #define NAND_CFG_COMMAND 0x04 /* w Command */ |
53 | #define NAND_CFG_BASE 0x10 /* l Control Base Address */ | |
54 | #define NAND_CFG_INTP 0x3d /* b Interrupt Pin */ | |
55 | #define NAND_CFG_INTE 0x48 /* b Int Enable */ | |
56 | #define NAND_CFG_EC 0x4a /* b Event Control */ | |
57 | #define NAND_CFG_ICC 0x4c /* b Internal Clock Control */ | |
58 | #define NAND_CFG_ECCC 0x5b /* b ECC Control */ | |
59 | #define NAND_CFG_NFTC 0x60 /* b NAND Flash Transaction Control */ | |
60 | #define NAND_CFG_NFM 0x61 /* b NAND Flash Monitor */ | |
61 | #define NAND_CFG_NFPSC 0x62 /* b NAND Flash Power Supply Control */ | |
62 | #define NAND_CFG_NFDC 0x63 /* b NAND Flash Detect Control */ | |
63 | ||
64 | #define NAND_DATA 0x00 /* l Data */ | |
65 | #define NAND_MODE 0x04 /* b Mode */ | |
66 | #define NAND_STATUS 0x05 /* b Status */ | |
67 | #define NAND_ISR 0x06 /* b Interrupt Status */ | |
68 | #define NAND_IMR 0x07 /* b Interrupt Mask */ | |
69 | ||
70 | #define NAND_MODE_WP 0x80 | |
71 | #define NAND_MODE_CE 0x10 | |
72 | #define NAND_MODE_ALE 0x02 | |
73 | #define NAND_MODE_CLE 0x01 | |
74 | #define NAND_MODE_ECC_MASK 0x60 | |
75 | #define NAND_MODE_ECC_EN 0x20 | |
76 | #define NAND_MODE_ECC_READ 0x40 | |
77 | #define NAND_MODE_ECC_RST 0x60 | |
78 | ||
88d2c950 AZ |
79 | struct tc6393xb_s { |
80 | target_phys_addr_t target_base; | |
a6569fc5 AZ |
81 | qemu_irq irq; |
82 | qemu_irq *sub_irqs; | |
88d2c950 AZ |
83 | struct { |
84 | uint8_t ISR; | |
85 | uint8_t IMR; | |
86 | uint8_t IRR; | |
87 | uint16_t GPER; | |
88 | uint8_t GPI_SR[3]; | |
89 | uint8_t GPI_IMR[3]; | |
90 | uint8_t GPI_EDER[3]; | |
91 | uint8_t GPI_LIR[3]; | |
92 | uint8_t GP_IARCR[3]; | |
93 | uint8_t GP_IARLCR[3]; | |
94 | uint8_t GPI_BCR[3]; | |
95 | uint16_t GPA_IARCR; | |
96 | uint16_t GPA_IARLCR; | |
97 | uint16_t CCR; | |
98 | uint16_t PLL2CR; | |
99 | uint32_t PLL1CR; | |
100 | uint8_t DIARCR; | |
101 | uint8_t DBOCR; | |
102 | uint8_t FER; | |
103 | uint16_t MCR; | |
104 | uint8_t CONFIG; | |
105 | uint8_t DEBUG; | |
106 | } scr; | |
107 | uint32_t gpio_dir; | |
108 | uint32_t gpio_level; | |
109 | uint32_t prev_level; | |
110 | qemu_irq handler[TC6393XB_GPIOS]; | |
111 | qemu_irq *gpio_in; | |
a6569fc5 AZ |
112 | |
113 | struct { | |
114 | uint8_t mode; | |
115 | uint8_t isr; | |
116 | uint8_t imr; | |
117 | } nand; | |
118 | int nand_enable; | |
119 | uint32_t nand_phys; | |
120 | struct nand_flash_s *flash; | |
121 | struct ecc_state_s ecc; | |
88d2c950 AZ |
122 | }; |
123 | ||
124 | qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s) | |
125 | { | |
126 | return s->gpio_in; | |
127 | } | |
128 | ||
129 | static void tc6393xb_gpio_set(void *opaque, int line, int level) | |
130 | { | |
131 | // struct tc6393xb_s *s = opaque; | |
132 | ||
133 | if (line > TC6393XB_GPIOS) { | |
134 | printf("%s: No GPIO pin %i\n", __FUNCTION__, line); | |
135 | return; | |
136 | } | |
137 | ||
138 | // FIXME: how does the chip reflect the GPIO input level change? | |
139 | } | |
140 | ||
141 | void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line, | |
142 | qemu_irq handler) | |
143 | { | |
144 | if (line >= TC6393XB_GPIOS) { | |
145 | fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line); | |
146 | return; | |
147 | } | |
148 | ||
149 | s->handler[line] = handler; | |
150 | } | |
151 | ||
152 | static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s) | |
153 | { | |
154 | uint32_t level, diff; | |
155 | int bit; | |
156 | ||
157 | level = s->gpio_level & s->gpio_dir; | |
158 | ||
159 | for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) { | |
160 | bit = ffs(diff) - 1; | |
161 | qemu_set_irq(s->handler[bit], (level >> bit) & 1); | |
162 | } | |
163 | ||
164 | s->prev_level = level; | |
165 | } | |
166 | ||
a6569fc5 AZ |
167 | static void tc6393xb_sub_irq(void *opaque, int line, int level) { |
168 | struct tc6393xb_s *s = opaque; | |
169 | uint8_t isr = s->scr.ISR; | |
170 | if (level) | |
171 | isr |= 1 << line; | |
172 | else | |
173 | isr &= ~(1 << line); | |
174 | s->scr.ISR = isr; | |
175 | qemu_set_irq(s->irq, isr & s->scr.IMR); | |
176 | } | |
177 | ||
88d2c950 AZ |
178 | #define SCR_REG_B(N) \ |
179 | case SCR_ ##N: return s->scr.N | |
180 | #define SCR_REG_W(N) \ | |
181 | case SCR_ ##N: return s->scr.N; \ | |
182 | case SCR_ ##N + 1: return s->scr.N >> 8; | |
183 | #define SCR_REG_L(N) \ | |
184 | case SCR_ ##N: return s->scr.N; \ | |
185 | case SCR_ ##N + 1: return s->scr.N >> 8; \ | |
186 | case SCR_ ##N + 2: return s->scr.N >> 16; \ | |
187 | case SCR_ ##N + 3: return s->scr.N >> 24; | |
188 | #define SCR_REG_A(N) \ | |
189 | case SCR_ ##N(0): return s->scr.N[0]; \ | |
190 | case SCR_ ##N(1): return s->scr.N[1]; \ | |
191 | case SCR_ ##N(2): return s->scr.N[2] | |
192 | ||
a6569fc5 | 193 | static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr) |
88d2c950 | 194 | { |
88d2c950 AZ |
195 | switch (addr) { |
196 | case SCR_REVID: | |
197 | return 3; | |
198 | case SCR_REVID+1: | |
199 | return 0; | |
200 | SCR_REG_B(ISR); | |
201 | SCR_REG_B(IMR); | |
202 | SCR_REG_B(IRR); | |
203 | SCR_REG_W(GPER); | |
204 | SCR_REG_A(GPI_SR); | |
205 | SCR_REG_A(GPI_IMR); | |
206 | SCR_REG_A(GPI_EDER); | |
207 | SCR_REG_A(GPI_LIR); | |
208 | case SCR_GPO_DSR(0): | |
209 | case SCR_GPO_DSR(1): | |
210 | case SCR_GPO_DSR(2): | |
211 | return (s->gpio_level >> ((addr - SCR_GPO_DSR(0)) * 8)) & 0xff; | |
212 | case SCR_GPO_DOECR(0): | |
213 | case SCR_GPO_DOECR(1): | |
214 | case SCR_GPO_DOECR(2): | |
215 | return (s->gpio_dir >> ((addr - SCR_GPO_DOECR(0)) * 8)) & 0xff; | |
216 | SCR_REG_A(GP_IARCR); | |
217 | SCR_REG_A(GP_IARLCR); | |
218 | SCR_REG_A(GPI_BCR); | |
219 | SCR_REG_W(GPA_IARCR); | |
220 | SCR_REG_W(GPA_IARLCR); | |
221 | SCR_REG_W(CCR); | |
222 | SCR_REG_W(PLL2CR); | |
223 | SCR_REG_L(PLL1CR); | |
224 | SCR_REG_B(DIARCR); | |
225 | SCR_REG_B(DBOCR); | |
226 | SCR_REG_B(FER); | |
227 | SCR_REG_W(MCR); | |
228 | SCR_REG_B(CONFIG); | |
229 | SCR_REG_B(DEBUG); | |
230 | } | |
a6569fc5 | 231 | fprintf(stderr, "tc6393xb_scr: unhandled read at %08x\n", (uint32_t) addr); |
88d2c950 AZ |
232 | return 0; |
233 | } | |
234 | #undef SCR_REG_B | |
235 | #undef SCR_REG_W | |
236 | #undef SCR_REG_L | |
237 | #undef SCR_REG_A | |
238 | ||
239 | #define SCR_REG_B(N) \ | |
a6569fc5 | 240 | case SCR_ ##N: s->scr.N = value; return; |
88d2c950 | 241 | #define SCR_REG_W(N) \ |
a6569fc5 AZ |
242 | case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ |
243 | case SCR_ ##N + 1: s->scr.N = (s->scr.N & 0xff) | (value << 8); return | |
88d2c950 | 244 | #define SCR_REG_L(N) \ |
a6569fc5 AZ |
245 | case SCR_ ##N: s->scr.N = (s->scr.N & ~0xff) | (value & 0xff); return; \ |
246 | case SCR_ ##N + 1: s->scr.N = (s->scr.N & ~(0xff << 8)) | (value & (0xff << 8)); return; \ | |
247 | case SCR_ ##N + 2: s->scr.N = (s->scr.N & ~(0xff << 16)) | (value & (0xff << 16)); return; \ | |
248 | case SCR_ ##N + 3: s->scr.N = (s->scr.N & ~(0xff << 24)) | (value & (0xff << 24)); return; | |
88d2c950 | 249 | #define SCR_REG_A(N) \ |
a6569fc5 AZ |
250 | case SCR_ ##N(0): s->scr.N[0] = value; return; \ |
251 | case SCR_ ##N(1): s->scr.N[1] = value; return; \ | |
252 | case SCR_ ##N(2): s->scr.N[2] = value; return | |
88d2c950 | 253 | |
a6569fc5 | 254 | static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) |
88d2c950 | 255 | { |
88d2c950 AZ |
256 | switch (addr) { |
257 | SCR_REG_B(ISR); | |
258 | SCR_REG_B(IMR); | |
259 | SCR_REG_B(IRR); | |
260 | SCR_REG_W(GPER); | |
261 | SCR_REG_A(GPI_SR); | |
262 | SCR_REG_A(GPI_IMR); | |
263 | SCR_REG_A(GPI_EDER); | |
264 | SCR_REG_A(GPI_LIR); | |
265 | case SCR_GPO_DSR(0): | |
266 | case SCR_GPO_DSR(1): | |
267 | case SCR_GPO_DSR(2): | |
268 | s->gpio_level = (s->gpio_level & ~(0xff << ((addr - SCR_GPO_DSR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DSR(0))*8)); | |
269 | tc6393xb_gpio_handler_update(s); | |
a6569fc5 | 270 | return; |
88d2c950 AZ |
271 | case SCR_GPO_DOECR(0): |
272 | case SCR_GPO_DOECR(1): | |
273 | case SCR_GPO_DOECR(2): | |
274 | s->gpio_dir = (s->gpio_dir & ~(0xff << ((addr - SCR_GPO_DOECR(0))*8))) | ((value & 0xff) << ((addr - SCR_GPO_DOECR(0))*8)); | |
275 | tc6393xb_gpio_handler_update(s); | |
a6569fc5 | 276 | return; |
88d2c950 AZ |
277 | SCR_REG_A(GP_IARCR); |
278 | SCR_REG_A(GP_IARLCR); | |
279 | SCR_REG_A(GPI_BCR); | |
280 | SCR_REG_W(GPA_IARCR); | |
281 | SCR_REG_W(GPA_IARLCR); | |
282 | SCR_REG_W(CCR); | |
283 | SCR_REG_W(PLL2CR); | |
284 | SCR_REG_L(PLL1CR); | |
285 | SCR_REG_B(DIARCR); | |
286 | SCR_REG_B(DBOCR); | |
287 | SCR_REG_B(FER); | |
288 | SCR_REG_W(MCR); | |
289 | SCR_REG_B(CONFIG); | |
290 | SCR_REG_B(DEBUG); | |
88d2c950 | 291 | } |
a6569fc5 AZ |
292 | fprintf(stderr, "tc6393xb_scr: unhandled write at %08x: %02x\n", |
293 | (uint32_t) addr, value & 0xff); | |
88d2c950 AZ |
294 | } |
295 | #undef SCR_REG_B | |
296 | #undef SCR_REG_W | |
297 | #undef SCR_REG_L | |
298 | #undef SCR_REG_A | |
299 | ||
a6569fc5 AZ |
300 | static void tc6393xb_nand_irq(struct tc6393xb_s *s) { |
301 | qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND], | |
302 | (s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr)); | |
303 | } | |
304 | ||
305 | static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t addr) { | |
306 | switch (addr) { | |
307 | case NAND_CFG_COMMAND: | |
308 | return s->nand_enable ? 2 : 0; | |
309 | case NAND_CFG_BASE: | |
310 | case NAND_CFG_BASE + 1: | |
311 | case NAND_CFG_BASE + 2: | |
312 | case NAND_CFG_BASE + 3: | |
313 | return s->nand_phys >> (addr - NAND_CFG_BASE); | |
314 | } | |
315 | fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr); | |
316 | return 0; | |
317 | } | |
318 | static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) { | |
319 | switch (addr) { | |
320 | case NAND_CFG_COMMAND: | |
321 | s->nand_enable = (value & 0x2); | |
322 | return; | |
323 | case NAND_CFG_BASE: | |
324 | case NAND_CFG_BASE + 1: | |
325 | case NAND_CFG_BASE + 2: | |
326 | case NAND_CFG_BASE + 3: | |
327 | s->nand_phys &= ~(0xff << ((addr - NAND_CFG_BASE) * 8)); | |
328 | s->nand_phys |= (value & 0xff) << ((addr - NAND_CFG_BASE) * 8); | |
329 | return; | |
330 | } | |
331 | fprintf(stderr, "tc6393xb_nand_cfg: unhandled write at %08x: %02x\n", | |
332 | (uint32_t) addr, value & 0xff); | |
333 | } | |
334 | ||
335 | static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t addr) { | |
336 | switch (addr) { | |
337 | case NAND_DATA + 0: | |
338 | case NAND_DATA + 1: | |
339 | case NAND_DATA + 2: | |
340 | case NAND_DATA + 3: | |
341 | return nand_getio(s->flash); | |
342 | case NAND_MODE: | |
343 | return s->nand.mode; | |
344 | case NAND_STATUS: | |
345 | return 0x14; | |
346 | case NAND_ISR: | |
347 | return s->nand.isr; | |
348 | case NAND_IMR: | |
349 | return s->nand.imr; | |
350 | } | |
351 | fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr); | |
352 | return 0; | |
353 | } | |
354 | static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) { | |
355 | // fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n", | |
356 | // (uint32_t) addr, value & 0xff); | |
357 | switch (addr) { | |
358 | case NAND_DATA + 0: | |
359 | case NAND_DATA + 1: | |
360 | case NAND_DATA + 2: | |
361 | case NAND_DATA + 3: | |
362 | nand_setio(s->flash, value); | |
363 | s->nand.isr &= 1; | |
364 | tc6393xb_nand_irq(s); | |
365 | return; | |
366 | case NAND_MODE: | |
367 | s->nand.mode = value; | |
368 | nand_setpins(s->flash, | |
369 | value & NAND_MODE_CLE, | |
370 | value & NAND_MODE_ALE, | |
371 | !(value & NAND_MODE_CE), | |
372 | value & NAND_MODE_WP, | |
373 | 0); // FIXME: gnd | |
374 | switch (value & NAND_MODE_ECC_MASK) { | |
375 | case NAND_MODE_ECC_RST: | |
376 | ecc_reset(&s->ecc); | |
377 | break; | |
378 | case NAND_MODE_ECC_READ: | |
379 | // FIXME | |
380 | break; | |
381 | case NAND_MODE_ECC_EN: | |
382 | ecc_reset(&s->ecc); | |
383 | } | |
384 | return; | |
385 | case NAND_ISR: | |
386 | s->nand.isr = value; | |
387 | tc6393xb_nand_irq(s); | |
388 | return; | |
389 | case NAND_IMR: | |
390 | s->nand.imr = value; | |
391 | tc6393xb_nand_irq(s); | |
392 | return; | |
393 | } | |
394 | fprintf(stderr, "tc6393xb_nand: unhandled write at %08x: %02x\n", | |
395 | (uint32_t) addr, value & 0xff); | |
396 | } | |
397 | ||
398 | static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { | |
399 | struct tc6393xb_s *s = opaque; | |
400 | addr -= s->target_base; | |
401 | ||
402 | switch (addr >> 8) { | |
403 | case 0: | |
404 | return tc6393xb_scr_readb(s, addr & 0xff); | |
405 | case 1: | |
406 | return tc6393xb_nand_cfg_readb(s, addr & 0xff); | |
407 | }; | |
408 | ||
409 | if ((addr &~0xff) == s->nand_phys && s->nand_enable) { | |
410 | // return tc6393xb_nand_readb(s, addr & 0xff); | |
411 | uint8_t d = tc6393xb_nand_readb(s, addr & 0xff); | |
412 | // fprintf(stderr, "tc6393xb_nand: read at %08x: %02hhx\n", (uint32_t) addr, d); | |
413 | return d; | |
414 | } | |
415 | ||
416 | // fprintf(stderr, "tc6393xb: unhandled read at %08x\n", (uint32_t) addr); | |
417 | return 0; | |
418 | } | |
419 | ||
420 | static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { | |
421 | struct tc6393xb_s *s = opaque; | |
422 | addr -= s->target_base; | |
423 | ||
424 | switch (addr >> 8) { | |
425 | case 0: | |
426 | tc6393xb_scr_writeb(s, addr & 0xff, value); | |
427 | return; | |
428 | case 1: | |
429 | tc6393xb_nand_cfg_writeb(s, addr & 0xff, value); | |
430 | return; | |
431 | }; | |
432 | ||
433 | if ((addr &~0xff) == s->nand_phys && s->nand_enable) | |
434 | tc6393xb_nand_writeb(s, addr & 0xff, value); | |
435 | else | |
436 | fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n", | |
437 | (uint32_t) addr, value & 0xff); | |
438 | } | |
439 | ||
88d2c950 AZ |
440 | static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr) |
441 | { | |
442 | return (tc6393xb_readb(opaque, addr) & 0xff) | | |
443 | (tc6393xb_readb(opaque, addr + 1) << 8); | |
444 | } | |
445 | ||
446 | static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr) | |
447 | { | |
448 | return (tc6393xb_readb(opaque, addr) & 0xff) | | |
449 | ((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) | | |
450 | ((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) | | |
451 | ((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24); | |
452 | } | |
453 | ||
454 | static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value) | |
455 | { | |
456 | tc6393xb_writeb(opaque, addr, value); | |
457 | tc6393xb_writeb(opaque, addr + 1, value >> 8); | |
458 | } | |
459 | ||
460 | static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value) | |
461 | { | |
462 | tc6393xb_writeb(opaque, addr, value); | |
463 | tc6393xb_writeb(opaque, addr + 1, value >> 8); | |
464 | tc6393xb_writeb(opaque, addr + 2, value >> 16); | |
465 | tc6393xb_writeb(opaque, addr + 3, value >> 24); | |
466 | } | |
467 | ||
468 | struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq) | |
469 | { | |
470 | int iomemtype; | |
471 | struct tc6393xb_s *s; | |
472 | CPUReadMemoryFunc *tc6393xb_readfn[] = { | |
473 | tc6393xb_readb, | |
474 | tc6393xb_readw, | |
475 | tc6393xb_readl, | |
476 | }; | |
477 | CPUWriteMemoryFunc *tc6393xb_writefn[] = { | |
478 | tc6393xb_writeb, | |
479 | tc6393xb_writew, | |
480 | tc6393xb_writel, | |
481 | }; | |
482 | ||
483 | s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s)); | |
484 | s->target_base = base; | |
a6569fc5 | 485 | s->irq = irq; |
88d2c950 AZ |
486 | s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); |
487 | ||
a6569fc5 AZ |
488 | s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); |
489 | ||
490 | s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76); | |
491 | ||
88d2c950 AZ |
492 | iomemtype = cpu_register_io_memory(0, tc6393xb_readfn, |
493 | tc6393xb_writefn, s); | |
494 | cpu_register_physical_memory(s->target_base, 0x200000, iomemtype); | |
495 | ||
496 | return s; | |
497 | } |