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Commit | Line | Data |
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420557e8 | 1 | /* |
6f7e9aec | 2 | * QEMU TCX Frame buffer |
5fafdf24 | 3 | * |
6f7e9aec | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
f40070c3 | 24 | |
077805fa | 25 | #include "qemu-common.h" |
28ecbaee PB |
26 | #include "ui/console.h" |
27 | #include "ui/pixel_ops.h" | |
83c9f4ca PB |
28 | #include "hw/sysbus.h" |
29 | #include "hw/qdev-addr.h" | |
420557e8 | 30 | |
420557e8 FB |
31 | #define MAXX 1024 |
32 | #define MAXY 768 | |
6f7e9aec | 33 | #define TCX_DAC_NREGS 16 |
8508b89e BS |
34 | #define TCX_THC_NREGS_8 0x081c |
35 | #define TCX_THC_NREGS_24 0x1000 | |
36 | #define TCX_TEC_NREGS 0x1000 | |
420557e8 | 37 | |
420557e8 | 38 | typedef struct TCXState { |
f40070c3 | 39 | SysBusDevice busdev; |
a8170e5e | 40 | hwaddr addr; |
c78f7137 | 41 | QemuConsole *con; |
8d5f07fa | 42 | uint8_t *vram; |
eee0b836 | 43 | uint32_t *vram24, *cplane; |
d08151bf AK |
44 | MemoryRegion vram_mem; |
45 | MemoryRegion vram_8bit; | |
46 | MemoryRegion vram_24bit; | |
47 | MemoryRegion vram_cplane; | |
48 | MemoryRegion dac; | |
49 | MemoryRegion tec; | |
50 | MemoryRegion thc24; | |
51 | MemoryRegion thc8; | |
52 | ram_addr_t vram24_offset, cplane_offset; | |
ee6847d1 | 53 | uint32_t vram_size; |
21206a10 | 54 | uint32_t palette[256]; |
427a66c3 BS |
55 | uint8_t r[256], g[256], b[256]; |
56 | uint16_t width, height, depth; | |
6f7e9aec | 57 | uint8_t dac_index, dac_state; |
420557e8 FB |
58 | } TCXState; |
59 | ||
d7098135 LC |
60 | static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch, |
61 | Error **errp); | |
62 | static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch, | |
63 | Error **errp); | |
d3ffcafe BS |
64 | |
65 | static void tcx_set_dirty(TCXState *s) | |
66 | { | |
fd4aa979 | 67 | memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY); |
d3ffcafe BS |
68 | } |
69 | ||
70 | static void tcx24_set_dirty(TCXState *s) | |
71 | { | |
fd4aa979 BS |
72 | memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4); |
73 | memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4); | |
d3ffcafe | 74 | } |
95219897 | 75 | |
21206a10 FB |
76 | static void update_palette_entries(TCXState *s, int start, int end) |
77 | { | |
c78f7137 | 78 | DisplaySurface *surface = qemu_console_surface(s->con); |
21206a10 | 79 | int i; |
c78f7137 GH |
80 | |
81 | for (i = start; i < end; i++) { | |
82 | switch (surface_bits_per_pixel(surface)) { | |
21206a10 FB |
83 | default: |
84 | case 8: | |
85 | s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]); | |
86 | break; | |
87 | case 15: | |
8927bcfd | 88 | s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]); |
21206a10 FB |
89 | break; |
90 | case 16: | |
8927bcfd | 91 | s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]); |
21206a10 FB |
92 | break; |
93 | case 32: | |
c78f7137 | 94 | if (is_surface_bgr(surface)) { |
7b5d76da | 95 | s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]); |
c78f7137 | 96 | } else { |
7b5d76da | 97 | s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]); |
c78f7137 | 98 | } |
21206a10 FB |
99 | break; |
100 | } | |
101 | } | |
d3ffcafe BS |
102 | if (s->depth == 24) { |
103 | tcx24_set_dirty(s); | |
104 | } else { | |
105 | tcx_set_dirty(s); | |
106 | } | |
21206a10 FB |
107 | } |
108 | ||
5fafdf24 | 109 | static void tcx_draw_line32(TCXState *s1, uint8_t *d, |
f930d07e | 110 | const uint8_t *s, int width) |
420557e8 | 111 | { |
e80cfcfc FB |
112 | int x; |
113 | uint8_t val; | |
8bdc2159 | 114 | uint32_t *p = (uint32_t *)d; |
e80cfcfc FB |
115 | |
116 | for(x = 0; x < width; x++) { | |
f930d07e | 117 | val = *s++; |
8bdc2159 | 118 | *p++ = s1->palette[val]; |
e80cfcfc | 119 | } |
420557e8 FB |
120 | } |
121 | ||
5fafdf24 | 122 | static void tcx_draw_line16(TCXState *s1, uint8_t *d, |
f930d07e | 123 | const uint8_t *s, int width) |
e80cfcfc FB |
124 | { |
125 | int x; | |
126 | uint8_t val; | |
8bdc2159 | 127 | uint16_t *p = (uint16_t *)d; |
8d5f07fa | 128 | |
e80cfcfc | 129 | for(x = 0; x < width; x++) { |
f930d07e | 130 | val = *s++; |
8bdc2159 | 131 | *p++ = s1->palette[val]; |
e80cfcfc FB |
132 | } |
133 | } | |
134 | ||
5fafdf24 | 135 | static void tcx_draw_line8(TCXState *s1, uint8_t *d, |
f930d07e | 136 | const uint8_t *s, int width) |
420557e8 | 137 | { |
e80cfcfc FB |
138 | int x; |
139 | uint8_t val; | |
140 | ||
141 | for(x = 0; x < width; x++) { | |
f930d07e | 142 | val = *s++; |
21206a10 | 143 | *d++ = s1->palette[val]; |
420557e8 | 144 | } |
420557e8 FB |
145 | } |
146 | ||
688ea2eb BS |
147 | /* |
148 | XXX Could be much more optimal: | |
149 | * detect if line/page/whole screen is in 24 bit mode | |
150 | * if destination is also BGR, use memcpy | |
151 | */ | |
eee0b836 BS |
152 | static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, |
153 | const uint8_t *s, int width, | |
154 | const uint32_t *cplane, | |
155 | const uint32_t *s24) | |
156 | { | |
c78f7137 | 157 | DisplaySurface *surface = qemu_console_surface(s1->con); |
7b5d76da | 158 | int x, bgr, r, g, b; |
688ea2eb | 159 | uint8_t val, *p8; |
eee0b836 BS |
160 | uint32_t *p = (uint32_t *)d; |
161 | uint32_t dval; | |
162 | ||
c78f7137 | 163 | bgr = is_surface_bgr(surface); |
eee0b836 | 164 | for(x = 0; x < width; x++, s++, s24++) { |
688ea2eb BS |
165 | if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) { |
166 | // 24-bit direct, BGR order | |
167 | p8 = (uint8_t *)s24; | |
168 | p8++; | |
169 | b = *p8++; | |
170 | g = *p8++; | |
f7e683b8 | 171 | r = *p8; |
7b5d76da AL |
172 | if (bgr) |
173 | dval = rgb_to_pixel32bgr(r, g, b); | |
174 | else | |
175 | dval = rgb_to_pixel32(r, g, b); | |
eee0b836 BS |
176 | } else { |
177 | val = *s; | |
178 | dval = s1->palette[val]; | |
179 | } | |
180 | *p++ = dval; | |
181 | } | |
182 | } | |
183 | ||
d08151bf | 184 | static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24, |
c227f099 | 185 | ram_addr_t cpage) |
eee0b836 BS |
186 | { |
187 | int ret; | |
eee0b836 | 188 | |
cd7a45c9 BS |
189 | ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE, |
190 | DIRTY_MEMORY_VGA); | |
191 | ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4, | |
192 | DIRTY_MEMORY_VGA); | |
193 | ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4, | |
194 | DIRTY_MEMORY_VGA); | |
eee0b836 BS |
195 | return ret; |
196 | } | |
197 | ||
c227f099 AL |
198 | static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, |
199 | ram_addr_t page_max, ram_addr_t page24, | |
200 | ram_addr_t cpage) | |
eee0b836 | 201 | { |
d08151bf AK |
202 | memory_region_reset_dirty(&ts->vram_mem, |
203 | page_min, page_max + TARGET_PAGE_SIZE, | |
204 | DIRTY_MEMORY_VGA); | |
205 | memory_region_reset_dirty(&ts->vram_mem, | |
206 | page24 + page_min * 4, | |
207 | page24 + page_max * 4 + TARGET_PAGE_SIZE, | |
208 | DIRTY_MEMORY_VGA); | |
209 | memory_region_reset_dirty(&ts->vram_mem, | |
210 | cpage + page_min * 4, | |
211 | cpage + page_max * 4 + TARGET_PAGE_SIZE, | |
212 | DIRTY_MEMORY_VGA); | |
eee0b836 BS |
213 | } |
214 | ||
e80cfcfc FB |
215 | /* Fixed line length 1024 allows us to do nice tricks not possible on |
216 | VGA... */ | |
95219897 | 217 | static void tcx_update_display(void *opaque) |
420557e8 | 218 | { |
e80cfcfc | 219 | TCXState *ts = opaque; |
c78f7137 | 220 | DisplaySurface *surface = qemu_console_surface(ts->con); |
c227f099 | 221 | ram_addr_t page, page_min, page_max; |
550be127 | 222 | int y, y_start, dd, ds; |
e80cfcfc | 223 | uint8_t *d, *s; |
b3ceef24 | 224 | void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width); |
e80cfcfc | 225 | |
c78f7137 | 226 | if (surface_bits_per_pixel(surface) == 0) { |
f930d07e | 227 | return; |
c78f7137 GH |
228 | } |
229 | ||
d08151bf | 230 | page = 0; |
e80cfcfc | 231 | y_start = -1; |
c0c440f3 | 232 | page_min = -1; |
550be127 | 233 | page_max = 0; |
c78f7137 | 234 | d = surface_data(surface); |
6f7e9aec | 235 | s = ts->vram; |
c78f7137 | 236 | dd = surface_stride(surface); |
e80cfcfc FB |
237 | ds = 1024; |
238 | ||
c78f7137 | 239 | switch (surface_bits_per_pixel(surface)) { |
e80cfcfc | 240 | case 32: |
f930d07e BS |
241 | f = tcx_draw_line32; |
242 | break; | |
21206a10 FB |
243 | case 15: |
244 | case 16: | |
f930d07e BS |
245 | f = tcx_draw_line16; |
246 | break; | |
e80cfcfc FB |
247 | default: |
248 | case 8: | |
f930d07e BS |
249 | f = tcx_draw_line8; |
250 | break; | |
e80cfcfc | 251 | case 0: |
f930d07e | 252 | return; |
e80cfcfc | 253 | } |
3b46e624 | 254 | |
6f7e9aec | 255 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { |
cd7a45c9 BS |
256 | if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE, |
257 | DIRTY_MEMORY_VGA)) { | |
f930d07e | 258 | if (y_start < 0) |
e80cfcfc FB |
259 | y_start = y; |
260 | if (page < page_min) | |
261 | page_min = page; | |
262 | if (page > page_max) | |
263 | page_max = page; | |
f930d07e BS |
264 | f(ts, d, s, ts->width); |
265 | d += dd; | |
266 | s += ds; | |
267 | f(ts, d, s, ts->width); | |
268 | d += dd; | |
269 | s += ds; | |
270 | f(ts, d, s, ts->width); | |
271 | d += dd; | |
272 | s += ds; | |
273 | f(ts, d, s, ts->width); | |
274 | d += dd; | |
275 | s += ds; | |
276 | } else { | |
e80cfcfc FB |
277 | if (y_start >= 0) { |
278 | /* flush to display */ | |
c78f7137 | 279 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 280 | ts->width, y - y_start); |
e80cfcfc FB |
281 | y_start = -1; |
282 | } | |
f930d07e BS |
283 | d += dd * 4; |
284 | s += ds * 4; | |
285 | } | |
e80cfcfc FB |
286 | } |
287 | if (y_start >= 0) { | |
f930d07e | 288 | /* flush to display */ |
c78f7137 | 289 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 290 | ts->width, y - y_start); |
e80cfcfc FB |
291 | } |
292 | /* reset modified pages */ | |
c0c440f3 | 293 | if (page_max >= page_min) { |
d08151bf AK |
294 | memory_region_reset_dirty(&ts->vram_mem, |
295 | page_min, page_max + TARGET_PAGE_SIZE, | |
296 | DIRTY_MEMORY_VGA); | |
e80cfcfc | 297 | } |
420557e8 FB |
298 | } |
299 | ||
eee0b836 BS |
300 | static void tcx24_update_display(void *opaque) |
301 | { | |
302 | TCXState *ts = opaque; | |
c78f7137 | 303 | DisplaySurface *surface = qemu_console_surface(ts->con); |
c227f099 | 304 | ram_addr_t page, page_min, page_max, cpage, page24; |
eee0b836 BS |
305 | int y, y_start, dd, ds; |
306 | uint8_t *d, *s; | |
307 | uint32_t *cptr, *s24; | |
308 | ||
c78f7137 | 309 | if (surface_bits_per_pixel(surface) != 32) { |
eee0b836 | 310 | return; |
c78f7137 GH |
311 | } |
312 | ||
d08151bf | 313 | page = 0; |
eee0b836 BS |
314 | page24 = ts->vram24_offset; |
315 | cpage = ts->cplane_offset; | |
316 | y_start = -1; | |
c0c440f3 | 317 | page_min = -1; |
eee0b836 | 318 | page_max = 0; |
c78f7137 | 319 | d = surface_data(surface); |
eee0b836 BS |
320 | s = ts->vram; |
321 | s24 = ts->vram24; | |
322 | cptr = ts->cplane; | |
c78f7137 | 323 | dd = surface_stride(surface); |
eee0b836 BS |
324 | ds = 1024; |
325 | ||
326 | for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, | |
327 | page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { | |
d08151bf | 328 | if (check_dirty(ts, page, page24, cpage)) { |
eee0b836 BS |
329 | if (y_start < 0) |
330 | y_start = y; | |
331 | if (page < page_min) | |
332 | page_min = page; | |
333 | if (page > page_max) | |
334 | page_max = page; | |
335 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); | |
336 | d += dd; | |
337 | s += ds; | |
338 | cptr += ds; | |
339 | s24 += ds; | |
340 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); | |
341 | d += dd; | |
342 | s += ds; | |
343 | cptr += ds; | |
344 | s24 += ds; | |
345 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); | |
346 | d += dd; | |
347 | s += ds; | |
348 | cptr += ds; | |
349 | s24 += ds; | |
350 | tcx24_draw_line32(ts, d, s, ts->width, cptr, s24); | |
351 | d += dd; | |
352 | s += ds; | |
353 | cptr += ds; | |
354 | s24 += ds; | |
355 | } else { | |
356 | if (y_start >= 0) { | |
357 | /* flush to display */ | |
c78f7137 | 358 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 359 | ts->width, y - y_start); |
eee0b836 BS |
360 | y_start = -1; |
361 | } | |
362 | d += dd * 4; | |
363 | s += ds * 4; | |
364 | cptr += ds * 4; | |
365 | s24 += ds * 4; | |
366 | } | |
367 | } | |
368 | if (y_start >= 0) { | |
369 | /* flush to display */ | |
c78f7137 | 370 | dpy_gfx_update(ts->con, 0, y_start, |
a93a4a22 | 371 | ts->width, y - y_start); |
eee0b836 BS |
372 | } |
373 | /* reset modified pages */ | |
c0c440f3 | 374 | if (page_max >= page_min) { |
eee0b836 BS |
375 | reset_dirty(ts, page_min, page_max, page24, cpage); |
376 | } | |
377 | } | |
378 | ||
95219897 | 379 | static void tcx_invalidate_display(void *opaque) |
420557e8 | 380 | { |
e80cfcfc | 381 | TCXState *s = opaque; |
e80cfcfc | 382 | |
d3ffcafe | 383 | tcx_set_dirty(s); |
c78f7137 | 384 | qemu_console_resize(s->con, s->width, s->height); |
420557e8 FB |
385 | } |
386 | ||
eee0b836 BS |
387 | static void tcx24_invalidate_display(void *opaque) |
388 | { | |
389 | TCXState *s = opaque; | |
eee0b836 | 390 | |
d3ffcafe BS |
391 | tcx_set_dirty(s); |
392 | tcx24_set_dirty(s); | |
c78f7137 | 393 | qemu_console_resize(s->con, s->width, s->height); |
eee0b836 BS |
394 | } |
395 | ||
e59fb374 | 396 | static int vmstate_tcx_post_load(void *opaque, int version_id) |
420557e8 FB |
397 | { |
398 | TCXState *s = opaque; | |
3b46e624 | 399 | |
21206a10 | 400 | update_palette_entries(s, 0, 256); |
d3ffcafe BS |
401 | if (s->depth == 24) { |
402 | tcx24_set_dirty(s); | |
403 | } else { | |
404 | tcx_set_dirty(s); | |
405 | } | |
5425a216 | 406 | |
e80cfcfc | 407 | return 0; |
420557e8 FB |
408 | } |
409 | ||
c0c41a4b BS |
410 | static const VMStateDescription vmstate_tcx = { |
411 | .name ="tcx", | |
412 | .version_id = 4, | |
413 | .minimum_version_id = 4, | |
414 | .minimum_version_id_old = 4, | |
752ff2fa | 415 | .post_load = vmstate_tcx_post_load, |
c0c41a4b BS |
416 | .fields = (VMStateField []) { |
417 | VMSTATE_UINT16(height, TCXState), | |
418 | VMSTATE_UINT16(width, TCXState), | |
419 | VMSTATE_UINT16(depth, TCXState), | |
420 | VMSTATE_BUFFER(r, TCXState), | |
421 | VMSTATE_BUFFER(g, TCXState), | |
422 | VMSTATE_BUFFER(b, TCXState), | |
423 | VMSTATE_UINT8(dac_index, TCXState), | |
424 | VMSTATE_UINT8(dac_state, TCXState), | |
425 | VMSTATE_END_OF_LIST() | |
426 | } | |
427 | }; | |
428 | ||
7f23f812 | 429 | static void tcx_reset(DeviceState *d) |
420557e8 | 430 | { |
7f23f812 | 431 | TCXState *s = container_of(d, TCXState, busdev.qdev); |
e80cfcfc FB |
432 | |
433 | /* Initialize palette */ | |
434 | memset(s->r, 0, 256); | |
435 | memset(s->g, 0, 256); | |
436 | memset(s->b, 0, 256); | |
437 | s->r[255] = s->g[255] = s->b[255] = 255; | |
21206a10 | 438 | update_palette_entries(s, 0, 256); |
e80cfcfc | 439 | memset(s->vram, 0, MAXX*MAXY); |
d08151bf AK |
440 | memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), |
441 | DIRTY_MEMORY_VGA); | |
6f7e9aec FB |
442 | s->dac_index = 0; |
443 | s->dac_state = 0; | |
444 | } | |
445 | ||
a8170e5e | 446 | static uint64_t tcx_dac_readl(void *opaque, hwaddr addr, |
d08151bf | 447 | unsigned size) |
6f7e9aec FB |
448 | { |
449 | return 0; | |
450 | } | |
451 | ||
a8170e5e | 452 | static void tcx_dac_writel(void *opaque, hwaddr addr, uint64_t val, |
d08151bf | 453 | unsigned size) |
6f7e9aec FB |
454 | { |
455 | TCXState *s = opaque; | |
6f7e9aec | 456 | |
e64d7d59 | 457 | switch (addr) { |
6f7e9aec | 458 | case 0: |
f930d07e BS |
459 | s->dac_index = val >> 24; |
460 | s->dac_state = 0; | |
461 | break; | |
e64d7d59 | 462 | case 4: |
f930d07e BS |
463 | switch (s->dac_state) { |
464 | case 0: | |
465 | s->r[s->dac_index] = val >> 24; | |
21206a10 | 466 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
f930d07e BS |
467 | s->dac_state++; |
468 | break; | |
469 | case 1: | |
470 | s->g[s->dac_index] = val >> 24; | |
21206a10 | 471 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
f930d07e BS |
472 | s->dac_state++; |
473 | break; | |
474 | case 2: | |
475 | s->b[s->dac_index] = val >> 24; | |
21206a10 | 476 | update_palette_entries(s, s->dac_index, s->dac_index + 1); |
5c8cdbf8 | 477 | s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement |
f930d07e BS |
478 | default: |
479 | s->dac_state = 0; | |
480 | break; | |
481 | } | |
482 | break; | |
6f7e9aec | 483 | default: |
f930d07e | 484 | break; |
6f7e9aec | 485 | } |
420557e8 FB |
486 | } |
487 | ||
d08151bf AK |
488 | static const MemoryRegionOps tcx_dac_ops = { |
489 | .read = tcx_dac_readl, | |
490 | .write = tcx_dac_writel, | |
491 | .endianness = DEVICE_NATIVE_ENDIAN, | |
492 | .valid = { | |
493 | .min_access_size = 4, | |
494 | .max_access_size = 4, | |
495 | }, | |
6f7e9aec FB |
496 | }; |
497 | ||
a8170e5e | 498 | static uint64_t dummy_readl(void *opaque, hwaddr addr, |
d08151bf | 499 | unsigned size) |
8508b89e BS |
500 | { |
501 | return 0; | |
502 | } | |
503 | ||
a8170e5e | 504 | static void dummy_writel(void *opaque, hwaddr addr, |
d08151bf | 505 | uint64_t val, unsigned size) |
8508b89e BS |
506 | { |
507 | } | |
508 | ||
d08151bf AK |
509 | static const MemoryRegionOps dummy_ops = { |
510 | .read = dummy_readl, | |
511 | .write = dummy_writel, | |
512 | .endianness = DEVICE_NATIVE_ENDIAN, | |
513 | .valid = { | |
514 | .min_access_size = 4, | |
515 | .max_access_size = 4, | |
516 | }, | |
8508b89e BS |
517 | }; |
518 | ||
81a322d4 | 519 | static int tcx_init1(SysBusDevice *dev) |
f40070c3 BS |
520 | { |
521 | TCXState *s = FROM_SYSBUS(TCXState, dev); | |
d08151bf | 522 | ram_addr_t vram_offset = 0; |
ee6847d1 | 523 | int size; |
dc828ca1 PB |
524 | uint8_t *vram_base; |
525 | ||
c5705a77 | 526 | memory_region_init_ram(&s->vram_mem, "tcx.vram", |
d08151bf | 527 | s->vram_size * (1 + 4 + 4)); |
c5705a77 | 528 | vmstate_register_ram_global(&s->vram_mem); |
d08151bf | 529 | vram_base = memory_region_get_ram_ptr(&s->vram_mem); |
eee0b836 | 530 | |
f40070c3 | 531 | /* 8-bit plane */ |
eee0b836 | 532 | s->vram = vram_base; |
ee6847d1 | 533 | size = s->vram_size; |
d08151bf AK |
534 | memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit", |
535 | &s->vram_mem, vram_offset, size); | |
750ecd44 | 536 | sysbus_init_mmio(dev, &s->vram_8bit); |
eee0b836 BS |
537 | vram_offset += size; |
538 | vram_base += size; | |
e80cfcfc | 539 | |
f40070c3 | 540 | /* DAC */ |
d08151bf | 541 | memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS); |
750ecd44 | 542 | sysbus_init_mmio(dev, &s->dac); |
eee0b836 | 543 | |
f40070c3 | 544 | /* TEC (dummy) */ |
d08151bf | 545 | memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS); |
750ecd44 | 546 | sysbus_init_mmio(dev, &s->tec); |
f40070c3 | 547 | /* THC: NetBSD writes here even with 8-bit display: dummy */ |
d08151bf AK |
548 | memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24", |
549 | TCX_THC_NREGS_24); | |
750ecd44 | 550 | sysbus_init_mmio(dev, &s->thc24); |
f40070c3 BS |
551 | |
552 | if (s->depth == 24) { | |
553 | /* 24-bit plane */ | |
ee6847d1 | 554 | size = s->vram_size * 4; |
eee0b836 BS |
555 | s->vram24 = (uint32_t *)vram_base; |
556 | s->vram24_offset = vram_offset; | |
d08151bf AK |
557 | memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit", |
558 | &s->vram_mem, vram_offset, size); | |
750ecd44 | 559 | sysbus_init_mmio(dev, &s->vram_24bit); |
eee0b836 BS |
560 | vram_offset += size; |
561 | vram_base += size; | |
562 | ||
f40070c3 | 563 | /* Control plane */ |
ee6847d1 | 564 | size = s->vram_size * 4; |
eee0b836 BS |
565 | s->cplane = (uint32_t *)vram_base; |
566 | s->cplane_offset = vram_offset; | |
d08151bf AK |
567 | memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane", |
568 | &s->vram_mem, vram_offset, size); | |
750ecd44 | 569 | sysbus_init_mmio(dev, &s->vram_cplane); |
f40070c3 | 570 | |
c78f7137 GH |
571 | s->con = graphic_console_init(tcx24_update_display, |
572 | tcx24_invalidate_display, | |
573 | tcx24_screen_dump, NULL, s); | |
eee0b836 | 574 | } else { |
f40070c3 | 575 | /* THC 8 bit (dummy) */ |
d08151bf AK |
576 | memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8", |
577 | TCX_THC_NREGS_8); | |
750ecd44 | 578 | sysbus_init_mmio(dev, &s->thc8); |
f40070c3 | 579 | |
c78f7137 GH |
580 | s->con = graphic_console_init(tcx_update_display, |
581 | tcx_invalidate_display, | |
582 | tcx_screen_dump, NULL, s); | |
eee0b836 | 583 | } |
e80cfcfc | 584 | |
c78f7137 | 585 | qemu_console_resize(s->con, s->width, s->height); |
81a322d4 | 586 | return 0; |
420557e8 FB |
587 | } |
588 | ||
d7098135 LC |
589 | static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch, |
590 | Error **errp) | |
8d5f07fa | 591 | { |
e80cfcfc | 592 | TCXState *s = opaque; |
8d5f07fa | 593 | FILE *f; |
e80cfcfc | 594 | uint8_t *d, *d1, v; |
0ab6b636 | 595 | int ret, y, x; |
8d5f07fa FB |
596 | |
597 | f = fopen(filename, "wb"); | |
0ab6b636 LC |
598 | if (!f) { |
599 | error_setg(errp, "failed to open file '%s': %s", filename, | |
600 | strerror(errno)); | |
e80cfcfc | 601 | return; |
0ab6b636 LC |
602 | } |
603 | ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); | |
604 | if (ret < 0) { | |
605 | goto write_err; | |
606 | } | |
6f7e9aec FB |
607 | d1 = s->vram; |
608 | for(y = 0; y < s->height; y++) { | |
8d5f07fa | 609 | d = d1; |
6f7e9aec | 610 | for(x = 0; x < s->width; x++) { |
8d5f07fa | 611 | v = *d; |
0ab6b636 LC |
612 | ret = fputc(s->r[v], f); |
613 | if (ret == EOF) { | |
614 | goto write_err; | |
615 | } | |
616 | ret = fputc(s->g[v], f); | |
617 | if (ret == EOF) { | |
618 | goto write_err; | |
619 | } | |
620 | ret = fputc(s->b[v], f); | |
621 | if (ret == EOF) { | |
622 | goto write_err; | |
623 | } | |
8d5f07fa FB |
624 | d++; |
625 | } | |
e80cfcfc | 626 | d1 += MAXX; |
8d5f07fa | 627 | } |
0ab6b636 LC |
628 | |
629 | out: | |
8d5f07fa FB |
630 | fclose(f); |
631 | return; | |
0ab6b636 LC |
632 | |
633 | write_err: | |
634 | error_setg(errp, "failed to write to file '%s': %s", filename, | |
635 | strerror(errno)); | |
636 | unlink(filename); | |
637 | goto out; | |
8d5f07fa FB |
638 | } |
639 | ||
d7098135 LC |
640 | static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch, |
641 | Error **errp) | |
eee0b836 BS |
642 | { |
643 | TCXState *s = opaque; | |
644 | FILE *f; | |
645 | uint8_t *d, *d1, v; | |
646 | uint32_t *s24, *cptr, dval; | |
537f2d2b | 647 | int ret, y, x; |
8d5f07fa | 648 | |
eee0b836 | 649 | f = fopen(filename, "wb"); |
537f2d2b LC |
650 | if (!f) { |
651 | error_setg(errp, "failed to open file '%s': %s", filename, | |
652 | strerror(errno)); | |
eee0b836 | 653 | return; |
537f2d2b LC |
654 | } |
655 | ret = fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255); | |
656 | if (ret < 0) { | |
657 | goto write_err; | |
658 | } | |
eee0b836 BS |
659 | d1 = s->vram; |
660 | s24 = s->vram24; | |
661 | cptr = s->cplane; | |
662 | for(y = 0; y < s->height; y++) { | |
663 | d = d1; | |
664 | for(x = 0; x < s->width; x++, d++, s24++) { | |
665 | if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct | |
666 | dval = *s24 & 0x00ffffff; | |
537f2d2b LC |
667 | ret = fputc((dval >> 16) & 0xff, f); |
668 | if (ret == EOF) { | |
669 | goto write_err; | |
670 | } | |
671 | ret = fputc((dval >> 8) & 0xff, f); | |
672 | if (ret == EOF) { | |
673 | goto write_err; | |
674 | } | |
675 | ret = fputc(dval & 0xff, f); | |
676 | if (ret == EOF) { | |
677 | goto write_err; | |
678 | } | |
eee0b836 BS |
679 | } else { |
680 | v = *d; | |
537f2d2b LC |
681 | ret = fputc(s->r[v], f); |
682 | if (ret == EOF) { | |
683 | goto write_err; | |
684 | } | |
685 | ret = fputc(s->g[v], f); | |
686 | if (ret == EOF) { | |
687 | goto write_err; | |
688 | } | |
689 | ret = fputc(s->b[v], f); | |
690 | if (ret == EOF) { | |
691 | goto write_err; | |
692 | } | |
eee0b836 BS |
693 | } |
694 | } | |
695 | d1 += MAXX; | |
696 | } | |
537f2d2b LC |
697 | |
698 | out: | |
eee0b836 BS |
699 | fclose(f); |
700 | return; | |
537f2d2b LC |
701 | |
702 | write_err: | |
703 | error_setg(errp, "failed to write to file '%s': %s", filename, | |
704 | strerror(errno)); | |
705 | unlink(filename); | |
706 | goto out; | |
eee0b836 | 707 | } |
f40070c3 | 708 | |
999e12bb AL |
709 | static Property tcx_properties[] = { |
710 | DEFINE_PROP_TADDR("addr", TCXState, addr, -1), | |
711 | DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1), | |
712 | DEFINE_PROP_UINT16("width", TCXState, width, -1), | |
713 | DEFINE_PROP_UINT16("height", TCXState, height, -1), | |
714 | DEFINE_PROP_UINT16("depth", TCXState, depth, -1), | |
715 | DEFINE_PROP_END_OF_LIST(), | |
716 | }; | |
717 | ||
718 | static void tcx_class_init(ObjectClass *klass, void *data) | |
719 | { | |
39bffca2 | 720 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
721 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
722 | ||
723 | k->init = tcx_init1; | |
39bffca2 AL |
724 | dc->reset = tcx_reset; |
725 | dc->vmsd = &vmstate_tcx; | |
726 | dc->props = tcx_properties; | |
999e12bb AL |
727 | } |
728 | ||
8c43a6f0 | 729 | static const TypeInfo tcx_info = { |
39bffca2 AL |
730 | .name = "SUNW,tcx", |
731 | .parent = TYPE_SYS_BUS_DEVICE, | |
732 | .instance_size = sizeof(TCXState), | |
733 | .class_init = tcx_class_init, | |
ee6847d1 GH |
734 | }; |
735 | ||
83f7d43a | 736 | static void tcx_register_types(void) |
f40070c3 | 737 | { |
39bffca2 | 738 | type_register_static(&tcx_info); |
f40070c3 BS |
739 | } |
740 | ||
83f7d43a | 741 | type_init(tcx_register_types) |