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CommitLineData
16b29ae1
AL
1/*
2 * High Precisition Event Timer emulation
3 *
4 * Copyright (c) 2007 Alexander Graf
5 * Copyright (c) 2008 IBM Corporation
6 *
7 * Authors: Beth Kon <bkon@us.ibm.com>
8 *
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
18 *
19 * You should have received a copy of the GNU Lesser General Public
8167ee88 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16b29ae1
AL
21 *
22 * *****************************************************************
23 *
24 * This driver attempts to emulate an HPET device in software.
25 */
26
83c9f4ca 27#include "hw/hw.h"
0d09e41a 28#include "hw/i386/pc.h"
28ecbaee 29#include "ui/console.h"
1de7afc9 30#include "qemu/timer.h"
0d09e41a 31#include "hw/timer/hpet.h"
83c9f4ca 32#include "hw/sysbus.h"
0d09e41a
PB
33#include "hw/timer/mc146818rtc.h"
34#include "hw/timer/i8254.h"
16b29ae1 35
16b29ae1
AL
36//#define HPET_DEBUG
37#ifdef HPET_DEBUG
d0f2c4c6 38#define DPRINTF printf
16b29ae1 39#else
d0f2c4c6 40#define DPRINTF(...)
16b29ae1
AL
41#endif
42
8caa0065
JK
43#define HPET_MSI_SUPPORT 0
44
02f9a6f5
HT
45#define TYPE_HPET "hpet"
46#define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET)
47
27bb0b2d
JK
48struct HPETState;
49typedef struct HPETTimer { /* timers */
50 uint8_t tn; /*timer number*/
51 QEMUTimer *qemu_timer;
52 struct HPETState *state;
53 /* Memory-mapped, software visible timer registers */
54 uint64_t config; /* configuration/cap */
55 uint64_t cmp; /* comparator */
8caa0065 56 uint64_t fsb; /* FSB route */
27bb0b2d
JK
57 /* Hidden register state */
58 uint64_t period; /* Last value written to comparator */
59 uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
60 * mode. Next pop will be actual timer expiration.
61 */
62} HPETTimer;
63
64typedef struct HPETState {
02f9a6f5
HT
65 /*< private >*/
66 SysBusDevice parent_obj;
67 /*< public >*/
68
e977aa37 69 MemoryRegion iomem;
27bb0b2d 70 uint64_t hpet_offset;
822557eb 71 qemu_irq irqs[HPET_NUM_IRQ_ROUTES];
8caa0065 72 uint32_t flags;
7d932dfd 73 uint8_t rtc_irq_level;
ce967e2f 74 qemu_irq pit_enabled;
be4b44c5
JK
75 uint8_t num_timers;
76 HPETTimer timer[HPET_MAX_TIMERS];
27bb0b2d
JK
77
78 /* Memory-mapped, software visible registers */
79 uint64_t capability; /* capabilities */
80 uint64_t config; /* configuration */
81 uint64_t isr; /* interrupt status reg */
82 uint64_t hpet_counter; /* main counter */
40ac17cd 83 uint8_t hpet_id; /* instance id */
27bb0b2d
JK
84} HPETState;
85
7d932dfd 86static uint32_t hpet_in_legacy_mode(HPETState *s)
16b29ae1 87{
7d932dfd 88 return s->config & HPET_CFG_LEGACY;
16b29ae1
AL
89}
90
c50c2d68 91static uint32_t timer_int_route(struct HPETTimer *timer)
16b29ae1 92{
27bb0b2d 93 return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
16b29ae1
AL
94}
95
8caa0065
JK
96static uint32_t timer_fsb_route(HPETTimer *t)
97{
98 return t->config & HPET_TN_FSB_ENABLE;
99}
100
b7eaa6c7 101static uint32_t hpet_enabled(HPETState *s)
16b29ae1 102{
b7eaa6c7 103 return s->config & HPET_CFG_ENABLE;
16b29ae1
AL
104}
105
106static uint32_t timer_is_periodic(HPETTimer *t)
107{
108 return t->config & HPET_TN_PERIODIC;
109}
110
111static uint32_t timer_enabled(HPETTimer *t)
112{
113 return t->config & HPET_TN_ENABLE;
114}
115
116static uint32_t hpet_time_after(uint64_t a, uint64_t b)
117{
118 return ((int32_t)(b) - (int32_t)(a) < 0);
119}
120
121static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
122{
123 return ((int64_t)(b) - (int64_t)(a) < 0);
124}
125
c50c2d68 126static uint64_t ticks_to_ns(uint64_t value)
16b29ae1
AL
127{
128 return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
129}
130
c50c2d68 131static uint64_t ns_to_ticks(uint64_t value)
16b29ae1
AL
132{
133 return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
134}
135
136static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
137{
138 new &= mask;
139 new |= old & ~mask;
140 return new;
141}
142
143static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
144{
c50c2d68 145 return (!(old & mask) && (new & mask));
16b29ae1
AL
146}
147
148static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
149{
c50c2d68 150 return ((old & mask) && !(new & mask));
16b29ae1
AL
151}
152
b7eaa6c7 153static uint64_t hpet_get_ticks(HPETState *s)
16b29ae1 154{
bc72ad67 155 return ns_to_ticks(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hpet_offset);
16b29ae1
AL
156}
157
c50c2d68
AJ
158/*
159 * calculate diff between comparator value and current ticks
16b29ae1
AL
160 */
161static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
162{
c50c2d68 163
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AL
164 if (t->config & HPET_TN_32BIT) {
165 uint32_t diff, cmp;
27bb0b2d 166
16b29ae1
AL
167 cmp = (uint32_t)t->cmp;
168 diff = cmp - (uint32_t)current;
4f61927a 169 diff = (int32_t)diff > 0 ? diff : (uint32_t)1;
16b29ae1
AL
170 return (uint64_t)diff;
171 } else {
172 uint64_t diff, cmp;
27bb0b2d 173
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AL
174 cmp = t->cmp;
175 diff = cmp - current;
4f61927a 176 diff = (int64_t)diff > 0 ? diff : (uint64_t)1;
16b29ae1
AL
177 return diff;
178 }
179}
180
22a9fe38 181static void update_irq(struct HPETTimer *timer, int set)
16b29ae1 182{
22a9fe38
JK
183 uint64_t mask;
184 HPETState *s;
16b29ae1
AL
185 int route;
186
7d932dfd 187 if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) {
16b29ae1
AL
188 /* if LegacyReplacementRoute bit is set, HPET specification requires
189 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
c50c2d68 190 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
16b29ae1 191 */
7d932dfd 192 route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ;
16b29ae1 193 } else {
27bb0b2d 194 route = timer_int_route(timer);
16b29ae1 195 }
22a9fe38
JK
196 s = timer->state;
197 mask = 1 << timer->tn;
198 if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) {
199 s->isr &= ~mask;
8caa0065
JK
200 if (!timer_fsb_route(timer)) {
201 qemu_irq_lower(s->irqs[route]);
202 }
203 } else if (timer_fsb_route(timer)) {
8517263f 204 stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff);
22a9fe38
JK
205 } else if (timer->config & HPET_TN_TYPE_LEVEL) {
206 s->isr |= mask;
207 qemu_irq_raise(s->irqs[route]);
208 } else {
209 s->isr &= ~mask;
210 qemu_irq_pulse(s->irqs[route]);
16b29ae1
AL
211 }
212}
213
d4bfa4d7 214static void hpet_pre_save(void *opaque)
16b29ae1 215{
d4bfa4d7 216 HPETState *s = opaque;
27bb0b2d 217
16b29ae1 218 /* save current counter value */
b7eaa6c7 219 s->hpet_counter = hpet_get_ticks(s);
16b29ae1
AL
220}
221
be4b44c5
JK
222static int hpet_pre_load(void *opaque)
223{
224 HPETState *s = opaque;
225
226 /* version 1 only supports 3, later versions will load the actual value */
227 s->num_timers = HPET_MIN_TIMERS;
228 return 0;
229}
230
e59fb374 231static int hpet_post_load(void *opaque, int version_id)
16b29ae1
AL
232{
233 HPETState *s = opaque;
c50c2d68 234
16b29ae1 235 /* Recalculate the offset between the main counter and guest time */
bc72ad67 236 s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
be4b44c5
JK
237
238 /* Push number of timers into capability returned via HPET_ID */
239 s->capability &= ~HPET_ID_NUM_TIM_MASK;
240 s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
40ac17cd 241 hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
8caa0065
JK
242
243 /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */
244 s->flags &= ~(1 << HPET_MSI_SUPPORT);
245 if (s->timer[0].config & HPET_TN_FSB_CAP) {
246 s->flags |= 1 << HPET_MSI_SUPPORT;
247 }
16b29ae1
AL
248 return 0;
249}
250
5904ae4e
JK
251static bool hpet_rtc_irq_level_needed(void *opaque)
252{
253 HPETState *s = opaque;
254
255 return s->rtc_irq_level != 0;
256}
257
258static const VMStateDescription vmstate_hpet_rtc_irq_level = {
259 .name = "hpet/rtc_irq_level",
260 .version_id = 1,
261 .minimum_version_id = 1,
262 .minimum_version_id_old = 1,
263 .fields = (VMStateField[]) {
264 VMSTATE_UINT8(rtc_irq_level, HPETState),
265 VMSTATE_END_OF_LIST()
266 }
267};
268
e6cb4d45
JQ
269static const VMStateDescription vmstate_hpet_timer = {
270 .name = "hpet_timer",
271 .version_id = 1,
272 .minimum_version_id = 1,
273 .minimum_version_id_old = 1,
274 .fields = (VMStateField []) {
275 VMSTATE_UINT8(tn, HPETTimer),
276 VMSTATE_UINT64(config, HPETTimer),
277 VMSTATE_UINT64(cmp, HPETTimer),
278 VMSTATE_UINT64(fsb, HPETTimer),
279 VMSTATE_UINT64(period, HPETTimer),
280 VMSTATE_UINT8(wrap_flag, HPETTimer),
281 VMSTATE_TIMER(qemu_timer, HPETTimer),
282 VMSTATE_END_OF_LIST()
283 }
284};
285
286static const VMStateDescription vmstate_hpet = {
287 .name = "hpet",
be4b44c5 288 .version_id = 2,
e6cb4d45
JQ
289 .minimum_version_id = 1,
290 .minimum_version_id_old = 1,
291 .pre_save = hpet_pre_save,
be4b44c5 292 .pre_load = hpet_pre_load,
e6cb4d45
JQ
293 .post_load = hpet_post_load,
294 .fields = (VMStateField []) {
295 VMSTATE_UINT64(config, HPETState),
296 VMSTATE_UINT64(isr, HPETState),
297 VMSTATE_UINT64(hpet_counter, HPETState),
be4b44c5
JK
298 VMSTATE_UINT8_V(num_timers, HPETState, 2),
299 VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0,
300 vmstate_hpet_timer, HPETTimer),
e6cb4d45 301 VMSTATE_END_OF_LIST()
5904ae4e
JK
302 },
303 .subsections = (VMStateSubsection[]) {
304 {
305 .vmsd = &vmstate_hpet_rtc_irq_level,
306 .needed = hpet_rtc_irq_level_needed,
307 }, {
308 /* empty */
309 }
e6cb4d45
JQ
310 }
311};
312
c50c2d68 313/*
16b29ae1
AL
314 * timer expiration callback
315 */
316static void hpet_timer(void *opaque)
317{
27bb0b2d 318 HPETTimer *t = opaque;
16b29ae1
AL
319 uint64_t diff;
320
321 uint64_t period = t->period;
b7eaa6c7 322 uint64_t cur_tick = hpet_get_ticks(t->state);
16b29ae1
AL
323
324 if (timer_is_periodic(t) && period != 0) {
325 if (t->config & HPET_TN_32BIT) {
27bb0b2d 326 while (hpet_time_after(cur_tick, t->cmp)) {
16b29ae1 327 t->cmp = (uint32_t)(t->cmp + t->period);
27bb0b2d
JK
328 }
329 } else {
330 while (hpet_time_after64(cur_tick, t->cmp)) {
16b29ae1 331 t->cmp += period;
27bb0b2d
JK
332 }
333 }
16b29ae1 334 diff = hpet_calculate_diff(t, cur_tick);
bc72ad67
AB
335 timer_mod(t->qemu_timer,
336 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
16b29ae1
AL
337 } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
338 if (t->wrap_flag) {
339 diff = hpet_calculate_diff(t, cur_tick);
bc72ad67 340 timer_mod(t->qemu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
27bb0b2d 341 (int64_t)ticks_to_ns(diff));
16b29ae1
AL
342 t->wrap_flag = 0;
343 }
344 }
22a9fe38 345 update_irq(t, 1);
16b29ae1
AL
346}
347
348static void hpet_set_timer(HPETTimer *t)
349{
350 uint64_t diff;
351 uint32_t wrap_diff; /* how many ticks until we wrap? */
b7eaa6c7 352 uint64_t cur_tick = hpet_get_ticks(t->state);
c50c2d68 353
16b29ae1
AL
354 /* whenever new timer is being set up, make sure wrap_flag is 0 */
355 t->wrap_flag = 0;
356 diff = hpet_calculate_diff(t, cur_tick);
357
c50c2d68 358 /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
16b29ae1 359 * counter wraps in addition to an interrupt with comparator match.
c50c2d68 360 */
16b29ae1
AL
361 if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
362 wrap_diff = 0xffffffff - (uint32_t)cur_tick;
363 if (wrap_diff < (uint32_t)diff) {
364 diff = wrap_diff;
c50c2d68 365 t->wrap_flag = 1;
16b29ae1
AL
366 }
367 }
bc72ad67
AB
368 timer_mod(t->qemu_timer,
369 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff));
16b29ae1
AL
370}
371
372static void hpet_del_timer(HPETTimer *t)
373{
bc72ad67 374 timer_del(t->qemu_timer);
22a9fe38 375 update_irq(t, 0);
16b29ae1
AL
376}
377
378#ifdef HPET_DEBUG
a8170e5e 379static uint32_t hpet_ram_readb(void *opaque, hwaddr addr)
16b29ae1
AL
380{
381 printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
382 return 0;
383}
384
a8170e5e 385static uint32_t hpet_ram_readw(void *opaque, hwaddr addr)
16b29ae1
AL
386{
387 printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
388 return 0;
389}
390#endif
391
a8170e5e 392static uint64_t hpet_ram_read(void *opaque, hwaddr addr,
e977aa37 393 unsigned size)
16b29ae1 394{
27bb0b2d 395 HPETState *s = opaque;
16b29ae1
AL
396 uint64_t cur_tick, index;
397
d0f2c4c6 398 DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
16b29ae1
AL
399 index = addr;
400 /*address range of all TN regs*/
401 if (index >= 0x100 && index <= 0x3ff) {
402 uint8_t timer_id = (addr - 0x100) / 0x20;
27bb0b2d
JK
403 HPETTimer *timer = &s->timer[timer_id];
404
be4b44c5 405 if (timer_id > s->num_timers) {
6982d664 406 DPRINTF("qemu: timer id out of range\n");
16b29ae1
AL
407 return 0;
408 }
16b29ae1
AL
409
410 switch ((addr - 0x100) % 0x20) {
27bb0b2d
JK
411 case HPET_TN_CFG:
412 return timer->config;
413 case HPET_TN_CFG + 4: // Interrupt capabilities
414 return timer->config >> 32;
415 case HPET_TN_CMP: // comparator register
416 return timer->cmp;
417 case HPET_TN_CMP + 4:
418 return timer->cmp >> 32;
419 case HPET_TN_ROUTE:
8caa0065
JK
420 return timer->fsb;
421 case HPET_TN_ROUTE + 4:
27bb0b2d
JK
422 return timer->fsb >> 32;
423 default:
424 DPRINTF("qemu: invalid hpet_ram_readl\n");
425 break;
16b29ae1
AL
426 }
427 } else {
428 switch (index) {
27bb0b2d
JK
429 case HPET_ID:
430 return s->capability;
431 case HPET_PERIOD:
432 return s->capability >> 32;
433 case HPET_CFG:
434 return s->config;
435 case HPET_CFG + 4:
b2bedb21 436 DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n");
27bb0b2d
JK
437 return 0;
438 case HPET_COUNTER:
b7eaa6c7
JK
439 if (hpet_enabled(s)) {
440 cur_tick = hpet_get_ticks(s);
27bb0b2d
JK
441 } else {
442 cur_tick = s->hpet_counter;
443 }
444 DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
445 return cur_tick;
446 case HPET_COUNTER + 4:
b7eaa6c7
JK
447 if (hpet_enabled(s)) {
448 cur_tick = hpet_get_ticks(s);
27bb0b2d
JK
449 } else {
450 cur_tick = s->hpet_counter;
451 }
452 DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
453 return cur_tick >> 32;
454 case HPET_STATUS:
455 return s->isr;
456 default:
457 DPRINTF("qemu: invalid hpet_ram_readl\n");
458 break;
16b29ae1
AL
459 }
460 }
461 return 0;
462}
463
a8170e5e 464static void hpet_ram_write(void *opaque, hwaddr addr,
e977aa37 465 uint64_t value, unsigned size)
16b29ae1
AL
466{
467 int i;
27bb0b2d 468 HPETState *s = opaque;
ce536cfd 469 uint64_t old_val, new_val, val, index;
16b29ae1 470
d0f2c4c6 471 DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
16b29ae1 472 index = addr;
e977aa37 473 old_val = hpet_ram_read(opaque, addr, 4);
16b29ae1
AL
474 new_val = value;
475
476 /*address range of all TN regs*/
477 if (index >= 0x100 && index <= 0x3ff) {
478 uint8_t timer_id = (addr - 0x100) / 0x20;
16b29ae1 479 HPETTimer *timer = &s->timer[timer_id];
c50c2d68 480
b2bedb21 481 DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id);
be4b44c5 482 if (timer_id > s->num_timers) {
6982d664
JK
483 DPRINTF("qemu: timer id out of range\n");
484 return;
485 }
16b29ae1 486 switch ((addr - 0x100) % 0x20) {
27bb0b2d
JK
487 case HPET_TN_CFG:
488 DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
8caa0065
JK
489 if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) {
490 update_irq(timer, 0);
491 }
27bb0b2d
JK
492 val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK);
493 timer->config = (timer->config & 0xffffffff00000000ULL) | val;
494 if (new_val & HPET_TN_32BIT) {
495 timer->cmp = (uint32_t)timer->cmp;
496 timer->period = (uint32_t)timer->period;
497 }
9cec89e8
JK
498 if (activating_bit(old_val, new_val, HPET_TN_ENABLE)) {
499 hpet_set_timer(timer);
500 } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) {
501 hpet_del_timer(timer);
502 }
27bb0b2d
JK
503 break;
504 case HPET_TN_CFG + 4: // Interrupt capabilities
505 DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
506 break;
507 case HPET_TN_CMP: // comparator register
b2bedb21 508 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n");
27bb0b2d
JK
509 if (timer->config & HPET_TN_32BIT) {
510 new_val = (uint32_t)new_val;
511 }
512 if (!timer_is_periodic(timer)
513 || (timer->config & HPET_TN_SETVAL)) {
514 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val;
515 }
516 if (timer_is_periodic(timer)) {
517 /*
518 * FIXME: Clamp period to reasonable min value?
519 * Clamp period to reasonable max value
520 */
521 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
522 timer->period =
523 (timer->period & 0xffffffff00000000ULL) | new_val;
524 }
525 timer->config &= ~HPET_TN_SETVAL;
b7eaa6c7 526 if (hpet_enabled(s)) {
27bb0b2d
JK
527 hpet_set_timer(timer);
528 }
529 break;
530 case HPET_TN_CMP + 4: // comparator register high order
531 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
532 if (!timer_is_periodic(timer)
533 || (timer->config & HPET_TN_SETVAL)) {
534 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32;
535 } else {
536 /*
537 * FIXME: Clamp period to reasonable min value?
538 * Clamp period to reasonable max value
539 */
540 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
541 timer->period =
542 (timer->period & 0xffffffffULL) | new_val << 32;
16b29ae1
AL
543 }
544 timer->config &= ~HPET_TN_SETVAL;
b7eaa6c7 545 if (hpet_enabled(s)) {
16b29ae1 546 hpet_set_timer(timer);
16b29ae1 547 }
16b29ae1 548 break;
8caa0065
JK
549 case HPET_TN_ROUTE:
550 timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val;
551 break;
27bb0b2d 552 case HPET_TN_ROUTE + 4:
8caa0065 553 timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff);
27bb0b2d
JK
554 break;
555 default:
556 DPRINTF("qemu: invalid hpet_ram_writel\n");
557 break;
16b29ae1
AL
558 }
559 return;
560 } else {
561 switch (index) {
27bb0b2d
JK
562 case HPET_ID:
563 return;
564 case HPET_CFG:
565 val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK);
566 s->config = (s->config & 0xffffffff00000000ULL) | val;
567 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
568 /* Enable main counter and interrupt generation. */
569 s->hpet_offset =
bc72ad67 570 ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
be4b44c5 571 for (i = 0; i < s->num_timers; i++) {
27bb0b2d
JK
572 if ((&s->timer[i])->cmp != ~0ULL) {
573 hpet_set_timer(&s->timer[i]);
574 }
16b29ae1 575 }
27bb0b2d
JK
576 } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
577 /* Halt main counter and disable interrupt generation. */
b7eaa6c7 578 s->hpet_counter = hpet_get_ticks(s);
be4b44c5 579 for (i = 0; i < s->num_timers; i++) {
27bb0b2d 580 hpet_del_timer(&s->timer[i]);
16b29ae1 581 }
27bb0b2d 582 }
ce967e2f
JK
583 /* i8254 and RTC output pins are disabled
584 * when HPET is in legacy mode */
27bb0b2d 585 if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
ce967e2f
JK
586 qemu_set_irq(s->pit_enabled, 0);
587 qemu_irq_lower(s->irqs[0]);
7d932dfd 588 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]);
27bb0b2d 589 } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
ce967e2f
JK
590 qemu_irq_lower(s->irqs[0]);
591 qemu_set_irq(s->pit_enabled, 1);
7d932dfd 592 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level);
27bb0b2d
JK
593 }
594 break;
595 case HPET_CFG + 4:
b2bedb21 596 DPRINTF("qemu: invalid HPET_CFG+4 write\n");
27bb0b2d
JK
597 break;
598 case HPET_STATUS:
22a9fe38 599 val = new_val & s->isr;
be4b44c5 600 for (i = 0; i < s->num_timers; i++) {
22a9fe38
JK
601 if (val & (1 << i)) {
602 update_irq(&s->timer[i], 0);
603 }
604 }
27bb0b2d
JK
605 break;
606 case HPET_COUNTER:
b7eaa6c7 607 if (hpet_enabled(s)) {
ad0a6551 608 DPRINTF("qemu: Writing counter while HPET enabled!\n");
27bb0b2d
JK
609 }
610 s->hpet_counter =
611 (s->hpet_counter & 0xffffffff00000000ULL) | value;
612 DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
613 value, s->hpet_counter);
614 break;
615 case HPET_COUNTER + 4:
b7eaa6c7 616 if (hpet_enabled(s)) {
ad0a6551 617 DPRINTF("qemu: Writing counter while HPET enabled!\n");
27bb0b2d
JK
618 }
619 s->hpet_counter =
620 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32);
621 DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
622 value, s->hpet_counter);
623 break;
624 default:
625 DPRINTF("qemu: invalid hpet_ram_writel\n");
626 break;
16b29ae1
AL
627 }
628 }
629}
630
e977aa37
AK
631static const MemoryRegionOps hpet_ram_ops = {
632 .read = hpet_ram_read,
633 .write = hpet_ram_write,
634 .valid = {
635 .min_access_size = 4,
636 .max_access_size = 4,
637 },
638 .endianness = DEVICE_NATIVE_ENDIAN,
16b29ae1
AL
639};
640
822557eb 641static void hpet_reset(DeviceState *d)
27bb0b2d 642{
02f9a6f5
HT
643 HPETState *s = HPET(d);
644 SysBusDevice *sbd = SYS_BUS_DEVICE(d);
16b29ae1 645 int i;
16b29ae1 646
be4b44c5 647 for (i = 0; i < s->num_timers; i++) {
16b29ae1 648 HPETTimer *timer = &s->timer[i];
27bb0b2d 649
16b29ae1 650 hpet_del_timer(timer);
16b29ae1 651 timer->cmp = ~0ULL;
8caa0065
JK
652 timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
653 if (s->flags & (1 << HPET_MSI_SUPPORT)) {
654 timer->config |= HPET_TN_FSB_CAP;
655 }
ce536cfd
BK
656 /* advertise availability of ioapic inti2 */
657 timer->config |= 0x00000004ULL << 32;
16b29ae1
AL
658 timer->period = 0ULL;
659 timer->wrap_flag = 0;
660 }
661
ce967e2f 662 qemu_set_irq(s->pit_enabled, 1);
16b29ae1
AL
663 s->hpet_counter = 0ULL;
664 s->hpet_offset = 0ULL;
7d93b1fa 665 s->config = 0ULL;
40ac17cd 666 hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability;
02f9a6f5 667 hpet_cfg.hpet[s->hpet_id].address = sbd->mmio[0].addr;
5904ae4e
JK
668
669 /* to document that the RTC lowers its output on reset as well */
670 s->rtc_irq_level = 0;
16b29ae1
AL
671}
672
ce967e2f 673static void hpet_handle_legacy_irq(void *opaque, int n, int level)
7d932dfd 674{
02f9a6f5 675 HPETState *s = HPET(opaque);
7d932dfd 676
ce967e2f
JK
677 if (n == HPET_LEGACY_PIT_INT) {
678 if (!hpet_in_legacy_mode(s)) {
679 qemu_set_irq(s->irqs[0], level);
680 }
681 } else {
682 s->rtc_irq_level = level;
683 if (!hpet_in_legacy_mode(s)) {
684 qemu_set_irq(s->irqs[RTC_ISA_IRQ], level);
685 }
7d932dfd
JK
686 }
687}
688
726887ef 689static void hpet_init(Object *obj)
27bb0b2d 690{
726887ef
HT
691 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
692 HPETState *s = HPET(obj);
693
694 /* HPET Area */
695 memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", 0x400);
696 sysbus_init_mmio(sbd, &s->iomem);
697}
698
699static void hpet_realize(DeviceState *dev, Error **errp)
700{
701 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
02f9a6f5 702 HPETState *s = HPET(dev);
e977aa37 703 int i;
27bb0b2d 704 HPETTimer *timer;
16b29ae1 705
d2c5efd8
SW
706 if (hpet_cfg.count == UINT8_MAX) {
707 /* first instance */
40ac17cd 708 hpet_cfg.count = 0;
d2c5efd8 709 }
40ac17cd
GN
710
711 if (hpet_cfg.count == 8) {
726887ef
HT
712 error_setg(errp, "Only 8 instances of HPET is allowed");
713 return;
40ac17cd
GN
714 }
715
716 s->hpet_id = hpet_cfg.count++;
717
822557eb 718 for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
726887ef 719 sysbus_init_irq(sbd, &s->irqs[i]);
822557eb 720 }
be4b44c5
JK
721
722 if (s->num_timers < HPET_MIN_TIMERS) {
723 s->num_timers = HPET_MIN_TIMERS;
724 } else if (s->num_timers > HPET_MAX_TIMERS) {
725 s->num_timers = HPET_MAX_TIMERS;
726 }
727 for (i = 0; i < HPET_MAX_TIMERS; i++) {
27bb0b2d 728 timer = &s->timer[i];
bc72ad67 729 timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer);
7afbecc9
JK
730 timer->tn = i;
731 timer->state = s;
16b29ae1 732 }
822557eb 733
072c2c31
JK
734 /* 64-bit main counter; LegacyReplacementRoute. */
735 s->capability = 0x8086a001ULL;
736 s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT;
737 s->capability |= ((HPET_CLK_PERIOD) << 32);
738
726887ef
HT
739 qdev_init_gpio_in(dev, hpet_handle_legacy_irq, 2);
740 qdev_init_gpio_out(dev, &s->pit_enabled, 1);
16b29ae1 741}
822557eb 742
999e12bb
AL
743static Property hpet_device_properties[] = {
744 DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS),
745 DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false),
746 DEFINE_PROP_END_OF_LIST(),
747};
748
749static void hpet_device_class_init(ObjectClass *klass, void *data)
750{
39bffca2 751 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb 752
726887ef 753 dc->realize = hpet_realize;
39bffca2
AL
754 dc->no_user = 1;
755 dc->reset = hpet_reset;
756 dc->vmsd = &vmstate_hpet;
757 dc->props = hpet_device_properties;
999e12bb
AL
758}
759
64e9df8d
MT
760bool hpet_find(void)
761{
762 return object_resolve_path_type("", TYPE_HPET, NULL);
763}
764
8c43a6f0 765static const TypeInfo hpet_device_info = {
02f9a6f5 766 .name = TYPE_HPET,
39bffca2
AL
767 .parent = TYPE_SYS_BUS_DEVICE,
768 .instance_size = sizeof(HPETState),
726887ef 769 .instance_init = hpet_init,
39bffca2 770 .class_init = hpet_device_class_init,
822557eb
JK
771};
772
83f7d43a 773static void hpet_register_types(void)
822557eb 774{
39bffca2 775 type_register_static(&hpet_device_info);
822557eb
JK
776}
777
83f7d43a 778type_init(hpet_register_types)