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Commit | Line | Data |
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a541f297 | 1 | /* |
819385c5 | 2 | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms |
5fafdf24 | 3 | * |
3ccacc4a | 4 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/hw.h" |
0d09e41a | 25 | #include "hw/timer/m48t59.h" |
1de7afc9 | 26 | #include "qemu/timer.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
83c9f4ca | 28 | #include "hw/sysbus.h" |
0d09e41a | 29 | #include "hw/isa/isa.h" |
022c62cb | 30 | #include "exec/address-spaces.h" |
a541f297 | 31 | |
13ab5daa | 32 | //#define DEBUG_NVRAM |
a541f297 | 33 | |
13ab5daa | 34 | #if defined(DEBUG_NVRAM) |
001faf32 | 35 | #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
a541f297 | 36 | #else |
001faf32 | 37 | #define NVRAM_PRINTF(fmt, ...) do { } while (0) |
a541f297 FB |
38 | #endif |
39 | ||
819385c5 | 40 | /* |
4aed2c33 | 41 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has |
819385c5 FB |
42 | * alarm and a watchdog timer and related control registers. In the |
43 | * PPC platform there is also a nvram lock function. | |
44 | */ | |
930f3fe1 BS |
45 | |
46 | /* | |
47 | * Chipset docs: | |
48 | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf | |
49 | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf | |
50 | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf | |
51 | */ | |
52 | ||
43a34704 | 53 | struct M48t59State { |
a541f297 | 54 | /* Hardware parameters */ |
d537cf6c | 55 | qemu_irq IRQ; |
5a31cd68 | 56 | MemoryRegion iomem; |
a541f297 | 57 | uint32_t io_base; |
ee6847d1 | 58 | uint32_t size; |
a541f297 FB |
59 | /* RTC management */ |
60 | time_t time_offset; | |
61 | time_t stop_time; | |
62 | /* Alarm & watchdog */ | |
f6503059 | 63 | struct tm alarm; |
a541f297 FB |
64 | struct QEMUTimer *alrm_timer; |
65 | struct QEMUTimer *wd_timer; | |
66 | /* NVRAM storage */ | |
a541f297 | 67 | uint8_t *buffer; |
42c812b9 | 68 | /* Model parameters */ |
7bc3018b | 69 | uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */ |
42c812b9 BS |
70 | /* NVRAM storage */ |
71 | uint16_t addr; | |
72 | uint8_t lock; | |
c5df018e | 73 | }; |
a541f297 | 74 | |
a2772c70 AF |
75 | #define TYPE_ISA_M48T59 "m48t59_isa" |
76 | #define ISA_M48T59(obj) \ | |
77 | OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59) | |
78 | ||
f80237d4 | 79 | typedef struct M48t59ISAState { |
a2772c70 AF |
80 | ISADevice parent_obj; |
81 | ||
43a34704 | 82 | M48t59State state; |
9936d6e4 | 83 | MemoryRegion io; |
f80237d4 BS |
84 | } M48t59ISAState; |
85 | ||
86 | typedef struct M48t59SysBusState { | |
87 | SysBusDevice busdev; | |
43a34704 | 88 | M48t59State state; |
087bd055 | 89 | MemoryRegion io; |
f80237d4 BS |
90 | } M48t59SysBusState; |
91 | ||
a541f297 | 92 | /* Fake timer functions */ |
a541f297 | 93 | |
a541f297 FB |
94 | /* Alarm management */ |
95 | static void alarm_cb (void *opaque) | |
96 | { | |
f6503059 | 97 | struct tm tm; |
a541f297 | 98 | uint64_t next_time; |
43a34704 | 99 | M48t59State *NVRAM = opaque; |
a541f297 | 100 | |
d537cf6c | 101 | qemu_set_irq(NVRAM->IRQ, 1); |
5fafdf24 | 102 | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
a541f297 FB |
103 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
104 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
105 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
106 | /* Repeat once a month */ |
107 | qemu_get_timedate(&tm, NVRAM->time_offset); | |
108 | tm.tm_mon++; | |
109 | if (tm.tm_mon == 13) { | |
110 | tm.tm_mon = 1; | |
111 | tm.tm_year++; | |
112 | } | |
113 | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; | |
a541f297 FB |
114 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
115 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && | |
116 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
117 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
118 | /* Repeat once a day */ |
119 | next_time = 24 * 60 * 60; | |
a541f297 FB |
120 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
121 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
122 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
123 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
124 | /* Repeat once an hour */ |
125 | next_time = 60 * 60; | |
a541f297 FB |
126 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
127 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
128 | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && | |
129 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
130 | /* Repeat once a minute */ |
131 | next_time = 60; | |
a541f297 | 132 | } else { |
f6503059 AZ |
133 | /* Repeat once a second */ |
134 | next_time = 1; | |
a541f297 | 135 | } |
1d849502 | 136 | qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) + |
f6503059 | 137 | next_time * 1000); |
d537cf6c | 138 | qemu_set_irq(NVRAM->IRQ, 0); |
a541f297 FB |
139 | } |
140 | ||
43a34704 | 141 | static void set_alarm(M48t59State *NVRAM) |
f6503059 AZ |
142 | { |
143 | int diff; | |
144 | if (NVRAM->alrm_timer != NULL) { | |
145 | qemu_del_timer(NVRAM->alrm_timer); | |
146 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; | |
147 | if (diff > 0) | |
148 | qemu_mod_timer(NVRAM->alrm_timer, diff * 1000); | |
149 | } | |
150 | } | |
a541f297 | 151 | |
f6503059 | 152 | /* RTC management helpers */ |
43a34704 | 153 | static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 154 | { |
f6503059 | 155 | qemu_get_timedate(tm, NVRAM->time_offset); |
a541f297 FB |
156 | } |
157 | ||
43a34704 | 158 | static void set_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 159 | { |
f6503059 AZ |
160 | NVRAM->time_offset = qemu_timedate_diff(tm); |
161 | set_alarm(NVRAM); | |
a541f297 FB |
162 | } |
163 | ||
164 | /* Watchdog management */ | |
165 | static void watchdog_cb (void *opaque) | |
166 | { | |
43a34704 | 167 | M48t59State *NVRAM = opaque; |
a541f297 FB |
168 | |
169 | NVRAM->buffer[0x1FF0] |= 0x80; | |
170 | if (NVRAM->buffer[0x1FF7] & 0x80) { | |
171 | NVRAM->buffer[0x1FF7] = 0x00; | |
172 | NVRAM->buffer[0x1FFC] &= ~0x40; | |
13ab5daa | 173 | /* May it be a hw CPU Reset instead ? */ |
d7d02e3c | 174 | qemu_system_reset_request(); |
a541f297 | 175 | } else { |
d537cf6c PB |
176 | qemu_set_irq(NVRAM->IRQ, 1); |
177 | qemu_set_irq(NVRAM->IRQ, 0); | |
a541f297 FB |
178 | } |
179 | } | |
180 | ||
43a34704 | 181 | static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
a541f297 FB |
182 | { |
183 | uint64_t interval; /* in 1/16 seconds */ | |
184 | ||
868d585a | 185 | NVRAM->buffer[0x1FF0] &= ~0x80; |
a541f297 FB |
186 | if (NVRAM->wd_timer != NULL) { |
187 | qemu_del_timer(NVRAM->wd_timer); | |
868d585a JM |
188 | if (value != 0) { |
189 | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); | |
190 | qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + | |
191 | ((interval * 1000) >> 4)); | |
192 | } | |
a541f297 FB |
193 | } |
194 | } | |
195 | ||
196 | /* Direct access to NVRAM */ | |
897b4c6c | 197 | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
a541f297 | 198 | { |
43a34704 | 199 | M48t59State *NVRAM = opaque; |
a541f297 FB |
200 | struct tm tm; |
201 | int tmp; | |
202 | ||
819385c5 FB |
203 | if (addr > 0x1FF8 && addr < 0x2000) |
204 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); | |
4aed2c33 BS |
205 | |
206 | /* check for NVRAM access */ | |
7bc3018b PB |
207 | if ((NVRAM->model == 2 && addr < 0x7f8) || |
208 | (NVRAM->model == 8 && addr < 0x1ff8) || | |
209 | (NVRAM->model == 59 && addr < 0x1ff0)) { | |
819385c5 | 210 | goto do_write; |
7bc3018b | 211 | } |
4aed2c33 BS |
212 | |
213 | /* TOD access */ | |
819385c5 | 214 | switch (addr) { |
a541f297 FB |
215 | case 0x1FF0: |
216 | /* flags register : read-only */ | |
217 | break; | |
218 | case 0x1FF1: | |
219 | /* unused */ | |
220 | break; | |
221 | case 0x1FF2: | |
222 | /* alarm seconds */ | |
abd0c6bd | 223 | tmp = from_bcd(val & 0x7F); |
819385c5 | 224 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 225 | NVRAM->alarm.tm_sec = tmp; |
819385c5 | 226 | NVRAM->buffer[0x1FF2] = val; |
f6503059 | 227 | set_alarm(NVRAM); |
819385c5 | 228 | } |
a541f297 FB |
229 | break; |
230 | case 0x1FF3: | |
231 | /* alarm minutes */ | |
abd0c6bd | 232 | tmp = from_bcd(val & 0x7F); |
819385c5 | 233 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 234 | NVRAM->alarm.tm_min = tmp; |
819385c5 | 235 | NVRAM->buffer[0x1FF3] = val; |
f6503059 | 236 | set_alarm(NVRAM); |
819385c5 | 237 | } |
a541f297 FB |
238 | break; |
239 | case 0x1FF4: | |
240 | /* alarm hours */ | |
abd0c6bd | 241 | tmp = from_bcd(val & 0x3F); |
819385c5 | 242 | if (tmp >= 0 && tmp <= 23) { |
f6503059 | 243 | NVRAM->alarm.tm_hour = tmp; |
819385c5 | 244 | NVRAM->buffer[0x1FF4] = val; |
f6503059 | 245 | set_alarm(NVRAM); |
819385c5 | 246 | } |
a541f297 FB |
247 | break; |
248 | case 0x1FF5: | |
249 | /* alarm date */ | |
02f5da11 | 250 | tmp = from_bcd(val & 0x3F); |
819385c5 | 251 | if (tmp != 0) { |
f6503059 | 252 | NVRAM->alarm.tm_mday = tmp; |
819385c5 | 253 | NVRAM->buffer[0x1FF5] = val; |
f6503059 | 254 | set_alarm(NVRAM); |
819385c5 | 255 | } |
a541f297 FB |
256 | break; |
257 | case 0x1FF6: | |
258 | /* interrupts */ | |
819385c5 | 259 | NVRAM->buffer[0x1FF6] = val; |
a541f297 FB |
260 | break; |
261 | case 0x1FF7: | |
262 | /* watchdog */ | |
819385c5 FB |
263 | NVRAM->buffer[0x1FF7] = val; |
264 | set_up_watchdog(NVRAM, val); | |
a541f297 FB |
265 | break; |
266 | case 0x1FF8: | |
4aed2c33 | 267 | case 0x07F8: |
a541f297 | 268 | /* control */ |
4aed2c33 | 269 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
a541f297 FB |
270 | break; |
271 | case 0x1FF9: | |
4aed2c33 | 272 | case 0x07F9: |
a541f297 | 273 | /* seconds (BCD) */ |
abd0c6bd | 274 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
275 | if (tmp >= 0 && tmp <= 59) { |
276 | get_time(NVRAM, &tm); | |
277 | tm.tm_sec = tmp; | |
278 | set_time(NVRAM, &tm); | |
279 | } | |
f6503059 | 280 | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
a541f297 FB |
281 | if (val & 0x80) { |
282 | NVRAM->stop_time = time(NULL); | |
283 | } else { | |
284 | NVRAM->time_offset += NVRAM->stop_time - time(NULL); | |
285 | NVRAM->stop_time = 0; | |
286 | } | |
287 | } | |
f6503059 | 288 | NVRAM->buffer[addr] = val & 0x80; |
a541f297 FB |
289 | break; |
290 | case 0x1FFA: | |
4aed2c33 | 291 | case 0x07FA: |
a541f297 | 292 | /* minutes (BCD) */ |
abd0c6bd | 293 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
294 | if (tmp >= 0 && tmp <= 59) { |
295 | get_time(NVRAM, &tm); | |
296 | tm.tm_min = tmp; | |
297 | set_time(NVRAM, &tm); | |
298 | } | |
299 | break; | |
300 | case 0x1FFB: | |
4aed2c33 | 301 | case 0x07FB: |
a541f297 | 302 | /* hours (BCD) */ |
abd0c6bd | 303 | tmp = from_bcd(val & 0x3F); |
a541f297 FB |
304 | if (tmp >= 0 && tmp <= 23) { |
305 | get_time(NVRAM, &tm); | |
306 | tm.tm_hour = tmp; | |
307 | set_time(NVRAM, &tm); | |
308 | } | |
309 | break; | |
310 | case 0x1FFC: | |
4aed2c33 | 311 | case 0x07FC: |
a541f297 | 312 | /* day of the week / century */ |
abd0c6bd | 313 | tmp = from_bcd(val & 0x07); |
a541f297 FB |
314 | get_time(NVRAM, &tm); |
315 | tm.tm_wday = tmp; | |
316 | set_time(NVRAM, &tm); | |
4aed2c33 | 317 | NVRAM->buffer[addr] = val & 0x40; |
a541f297 FB |
318 | break; |
319 | case 0x1FFD: | |
4aed2c33 | 320 | case 0x07FD: |
02f5da11 AT |
321 | /* date (BCD) */ |
322 | tmp = from_bcd(val & 0x3F); | |
a541f297 FB |
323 | if (tmp != 0) { |
324 | get_time(NVRAM, &tm); | |
325 | tm.tm_mday = tmp; | |
326 | set_time(NVRAM, &tm); | |
327 | } | |
328 | break; | |
329 | case 0x1FFE: | |
4aed2c33 | 330 | case 0x07FE: |
a541f297 | 331 | /* month */ |
abd0c6bd | 332 | tmp = from_bcd(val & 0x1F); |
a541f297 FB |
333 | if (tmp >= 1 && tmp <= 12) { |
334 | get_time(NVRAM, &tm); | |
335 | tm.tm_mon = tmp - 1; | |
336 | set_time(NVRAM, &tm); | |
337 | } | |
338 | break; | |
339 | case 0x1FFF: | |
4aed2c33 | 340 | case 0x07FF: |
a541f297 | 341 | /* year */ |
abd0c6bd | 342 | tmp = from_bcd(val); |
a541f297 FB |
343 | if (tmp >= 0 && tmp <= 99) { |
344 | get_time(NVRAM, &tm); | |
7bc3018b | 345 | if (NVRAM->model == 8) { |
abd0c6bd | 346 | tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
7bc3018b | 347 | } else { |
abd0c6bd | 348 | tm.tm_year = from_bcd(val); |
7bc3018b | 349 | } |
a541f297 FB |
350 | set_time(NVRAM, &tm); |
351 | } | |
352 | break; | |
353 | default: | |
13ab5daa | 354 | /* Check lock registers state */ |
819385c5 | 355 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 356 | break; |
819385c5 | 357 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 358 | break; |
819385c5 FB |
359 | do_write: |
360 | if (addr < NVRAM->size) { | |
361 | NVRAM->buffer[addr] = val & 0xFF; | |
a541f297 FB |
362 | } |
363 | break; | |
364 | } | |
365 | } | |
366 | ||
897b4c6c | 367 | uint32_t m48t59_read (void *opaque, uint32_t addr) |
a541f297 | 368 | { |
43a34704 | 369 | M48t59State *NVRAM = opaque; |
a541f297 FB |
370 | struct tm tm; |
371 | uint32_t retval = 0xFF; | |
372 | ||
4aed2c33 | 373 | /* check for NVRAM access */ |
7bc3018b PB |
374 | if ((NVRAM->model == 2 && addr < 0x078f) || |
375 | (NVRAM->model == 8 && addr < 0x1ff8) || | |
376 | (NVRAM->model == 59 && addr < 0x1ff0)) { | |
819385c5 | 377 | goto do_read; |
7bc3018b | 378 | } |
4aed2c33 BS |
379 | |
380 | /* TOD access */ | |
819385c5 | 381 | switch (addr) { |
a541f297 FB |
382 | case 0x1FF0: |
383 | /* flags register */ | |
384 | goto do_read; | |
385 | case 0x1FF1: | |
386 | /* unused */ | |
387 | retval = 0; | |
388 | break; | |
389 | case 0x1FF2: | |
390 | /* alarm seconds */ | |
391 | goto do_read; | |
392 | case 0x1FF3: | |
393 | /* alarm minutes */ | |
394 | goto do_read; | |
395 | case 0x1FF4: | |
396 | /* alarm hours */ | |
397 | goto do_read; | |
398 | case 0x1FF5: | |
399 | /* alarm date */ | |
400 | goto do_read; | |
401 | case 0x1FF6: | |
402 | /* interrupts */ | |
403 | goto do_read; | |
404 | case 0x1FF7: | |
405 | /* A read resets the watchdog */ | |
406 | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]); | |
407 | goto do_read; | |
408 | case 0x1FF8: | |
4aed2c33 | 409 | case 0x07F8: |
a541f297 FB |
410 | /* control */ |
411 | goto do_read; | |
412 | case 0x1FF9: | |
4aed2c33 | 413 | case 0x07F9: |
a541f297 FB |
414 | /* seconds (BCD) */ |
415 | get_time(NVRAM, &tm); | |
abd0c6bd | 416 | retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec); |
a541f297 FB |
417 | break; |
418 | case 0x1FFA: | |
4aed2c33 | 419 | case 0x07FA: |
a541f297 FB |
420 | /* minutes (BCD) */ |
421 | get_time(NVRAM, &tm); | |
abd0c6bd | 422 | retval = to_bcd(tm.tm_min); |
a541f297 FB |
423 | break; |
424 | case 0x1FFB: | |
4aed2c33 | 425 | case 0x07FB: |
a541f297 FB |
426 | /* hours (BCD) */ |
427 | get_time(NVRAM, &tm); | |
abd0c6bd | 428 | retval = to_bcd(tm.tm_hour); |
a541f297 FB |
429 | break; |
430 | case 0x1FFC: | |
4aed2c33 | 431 | case 0x07FC: |
a541f297 FB |
432 | /* day of the week / century */ |
433 | get_time(NVRAM, &tm); | |
4aed2c33 | 434 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
a541f297 FB |
435 | break; |
436 | case 0x1FFD: | |
4aed2c33 | 437 | case 0x07FD: |
a541f297 FB |
438 | /* date */ |
439 | get_time(NVRAM, &tm); | |
abd0c6bd | 440 | retval = to_bcd(tm.tm_mday); |
a541f297 FB |
441 | break; |
442 | case 0x1FFE: | |
4aed2c33 | 443 | case 0x07FE: |
a541f297 FB |
444 | /* month */ |
445 | get_time(NVRAM, &tm); | |
abd0c6bd | 446 | retval = to_bcd(tm.tm_mon + 1); |
a541f297 FB |
447 | break; |
448 | case 0x1FFF: | |
4aed2c33 | 449 | case 0x07FF: |
a541f297 FB |
450 | /* year */ |
451 | get_time(NVRAM, &tm); | |
7bc3018b | 452 | if (NVRAM->model == 8) { |
abd0c6bd | 453 | retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
7bc3018b | 454 | } else { |
abd0c6bd | 455 | retval = to_bcd(tm.tm_year); |
7bc3018b | 456 | } |
a541f297 FB |
457 | break; |
458 | default: | |
13ab5daa | 459 | /* Check lock registers state */ |
819385c5 | 460 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 461 | break; |
819385c5 | 462 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 463 | break; |
819385c5 FB |
464 | do_read: |
465 | if (addr < NVRAM->size) { | |
466 | retval = NVRAM->buffer[addr]; | |
a541f297 FB |
467 | } |
468 | break; | |
469 | } | |
819385c5 | 470 | if (addr > 0x1FF9 && addr < 0x2000) |
9ed1e667 | 471 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
a541f297 FB |
472 | |
473 | return retval; | |
474 | } | |
475 | ||
897b4c6c | 476 | void m48t59_toggle_lock (void *opaque, int lock) |
13ab5daa | 477 | { |
43a34704 | 478 | M48t59State *NVRAM = opaque; |
897b4c6c | 479 | |
13ab5daa FB |
480 | NVRAM->lock ^= 1 << lock; |
481 | } | |
482 | ||
a541f297 | 483 | /* IO access to NVRAM */ |
087bd055 AG |
484 | static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val, |
485 | unsigned size) | |
a541f297 | 486 | { |
43a34704 | 487 | M48t59State *NVRAM = opaque; |
a541f297 | 488 | |
9ed1e667 | 489 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); |
a541f297 FB |
490 | switch (addr) { |
491 | case 0: | |
492 | NVRAM->addr &= ~0x00FF; | |
493 | NVRAM->addr |= val; | |
494 | break; | |
495 | case 1: | |
496 | NVRAM->addr &= ~0xFF00; | |
497 | NVRAM->addr |= val << 8; | |
498 | break; | |
499 | case 3: | |
b1f88301 | 500 | m48t59_write(NVRAM, NVRAM->addr, val); |
a541f297 FB |
501 | NVRAM->addr = 0x0000; |
502 | break; | |
503 | default: | |
504 | break; | |
505 | } | |
506 | } | |
507 | ||
087bd055 | 508 | static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size) |
a541f297 | 509 | { |
43a34704 | 510 | M48t59State *NVRAM = opaque; |
13ab5daa | 511 | uint32_t retval; |
a541f297 | 512 | |
13ab5daa FB |
513 | switch (addr) { |
514 | case 3: | |
819385c5 | 515 | retval = m48t59_read(NVRAM, NVRAM->addr); |
13ab5daa FB |
516 | break; |
517 | default: | |
518 | retval = -1; | |
519 | break; | |
520 | } | |
9ed1e667 | 521 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
a541f297 | 522 | |
13ab5daa | 523 | return retval; |
a541f297 FB |
524 | } |
525 | ||
a8170e5e | 526 | static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value) |
e1bb04f7 | 527 | { |
43a34704 | 528 | M48t59State *NVRAM = opaque; |
3b46e624 | 529 | |
819385c5 | 530 | m48t59_write(NVRAM, addr, value & 0xff); |
e1bb04f7 FB |
531 | } |
532 | ||
a8170e5e | 533 | static void nvram_writew (void *opaque, hwaddr addr, uint32_t value) |
e1bb04f7 | 534 | { |
43a34704 | 535 | M48t59State *NVRAM = opaque; |
3b46e624 | 536 | |
819385c5 FB |
537 | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
538 | m48t59_write(NVRAM, addr + 1, value & 0xff); | |
e1bb04f7 FB |
539 | } |
540 | ||
a8170e5e | 541 | static void nvram_writel (void *opaque, hwaddr addr, uint32_t value) |
e1bb04f7 | 542 | { |
43a34704 | 543 | M48t59State *NVRAM = opaque; |
3b46e624 | 544 | |
819385c5 FB |
545 | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
546 | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); | |
547 | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); | |
548 | m48t59_write(NVRAM, addr + 3, value & 0xff); | |
e1bb04f7 FB |
549 | } |
550 | ||
a8170e5e | 551 | static uint32_t nvram_readb (void *opaque, hwaddr addr) |
e1bb04f7 | 552 | { |
43a34704 | 553 | M48t59State *NVRAM = opaque; |
819385c5 | 554 | uint32_t retval; |
3b46e624 | 555 | |
819385c5 | 556 | retval = m48t59_read(NVRAM, addr); |
e1bb04f7 FB |
557 | return retval; |
558 | } | |
559 | ||
a8170e5e | 560 | static uint32_t nvram_readw (void *opaque, hwaddr addr) |
e1bb04f7 | 561 | { |
43a34704 | 562 | M48t59State *NVRAM = opaque; |
819385c5 | 563 | uint32_t retval; |
3b46e624 | 564 | |
819385c5 FB |
565 | retval = m48t59_read(NVRAM, addr) << 8; |
566 | retval |= m48t59_read(NVRAM, addr + 1); | |
e1bb04f7 FB |
567 | return retval; |
568 | } | |
569 | ||
a8170e5e | 570 | static uint32_t nvram_readl (void *opaque, hwaddr addr) |
e1bb04f7 | 571 | { |
43a34704 | 572 | M48t59State *NVRAM = opaque; |
819385c5 | 573 | uint32_t retval; |
e1bb04f7 | 574 | |
819385c5 FB |
575 | retval = m48t59_read(NVRAM, addr) << 24; |
576 | retval |= m48t59_read(NVRAM, addr + 1) << 16; | |
577 | retval |= m48t59_read(NVRAM, addr + 2) << 8; | |
578 | retval |= m48t59_read(NVRAM, addr + 3); | |
e1bb04f7 FB |
579 | return retval; |
580 | } | |
581 | ||
5a31cd68 AK |
582 | static const MemoryRegionOps nvram_ops = { |
583 | .old_mmio = { | |
584 | .read = { nvram_readb, nvram_readw, nvram_readl, }, | |
585 | .write = { nvram_writeb, nvram_writew, nvram_writel, }, | |
586 | }, | |
587 | .endianness = DEVICE_NATIVE_ENDIAN, | |
e1bb04f7 | 588 | }; |
819385c5 | 589 | |
fd484ae4 JQ |
590 | static const VMStateDescription vmstate_m48t59 = { |
591 | .name = "m48t59", | |
592 | .version_id = 1, | |
593 | .minimum_version_id = 1, | |
594 | .minimum_version_id_old = 1, | |
595 | .fields = (VMStateField[]) { | |
596 | VMSTATE_UINT8(lock, M48t59State), | |
597 | VMSTATE_UINT16(addr, M48t59State), | |
598 | VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), | |
599 | VMSTATE_END_OF_LIST() | |
600 | } | |
601 | }; | |
3ccacc4a | 602 | |
43a34704 | 603 | static void m48t59_reset_common(M48t59State *NVRAM) |
3ccacc4a | 604 | { |
6e6b7363 BS |
605 | NVRAM->addr = 0; |
606 | NVRAM->lock = 0; | |
3ccacc4a BS |
607 | if (NVRAM->alrm_timer != NULL) |
608 | qemu_del_timer(NVRAM->alrm_timer); | |
609 | ||
610 | if (NVRAM->wd_timer != NULL) | |
611 | qemu_del_timer(NVRAM->wd_timer); | |
612 | } | |
613 | ||
285e468d BS |
614 | static void m48t59_reset_isa(DeviceState *d) |
615 | { | |
a2772c70 | 616 | M48t59ISAState *isa = ISA_M48T59(d); |
43a34704 | 617 | M48t59State *NVRAM = &isa->state; |
285e468d BS |
618 | |
619 | m48t59_reset_common(NVRAM); | |
620 | } | |
621 | ||
622 | static void m48t59_reset_sysbus(DeviceState *d) | |
623 | { | |
624 | M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev); | |
43a34704 | 625 | M48t59State *NVRAM = &sys->state; |
285e468d BS |
626 | |
627 | m48t59_reset_common(NVRAM); | |
628 | } | |
629 | ||
9936d6e4 | 630 | static const MemoryRegionOps m48t59_io_ops = { |
087bd055 AG |
631 | .read = NVRAM_readb, |
632 | .write = NVRAM_writeb, | |
633 | .impl = { | |
634 | .min_access_size = 1, | |
635 | .max_access_size = 1, | |
636 | }, | |
637 | .endianness = DEVICE_LITTLE_ENDIAN, | |
9936d6e4 RH |
638 | }; |
639 | ||
a541f297 | 640 | /* Initialisation routine */ |
a8170e5e | 641 | M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, |
7bc3018b | 642 | uint32_t io_base, uint16_t size, int model) |
a541f297 | 643 | { |
d27cf0ae BS |
644 | DeviceState *dev; |
645 | SysBusDevice *s; | |
f80237d4 | 646 | M48t59SysBusState *d; |
51f9b84e | 647 | M48t59State *state; |
d27cf0ae BS |
648 | |
649 | dev = qdev_create(NULL, "m48t59"); | |
7bc3018b | 650 | qdev_prop_set_uint32(dev, "model", model); |
ee6847d1 GH |
651 | qdev_prop_set_uint32(dev, "size", size); |
652 | qdev_prop_set_uint32(dev, "io_base", io_base); | |
e23a1b33 | 653 | qdev_init_nofail(dev); |
1356b98d | 654 | s = SYS_BUS_DEVICE(dev); |
51f9b84e HP |
655 | d = FROM_SYSBUS(M48t59SysBusState, s); |
656 | state = &d->state; | |
d27cf0ae | 657 | sysbus_connect_irq(s, 0, IRQ); |
087bd055 | 658 | memory_region_init_io(&d->io, &m48t59_io_ops, state, "m48t59", 4); |
819385c5 | 659 | if (io_base != 0) { |
087bd055 | 660 | memory_region_add_subregion(get_system_io(), io_base, &d->io); |
819385c5 | 661 | } |
e1bb04f7 | 662 | if (mem_base != 0) { |
d27cf0ae | 663 | sysbus_mmio_map(s, 0, mem_base); |
e1bb04f7 | 664 | } |
d27cf0ae | 665 | |
51f9b84e | 666 | return state; |
d27cf0ae BS |
667 | } |
668 | ||
48a18b3c | 669 | M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, |
7bc3018b | 670 | int model) |
d27cf0ae | 671 | { |
f80237d4 | 672 | M48t59ISAState *d; |
a2772c70 AF |
673 | ISADevice *isadev; |
674 | DeviceState *dev; | |
43a34704 | 675 | M48t59State *s; |
f80237d4 | 676 | |
a2772c70 AF |
677 | isadev = isa_create(bus, TYPE_ISA_M48T59); |
678 | dev = DEVICE(isadev); | |
679 | qdev_prop_set_uint32(dev, "model", model); | |
680 | qdev_prop_set_uint32(dev, "size", size); | |
681 | qdev_prop_set_uint32(dev, "io_base", io_base); | |
682 | qdev_init_nofail(dev); | |
683 | d = ISA_M48T59(isadev); | |
f80237d4 | 684 | s = &d->state; |
d27cf0ae | 685 | |
9936d6e4 | 686 | memory_region_init_io(&d->io, &m48t59_io_ops, s, "m48t59", 4); |
f80237d4 | 687 | if (io_base != 0) { |
a2772c70 | 688 | isa_register_ioport(isadev, &d->io, io_base); |
f80237d4 | 689 | } |
d27cf0ae | 690 | |
f80237d4 BS |
691 | return s; |
692 | } | |
d27cf0ae | 693 | |
db895a1e | 694 | static void m48t59_realize_common(M48t59State *s, Error **errp) |
f80237d4 | 695 | { |
7267c094 | 696 | s->buffer = g_malloc0(s->size); |
7bc3018b | 697 | if (s->model == 59) { |
1d849502 | 698 | s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s); |
74475455 | 699 | s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s); |
819385c5 | 700 | } |
f6503059 | 701 | qemu_get_timedate(&s->alarm, 0); |
13ab5daa | 702 | |
fd484ae4 | 703 | vmstate_register(NULL, -1, &vmstate_m48t59, s); |
f80237d4 BS |
704 | } |
705 | ||
db895a1e | 706 | static void m48t59_isa_realize(DeviceState *dev, Error **errp) |
f80237d4 | 707 | { |
db895a1e | 708 | ISADevice *isadev = ISA_DEVICE(dev); |
a2772c70 | 709 | M48t59ISAState *d = ISA_M48T59(dev); |
43a34704 | 710 | M48t59State *s = &d->state; |
f80237d4 | 711 | |
db895a1e AF |
712 | isa_init_irq(isadev, &s->IRQ, 8); |
713 | m48t59_realize_common(s, errp); | |
d27cf0ae | 714 | } |
3ccacc4a | 715 | |
f80237d4 BS |
716 | static int m48t59_init1(SysBusDevice *dev) |
717 | { | |
718 | M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); | |
43a34704 | 719 | M48t59State *s = &d->state; |
db895a1e | 720 | Error *err = NULL; |
f80237d4 BS |
721 | |
722 | sysbus_init_irq(dev, &s->IRQ); | |
723 | ||
5a31cd68 | 724 | memory_region_init_io(&s->iomem, &nvram_ops, s, "m48t59.nvram", s->size); |
750ecd44 | 725 | sysbus_init_mmio(dev, &s->iomem); |
db895a1e AF |
726 | m48t59_realize_common(s, &err); |
727 | if (err != NULL) { | |
728 | error_free(err); | |
729 | return -1; | |
730 | } | |
f80237d4 BS |
731 | |
732 | return 0; | |
733 | } | |
734 | ||
39bffca2 AL |
735 | static Property m48t59_isa_properties[] = { |
736 | DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), | |
7bc3018b | 737 | DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), |
39bffca2 AL |
738 | DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
739 | DEFINE_PROP_END_OF_LIST(), | |
740 | }; | |
741 | ||
a2772c70 | 742 | static void m48t59_isa_class_init(ObjectClass *klass, void *data) |
8f04ee08 | 743 | { |
39bffca2 | 744 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e AF |
745 | |
746 | dc->realize = m48t59_isa_realize; | |
39bffca2 AL |
747 | dc->no_user = 1; |
748 | dc->reset = m48t59_reset_isa; | |
749 | dc->props = m48t59_isa_properties; | |
8f04ee08 AL |
750 | } |
751 | ||
8c43a6f0 | 752 | static const TypeInfo m48t59_isa_info = { |
a2772c70 | 753 | .name = TYPE_ISA_M48T59, |
39bffca2 AL |
754 | .parent = TYPE_ISA_DEVICE, |
755 | .instance_size = sizeof(M48t59ISAState), | |
a2772c70 | 756 | .class_init = m48t59_isa_class_init, |
f80237d4 BS |
757 | }; |
758 | ||
999e12bb AL |
759 | static Property m48t59_properties[] = { |
760 | DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), | |
7bc3018b | 761 | DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), |
999e12bb AL |
762 | DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
763 | DEFINE_PROP_END_OF_LIST(), | |
764 | }; | |
765 | ||
766 | static void m48t59_class_init(ObjectClass *klass, void *data) | |
767 | { | |
39bffca2 | 768 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
769 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
770 | ||
771 | k->init = m48t59_init1; | |
39bffca2 AL |
772 | dc->reset = m48t59_reset_sysbus; |
773 | dc->props = m48t59_properties; | |
999e12bb AL |
774 | } |
775 | ||
8c43a6f0 | 776 | static const TypeInfo m48t59_info = { |
39bffca2 AL |
777 | .name = "m48t59", |
778 | .parent = TYPE_SYS_BUS_DEVICE, | |
779 | .instance_size = sizeof(M48t59SysBusState), | |
780 | .class_init = m48t59_class_init, | |
ee6847d1 GH |
781 | }; |
782 | ||
83f7d43a | 783 | static void m48t59_register_types(void) |
d27cf0ae | 784 | { |
39bffca2 AL |
785 | type_register_static(&m48t59_info); |
786 | type_register_static(&m48t59_isa_info); | |
a541f297 | 787 | } |
d27cf0ae | 788 | |
83f7d43a | 789 | type_init(m48t59_register_types) |