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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU MC146818 RTC emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
b6a0aa05 | 24 | #include "qemu/osdep.h" |
4771d756 | 25 | #include "config-target.h" |
83c9f4ca | 26 | #include "hw/hw.h" |
1de7afc9 | 27 | #include "qemu/timer.h" |
9c17d615 | 28 | #include "sysemu/sysemu.h" |
0d09e41a | 29 | #include "hw/timer/mc146818rtc.h" |
7b1b5d19 | 30 | #include "qapi/visitor.h" |
e010ad8f | 31 | #include "qapi-event.h" |
f2ae8abf | 32 | #include "qmp-commands.h" |
80cabfad | 33 | |
d362e757 | 34 | #ifdef TARGET_I386 |
0d09e41a | 35 | #include "hw/i386/apic.h" |
d362e757 JK |
36 | #endif |
37 | ||
80cabfad | 38 | //#define DEBUG_CMOS |
aa6f63ff | 39 | //#define DEBUG_COALESCED |
80cabfad | 40 | |
ec51e364 IY |
41 | #ifdef DEBUG_CMOS |
42 | # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
43 | #else | |
44 | # define CMOS_DPRINTF(format, ...) do { } while (0) | |
45 | #endif | |
46 | ||
aa6f63ff BS |
47 | #ifdef DEBUG_COALESCED |
48 | # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) | |
49 | #else | |
50 | # define DPRINTF_C(format, ...) do { } while (0) | |
51 | #endif | |
52 | ||
00cf5774 PB |
53 | #define SEC_PER_MIN 60 |
54 | #define MIN_PER_HOUR 60 | |
55 | #define SEC_PER_HOUR 3600 | |
56 | #define HOUR_PER_DAY 24 | |
57 | #define SEC_PER_DAY 86400 | |
56038ef6 | 58 | |
dd17765b | 59 | #define RTC_REINJECT_ON_ACK_COUNT 20 |
e46deaba | 60 | #define RTC_CLOCK_RATE 32768 |
13566fe3 | 61 | #define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768) |
ba32edab | 62 | |
0e41271e AF |
63 | #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC) |
64 | ||
1d914fa0 | 65 | typedef struct RTCState { |
0e41271e AF |
66 | ISADevice parent_obj; |
67 | ||
b2c5009b | 68 | MemoryRegion io; |
dff38e7b FB |
69 | uint8_t cmos_data[128]; |
70 | uint8_t cmos_index; | |
32e0c826 | 71 | int32_t base_year; |
56038ef6 YZ |
72 | uint64_t base_rtc; |
73 | uint64_t last_update; | |
74 | int64_t offset; | |
d537cf6c | 75 | qemu_irq irq; |
18c6e2ff | 76 | int it_shift; |
dff38e7b FB |
77 | /* periodic timer */ |
78 | QEMUTimer *periodic_timer; | |
79 | int64_t next_periodic_time; | |
56038ef6 YZ |
80 | /* update-ended timer */ |
81 | QEMUTimer *update_timer; | |
00cf5774 | 82 | uint64_t next_alarm_time; |
ba32edab | 83 | uint16_t irq_reinject_on_ack_count; |
73822ec8 AL |
84 | uint32_t irq_coalesced; |
85 | uint32_t period; | |
93b66569 | 86 | QEMUTimer *coalesced_timer; |
17604dac | 87 | Notifier clock_reset_notifier; |
433acf0d | 88 | LostTickPolicy lost_tick_policy; |
da98c8eb | 89 | Notifier suspend_notifier; |
f2ae8abf | 90 | QLIST_ENTRY(RTCState) link; |
1d914fa0 | 91 | } RTCState; |
dff38e7b FB |
92 | |
93 | static void rtc_set_time(RTCState *s); | |
56038ef6 | 94 | static void rtc_update_time(RTCState *s); |
e2826cf4 | 95 | static void rtc_set_cmos(RTCState *s, const struct tm *tm); |
56038ef6 | 96 | static inline int rtc_from_bcd(RTCState *s, int a); |
00cf5774 | 97 | static uint64_t get_next_alarm(RTCState *s); |
56038ef6 | 98 | |
41a9b8b2 YZ |
99 | static inline bool rtc_running(RTCState *s) |
100 | { | |
101 | return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && | |
102 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); | |
103 | } | |
104 | ||
56038ef6 YZ |
105 | static uint64_t get_guest_rtc_ns(RTCState *s) |
106 | { | |
107 | uint64_t guest_rtc; | |
884f17c2 | 108 | uint64_t guest_clock = qemu_clock_get_ns(rtc_clock); |
56038ef6 | 109 | |
73bcb24d RS |
110 | guest_rtc = s->base_rtc * NANOSECONDS_PER_SECOND + |
111 | guest_clock - s->last_update + s->offset; | |
56038ef6 YZ |
112 | return guest_rtc; |
113 | } | |
dff38e7b | 114 | |
93b66569 AL |
115 | #ifdef TARGET_I386 |
116 | static void rtc_coalesced_timer_update(RTCState *s) | |
117 | { | |
118 | if (s->irq_coalesced == 0) { | |
bc72ad67 | 119 | timer_del(s->coalesced_timer); |
93b66569 AL |
120 | } else { |
121 | /* divide each RTC interval to 2 - 8 smaller intervals */ | |
122 | int c = MIN(s->irq_coalesced, 7) + 1; | |
884f17c2 | 123 | int64_t next_clock = qemu_clock_get_ns(rtc_clock) + |
73bcb24d | 124 | muldiv64(s->period / c, NANOSECONDS_PER_SECOND, RTC_CLOCK_RATE); |
bc72ad67 | 125 | timer_mod(s->coalesced_timer, next_clock); |
93b66569 AL |
126 | } |
127 | } | |
128 | ||
129 | static void rtc_coalesced_timer(void *opaque) | |
130 | { | |
131 | RTCState *s = opaque; | |
132 | ||
133 | if (s->irq_coalesced != 0) { | |
134 | apic_reset_irq_delivered(); | |
135 | s->cmos_data[RTC_REG_C] |= 0xc0; | |
aa6f63ff | 136 | DPRINTF_C("cmos: injecting from timer\n"); |
7d932dfd | 137 | qemu_irq_raise(s->irq); |
93b66569 AL |
138 | if (apic_get_irq_delivered()) { |
139 | s->irq_coalesced--; | |
aa6f63ff BS |
140 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
141 | s->irq_coalesced); | |
93b66569 AL |
142 | } |
143 | } | |
144 | ||
145 | rtc_coalesced_timer_update(s); | |
146 | } | |
147 | #endif | |
148 | ||
56038ef6 | 149 | /* handle periodic timer */ |
c4c18e24 | 150 | static void periodic_timer_update(RTCState *s, int64_t current_time) |
dff38e7b FB |
151 | { |
152 | int period_code, period; | |
153 | int64_t cur_clock, next_irq_clock; | |
154 | ||
155 | period_code = s->cmos_data[RTC_REG_A] & 0x0f; | |
100d9891 | 156 | if (period_code != 0 |
c2d30667 | 157 | && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) { |
dff38e7b FB |
158 | if (period_code <= 2) |
159 | period_code += 7; | |
160 | /* period in 32 Khz cycles */ | |
161 | period = 1 << (period_code - 1); | |
73822ec8 | 162 | #ifdef TARGET_I386 |
aa6f63ff | 163 | if (period != s->period) { |
73822ec8 | 164 | s->irq_coalesced = (s->irq_coalesced * s->period) / period; |
aa6f63ff BS |
165 | DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced); |
166 | } | |
73822ec8 AL |
167 | s->period = period; |
168 | #endif | |
dff38e7b | 169 | /* compute 32 khz clock */ |
73bcb24d RS |
170 | cur_clock = |
171 | muldiv64(current_time, RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND); | |
172 | ||
dff38e7b | 173 | next_irq_clock = (cur_clock & ~(period - 1)) + period; |
73bcb24d RS |
174 | s->next_periodic_time = muldiv64(next_irq_clock, NANOSECONDS_PER_SECOND, |
175 | RTC_CLOCK_RATE) + 1; | |
bc72ad67 | 176 | timer_mod(s->periodic_timer, s->next_periodic_time); |
dff38e7b | 177 | } else { |
73822ec8 AL |
178 | #ifdef TARGET_I386 |
179 | s->irq_coalesced = 0; | |
180 | #endif | |
bc72ad67 | 181 | timer_del(s->periodic_timer); |
dff38e7b FB |
182 | } |
183 | } | |
184 | ||
185 | static void rtc_periodic_timer(void *opaque) | |
186 | { | |
187 | RTCState *s = opaque; | |
188 | ||
c4c18e24 | 189 | periodic_timer_update(s, s->next_periodic_time); |
663447d4 | 190 | s->cmos_data[RTC_REG_C] |= REG_C_PF; |
100d9891 | 191 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { |
663447d4 | 192 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
93b66569 | 193 | #ifdef TARGET_I386 |
104059da | 194 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
ba32edab GN |
195 | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT) |
196 | s->irq_reinject_on_ack_count = 0; | |
93b66569 | 197 | apic_reset_irq_delivered(); |
7d932dfd | 198 | qemu_irq_raise(s->irq); |
93b66569 AL |
199 | if (!apic_get_irq_delivered()) { |
200 | s->irq_coalesced++; | |
201 | rtc_coalesced_timer_update(s); | |
aa6f63ff BS |
202 | DPRINTF_C("cmos: coalesced irqs increased to %d\n", |
203 | s->irq_coalesced); | |
93b66569 AL |
204 | } |
205 | } else | |
206 | #endif | |
7d932dfd | 207 | qemu_irq_raise(s->irq); |
100d9891 | 208 | } |
dff38e7b | 209 | } |
80cabfad | 210 | |
56038ef6 YZ |
211 | /* handle update-ended timer */ |
212 | static void check_update_timer(RTCState *s) | |
213 | { | |
214 | uint64_t next_update_time; | |
215 | uint64_t guest_nsec; | |
00cf5774 | 216 | int next_alarm_sec; |
56038ef6 | 217 | |
41a9b8b2 YZ |
218 | /* From the data sheet: "Holding the dividers in reset prevents |
219 | * interrupts from operating, while setting the SET bit allows" | |
220 | * them to occur. However, it will prevent an alarm interrupt | |
221 | * from occurring, because the time of day is not updated. | |
56038ef6 | 222 | */ |
41a9b8b2 | 223 | if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { |
bc72ad67 | 224 | timer_del(s->update_timer); |
41a9b8b2 YZ |
225 | return; |
226 | } | |
56038ef6 YZ |
227 | if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && |
228 | (s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
bc72ad67 | 229 | timer_del(s->update_timer); |
56038ef6 YZ |
230 | return; |
231 | } | |
232 | if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && | |
233 | (s->cmos_data[RTC_REG_C] & REG_C_AF)) { | |
bc72ad67 | 234 | timer_del(s->update_timer); |
56038ef6 YZ |
235 | return; |
236 | } | |
237 | ||
13566fe3 | 238 | guest_nsec = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND; |
00cf5774 | 239 | /* if UF is clear, reprogram to next second */ |
884f17c2 | 240 | next_update_time = qemu_clock_get_ns(rtc_clock) |
13566fe3 | 241 | + NANOSECONDS_PER_SECOND - guest_nsec; |
00cf5774 PB |
242 | |
243 | /* Compute time of next alarm. One second is already accounted | |
244 | * for in next_update_time. | |
245 | */ | |
246 | next_alarm_sec = get_next_alarm(s); | |
13566fe3 SH |
247 | s->next_alarm_time = next_update_time + |
248 | (next_alarm_sec - 1) * NANOSECONDS_PER_SECOND; | |
00cf5774 PB |
249 | |
250 | if (s->cmos_data[RTC_REG_C] & REG_C_UF) { | |
251 | /* UF is set, but AF is clear. Program the timer to target | |
252 | * the alarm time. */ | |
253 | next_update_time = s->next_alarm_time; | |
254 | } | |
e93379b0 | 255 | if (next_update_time != timer_expire_time_ns(s->update_timer)) { |
bc72ad67 | 256 | timer_mod(s->update_timer, next_update_time); |
56038ef6 YZ |
257 | } |
258 | } | |
259 | ||
260 | static inline uint8_t convert_hour(RTCState *s, uint8_t hour) | |
261 | { | |
262 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { | |
263 | hour %= 12; | |
264 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
265 | hour += 12; | |
266 | } | |
267 | } | |
268 | return hour; | |
269 | } | |
270 | ||
00cf5774 | 271 | static uint64_t get_next_alarm(RTCState *s) |
56038ef6 | 272 | { |
00cf5774 PB |
273 | int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec; |
274 | int32_t hour, min, sec; | |
275 | ||
276 | rtc_update_time(s); | |
56038ef6 YZ |
277 | |
278 | alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]); | |
279 | alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]); | |
280 | alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]); | |
00cf5774 | 281 | alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour); |
56038ef6 YZ |
282 | |
283 | cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); | |
284 | cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
285 | cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]); | |
286 | cur_hour = convert_hour(s, cur_hour); | |
287 | ||
00cf5774 PB |
288 | if (alarm_hour == -1) { |
289 | alarm_hour = cur_hour; | |
290 | if (alarm_min == -1) { | |
291 | alarm_min = cur_min; | |
292 | if (alarm_sec == -1) { | |
293 | alarm_sec = cur_sec + 1; | |
294 | } else if (cur_sec > alarm_sec) { | |
295 | alarm_min++; | |
296 | } | |
297 | } else if (cur_min == alarm_min) { | |
298 | if (alarm_sec == -1) { | |
299 | alarm_sec = cur_sec + 1; | |
300 | } else { | |
301 | if (cur_sec > alarm_sec) { | |
302 | alarm_hour++; | |
303 | } | |
304 | } | |
305 | if (alarm_sec == SEC_PER_MIN) { | |
306 | /* wrap to next hour, minutes is not in don't care mode */ | |
307 | alarm_sec = 0; | |
308 | alarm_hour++; | |
309 | } | |
310 | } else if (cur_min > alarm_min) { | |
311 | alarm_hour++; | |
312 | } | |
313 | } else if (cur_hour == alarm_hour) { | |
314 | if (alarm_min == -1) { | |
315 | alarm_min = cur_min; | |
316 | if (alarm_sec == -1) { | |
317 | alarm_sec = cur_sec + 1; | |
318 | } else if (cur_sec > alarm_sec) { | |
319 | alarm_min++; | |
320 | } | |
321 | ||
322 | if (alarm_sec == SEC_PER_MIN) { | |
323 | alarm_sec = 0; | |
324 | alarm_min++; | |
325 | } | |
326 | /* wrap to next day, hour is not in don't care mode */ | |
327 | alarm_min %= MIN_PER_HOUR; | |
328 | } else if (cur_min == alarm_min) { | |
329 | if (alarm_sec == -1) { | |
330 | alarm_sec = cur_sec + 1; | |
331 | } | |
332 | /* wrap to next day, hours+minutes not in don't care mode */ | |
333 | alarm_sec %= SEC_PER_MIN; | |
334 | } | |
56038ef6 | 335 | } |
56038ef6 | 336 | |
00cf5774 PB |
337 | /* values that are still don't care fire at the next min/sec */ |
338 | if (alarm_min == -1) { | |
339 | alarm_min = 0; | |
340 | } | |
341 | if (alarm_sec == -1) { | |
342 | alarm_sec = 0; | |
343 | } | |
344 | ||
345 | /* keep values in range */ | |
346 | if (alarm_sec == SEC_PER_MIN) { | |
347 | alarm_sec = 0; | |
348 | alarm_min++; | |
349 | } | |
350 | if (alarm_min == MIN_PER_HOUR) { | |
351 | alarm_min = 0; | |
352 | alarm_hour++; | |
353 | } | |
354 | alarm_hour %= HOUR_PER_DAY; | |
355 | ||
356 | hour = alarm_hour - cur_hour; | |
357 | min = hour * MIN_PER_HOUR + alarm_min - cur_min; | |
358 | sec = min * SEC_PER_MIN + alarm_sec - cur_sec; | |
359 | return sec <= 0 ? sec + SEC_PER_DAY : sec; | |
56038ef6 YZ |
360 | } |
361 | ||
362 | static void rtc_update_timer(void *opaque) | |
363 | { | |
364 | RTCState *s = opaque; | |
365 | int32_t irqs = REG_C_UF; | |
366 | int32_t new_irqs; | |
367 | ||
41a9b8b2 YZ |
368 | assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60); |
369 | ||
56038ef6 YZ |
370 | /* UIP might have been latched, update time and clear it. */ |
371 | rtc_update_time(s); | |
372 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
373 | ||
884f17c2 | 374 | if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) { |
56038ef6 YZ |
375 | irqs |= REG_C_AF; |
376 | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { | |
377 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC); | |
378 | } | |
379 | } | |
00cf5774 | 380 | |
56038ef6 YZ |
381 | new_irqs = irqs & ~s->cmos_data[RTC_REG_C]; |
382 | s->cmos_data[RTC_REG_C] |= irqs; | |
383 | if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) { | |
384 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
385 | qemu_irq_raise(s->irq); | |
386 | } | |
387 | check_update_timer(s); | |
388 | } | |
389 | ||
0da8c842 AG |
390 | static void cmos_ioport_write(void *opaque, hwaddr addr, |
391 | uint64_t data, unsigned size) | |
80cabfad | 392 | { |
b41a2cd1 | 393 | RTCState *s = opaque; |
80cabfad FB |
394 | |
395 | if ((addr & 1) == 0) { | |
396 | s->cmos_index = data & 0x7f; | |
397 | } else { | |
c5539cb4 | 398 | CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n", |
ec51e364 | 399 | s->cmos_index, data); |
dff38e7b | 400 | switch(s->cmos_index) { |
80cabfad FB |
401 | case RTC_SECONDS_ALARM: |
402 | case RTC_MINUTES_ALARM: | |
403 | case RTC_HOURS_ALARM: | |
80cabfad | 404 | s->cmos_data[s->cmos_index] = data; |
56038ef6 | 405 | check_update_timer(s); |
80cabfad | 406 | break; |
e67edb94 PB |
407 | case RTC_IBM_PS2_CENTURY_BYTE: |
408 | s->cmos_index = RTC_CENTURY; | |
409 | /* fall through */ | |
410 | case RTC_CENTURY: | |
80cabfad FB |
411 | case RTC_SECONDS: |
412 | case RTC_MINUTES: | |
413 | case RTC_HOURS: | |
414 | case RTC_DAY_OF_WEEK: | |
415 | case RTC_DAY_OF_MONTH: | |
416 | case RTC_MONTH: | |
417 | case RTC_YEAR: | |
418 | s->cmos_data[s->cmos_index] = data; | |
dff38e7b | 419 | /* if in set mode, do not update the time */ |
41a9b8b2 | 420 | if (rtc_running(s)) { |
dff38e7b | 421 | rtc_set_time(s); |
56038ef6 | 422 | check_update_timer(s); |
dff38e7b | 423 | } |
80cabfad FB |
424 | break; |
425 | case RTC_REG_A: | |
41a9b8b2 YZ |
426 | if ((data & 0x60) == 0x60) { |
427 | if (rtc_running(s)) { | |
428 | rtc_update_time(s); | |
429 | } | |
430 | /* What happens to UIP when divider reset is enabled is | |
431 | * unclear from the datasheet. Shouldn't matter much | |
432 | * though. | |
433 | */ | |
434 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
435 | } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && | |
436 | (data & 0x70) <= 0x20) { | |
437 | /* when the divider reset is removed, the first update cycle | |
438 | * begins one-half second later*/ | |
439 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
440 | s->offset = 500000000; | |
441 | rtc_set_time(s); | |
442 | } | |
443 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
444 | } | |
dff38e7b FB |
445 | /* UIP bit is read only */ |
446 | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | | |
447 | (s->cmos_data[RTC_REG_A] & REG_A_UIP); | |
884f17c2 | 448 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); |
56038ef6 | 449 | check_update_timer(s); |
dff38e7b | 450 | break; |
80cabfad | 451 | case RTC_REG_B: |
dff38e7b | 452 | if (data & REG_B_SET) { |
56038ef6 | 453 | /* update cmos to when the rtc was stopping */ |
41a9b8b2 | 454 | if (rtc_running(s)) { |
56038ef6 YZ |
455 | rtc_update_time(s); |
456 | } | |
dff38e7b FB |
457 | /* set mode: reset UIP mode */ |
458 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
459 | data &= ~REG_B_UIE; | |
460 | } else { | |
461 | /* if disabling set mode, update the time */ | |
41a9b8b2 YZ |
462 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) && |
463 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { | |
13566fe3 | 464 | s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND; |
dff38e7b FB |
465 | rtc_set_time(s); |
466 | } | |
467 | } | |
9324cc50 YZ |
468 | /* if an interrupt flag is already set when the interrupt |
469 | * becomes enabled, raise an interrupt immediately. */ | |
470 | if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) { | |
471 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
472 | qemu_irq_raise(s->irq); | |
473 | } else { | |
474 | s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF; | |
475 | qemu_irq_lower(s->irq); | |
476 | } | |
bedc572e | 477 | s->cmos_data[RTC_REG_B] = data; |
884f17c2 | 478 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); |
56038ef6 | 479 | check_update_timer(s); |
80cabfad FB |
480 | break; |
481 | case RTC_REG_C: | |
482 | case RTC_REG_D: | |
483 | /* cannot write to them */ | |
484 | break; | |
485 | default: | |
486 | s->cmos_data[s->cmos_index] = data; | |
487 | break; | |
488 | } | |
489 | } | |
490 | } | |
491 | ||
abd0c6bd | 492 | static inline int rtc_to_bcd(RTCState *s, int a) |
80cabfad | 493 | { |
6f1bf24d | 494 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
495 | return a; |
496 | } else { | |
497 | return ((a / 10) << 4) | (a % 10); | |
498 | } | |
80cabfad FB |
499 | } |
500 | ||
abd0c6bd | 501 | static inline int rtc_from_bcd(RTCState *s, int a) |
80cabfad | 502 | { |
00cf5774 PB |
503 | if ((a & 0xc0) == 0xc0) { |
504 | return -1; | |
505 | } | |
6f1bf24d | 506 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
507 | return a; |
508 | } else { | |
509 | return ((a >> 4) * 10) + (a & 0x0f); | |
510 | } | |
511 | } | |
512 | ||
e2826cf4 | 513 | static void rtc_get_time(RTCState *s, struct tm *tm) |
dff38e7b | 514 | { |
abd0c6bd PB |
515 | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
516 | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
517 | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); | |
3b89eb43 PB |
518 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { |
519 | tm->tm_hour %= 12; | |
520 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
521 | tm->tm_hour += 12; | |
522 | } | |
43f493af | 523 | } |
abd0c6bd PB |
524 | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1; |
525 | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); | |
526 | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; | |
b8994faf PB |
527 | tm->tm_year = |
528 | rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year + | |
529 | rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900; | |
e2826cf4 PB |
530 | } |
531 | ||
f2ae8abf MT |
532 | static QLIST_HEAD(, RTCState) rtc_devices = |
533 | QLIST_HEAD_INITIALIZER(rtc_devices); | |
534 | ||
535 | #ifdef TARGET_I386 | |
536 | void qmp_rtc_reset_reinjection(Error **errp) | |
537 | { | |
538 | RTCState *s; | |
539 | ||
540 | QLIST_FOREACH(s, &rtc_devices, link) { | |
541 | s->irq_coalesced = 0; | |
542 | } | |
543 | } | |
544 | #endif | |
545 | ||
e2826cf4 PB |
546 | static void rtc_set_time(RTCState *s) |
547 | { | |
548 | struct tm tm; | |
80cd3478 | 549 | |
e2826cf4 | 550 | rtc_get_time(s, &tm); |
e2826cf4 | 551 | s->base_rtc = mktimegm(&tm); |
884f17c2 | 552 | s->last_update = qemu_clock_get_ns(rtc_clock); |
56038ef6 | 553 | |
e010ad8f | 554 | qapi_event_send_rtc_change(qemu_timedate_diff(&tm), &error_abort); |
43f493af FB |
555 | } |
556 | ||
e2826cf4 | 557 | static void rtc_set_cmos(RTCState *s, const struct tm *tm) |
43f493af | 558 | { |
42fc73a1 | 559 | int year; |
dff38e7b | 560 | |
abd0c6bd PB |
561 | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
562 | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); | |
c29cd656 | 563 | if (s->cmos_data[RTC_REG_B] & REG_B_24H) { |
43f493af | 564 | /* 24 hour format */ |
abd0c6bd | 565 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
43f493af FB |
566 | } else { |
567 | /* 12 hour format */ | |
3b89eb43 PB |
568 | int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12; |
569 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h); | |
43f493af FB |
570 | if (tm->tm_hour >= 12) |
571 | s->cmos_data[RTC_HOURS] |= 0x80; | |
572 | } | |
abd0c6bd PB |
573 | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1); |
574 | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); | |
575 | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1); | |
b8994faf PB |
576 | year = tm->tm_year + 1900 - s->base_year; |
577 | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100); | |
578 | s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100); | |
43f493af FB |
579 | } |
580 | ||
56038ef6 | 581 | static void rtc_update_time(RTCState *s) |
43f493af | 582 | { |
56038ef6 YZ |
583 | struct tm ret; |
584 | time_t guest_sec; | |
585 | int64_t guest_nsec; | |
586 | ||
587 | guest_nsec = get_guest_rtc_ns(s); | |
13566fe3 | 588 | guest_sec = guest_nsec / NANOSECONDS_PER_SECOND; |
56038ef6 | 589 | gmtime_r(&guest_sec, &ret); |
02c6ccc6 AH |
590 | |
591 | /* Is SET flag of Register B disabled? */ | |
592 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) { | |
593 | rtc_set_cmos(s, &ret); | |
594 | } | |
43f493af FB |
595 | } |
596 | ||
56038ef6 | 597 | static int update_in_progress(RTCState *s) |
43f493af | 598 | { |
56038ef6 | 599 | int64_t guest_nsec; |
3b46e624 | 600 | |
41a9b8b2 | 601 | if (!rtc_running(s)) { |
56038ef6 | 602 | return 0; |
dff38e7b | 603 | } |
e93379b0 AB |
604 | if (timer_pending(s->update_timer)) { |
605 | int64_t next_update_time = timer_expire_time_ns(s->update_timer); | |
56038ef6 | 606 | /* Latch UIP until the timer expires. */ |
884f17c2 AB |
607 | if (qemu_clock_get_ns(rtc_clock) >= |
608 | (next_update_time - UIP_HOLD_LENGTH)) { | |
56038ef6 YZ |
609 | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
610 | return 1; | |
dff38e7b FB |
611 | } |
612 | } | |
613 | ||
56038ef6 YZ |
614 | guest_nsec = get_guest_rtc_ns(s); |
615 | /* UIP bit will be set at last 244us of every second. */ | |
13566fe3 SH |
616 | if ((guest_nsec % NANOSECONDS_PER_SECOND) >= |
617 | (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)) { | |
56038ef6 | 618 | return 1; |
dff38e7b | 619 | } |
56038ef6 | 620 | return 0; |
80cabfad FB |
621 | } |
622 | ||
0da8c842 AG |
623 | static uint64_t cmos_ioport_read(void *opaque, hwaddr addr, |
624 | unsigned size) | |
80cabfad | 625 | { |
b41a2cd1 | 626 | RTCState *s = opaque; |
80cabfad FB |
627 | int ret; |
628 | if ((addr & 1) == 0) { | |
629 | return 0xff; | |
630 | } else { | |
631 | switch(s->cmos_index) { | |
e67edb94 PB |
632 | case RTC_IBM_PS2_CENTURY_BYTE: |
633 | s->cmos_index = RTC_CENTURY; | |
634 | /* fall through */ | |
635 | case RTC_CENTURY: | |
80cabfad FB |
636 | case RTC_SECONDS: |
637 | case RTC_MINUTES: | |
638 | case RTC_HOURS: | |
639 | case RTC_DAY_OF_WEEK: | |
640 | case RTC_DAY_OF_MONTH: | |
641 | case RTC_MONTH: | |
642 | case RTC_YEAR: | |
56038ef6 YZ |
643 | /* if not in set mode, calibrate cmos before |
644 | * reading*/ | |
41a9b8b2 | 645 | if (rtc_running(s)) { |
56038ef6 YZ |
646 | rtc_update_time(s); |
647 | } | |
80cabfad FB |
648 | ret = s->cmos_data[s->cmos_index]; |
649 | break; | |
650 | case RTC_REG_A: | |
56038ef6 YZ |
651 | if (update_in_progress(s)) { |
652 | s->cmos_data[s->cmos_index] |= REG_A_UIP; | |
653 | } else { | |
654 | s->cmos_data[s->cmos_index] &= ~REG_A_UIP; | |
655 | } | |
80cabfad | 656 | ret = s->cmos_data[s->cmos_index]; |
80cabfad FB |
657 | break; |
658 | case RTC_REG_C: | |
659 | ret = s->cmos_data[s->cmos_index]; | |
d537cf6c | 660 | qemu_irq_lower(s->irq); |
fbc15e27 | 661 | s->cmos_data[RTC_REG_C] = 0x00; |
56038ef6 YZ |
662 | if (ret & (REG_C_UF | REG_C_AF)) { |
663 | check_update_timer(s); | |
664 | } | |
ba32edab GN |
665 | #ifdef TARGET_I386 |
666 | if(s->irq_coalesced && | |
fbc15e27 | 667 | (s->cmos_data[RTC_REG_B] & REG_B_PIE) && |
ba32edab GN |
668 | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
669 | s->irq_reinject_on_ack_count++; | |
fbc15e27 | 670 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF; |
ba32edab | 671 | apic_reset_irq_delivered(); |
aa6f63ff | 672 | DPRINTF_C("cmos: injecting on ack\n"); |
ba32edab | 673 | qemu_irq_raise(s->irq); |
aa6f63ff | 674 | if (apic_get_irq_delivered()) { |
ba32edab | 675 | s->irq_coalesced--; |
aa6f63ff BS |
676 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
677 | s->irq_coalesced); | |
678 | } | |
ba32edab GN |
679 | } |
680 | #endif | |
80cabfad FB |
681 | break; |
682 | default: | |
683 | ret = s->cmos_data[s->cmos_index]; | |
684 | break; | |
685 | } | |
ec51e364 IY |
686 | CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n", |
687 | s->cmos_index, ret); | |
80cabfad FB |
688 | return ret; |
689 | } | |
690 | } | |
691 | ||
1d914fa0 | 692 | void rtc_set_memory(ISADevice *dev, int addr, int val) |
dff38e7b | 693 | { |
0e41271e | 694 | RTCState *s = MC146818_RTC(dev); |
dff38e7b FB |
695 | if (addr >= 0 && addr <= 127) |
696 | s->cmos_data[addr] = val; | |
697 | } | |
698 | ||
b8b7456d IM |
699 | int rtc_get_memory(ISADevice *dev, int addr) |
700 | { | |
701 | RTCState *s = MC146818_RTC(dev); | |
702 | assert(addr >= 0 && addr <= 127); | |
703 | return s->cmos_data[addr]; | |
704 | } | |
705 | ||
1d914fa0 | 706 | static void rtc_set_date_from_host(ISADevice *dev) |
ea55ffb3 | 707 | { |
0e41271e | 708 | RTCState *s = MC146818_RTC(dev); |
f6503059 | 709 | struct tm tm; |
ea55ffb3 | 710 | |
f6503059 | 711 | qemu_get_timedate(&tm, 0); |
56038ef6 YZ |
712 | |
713 | s->base_rtc = mktimegm(&tm); | |
884f17c2 | 714 | s->last_update = qemu_clock_get_ns(rtc_clock); |
56038ef6 YZ |
715 | s->offset = 0; |
716 | ||
717 | /* set the CMOS date */ | |
e2826cf4 | 718 | rtc_set_cmos(s, &tm); |
ea55ffb3 TS |
719 | } |
720 | ||
6b075b8a | 721 | static int rtc_post_load(void *opaque, int version_id) |
80cabfad | 722 | { |
dff38e7b FB |
723 | RTCState *s = opaque; |
724 | ||
56038ef6 YZ |
725 | if (version_id <= 2) { |
726 | rtc_set_time(s); | |
727 | s->offset = 0; | |
728 | check_update_timer(s); | |
729 | } | |
730 | ||
ae46e239 PD |
731 | uint64_t now = qemu_clock_get_ns(rtc_clock); |
732 | if (now < s->next_periodic_time || | |
733 | now > (s->next_periodic_time + get_max_clock_jump())) { | |
734 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock)); | |
735 | } | |
736 | ||
56038ef6 | 737 | #ifdef TARGET_I386 |
048c74c4 | 738 | if (version_id >= 2) { |
104059da | 739 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
048c74c4 JQ |
740 | rtc_coalesced_timer_update(s); |
741 | } | |
048c74c4 | 742 | } |
6b075b8a | 743 | #endif |
73822ec8 AL |
744 | return 0; |
745 | } | |
73822ec8 | 746 | |
5cd8cada JQ |
747 | static bool rtc_irq_reinject_on_ack_count_needed(void *opaque) |
748 | { | |
749 | RTCState *s = (RTCState *)opaque; | |
750 | return s->irq_reinject_on_ack_count != 0; | |
751 | } | |
752 | ||
0b102153 | 753 | static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = { |
bb426311 | 754 | .name = "mc146818rtc/irq_reinject_on_ack_count", |
0b102153 PD |
755 | .version_id = 1, |
756 | .minimum_version_id = 1, | |
5cd8cada | 757 | .needed = rtc_irq_reinject_on_ack_count_needed, |
0b102153 PD |
758 | .fields = (VMStateField[]) { |
759 | VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState), | |
760 | VMSTATE_END_OF_LIST() | |
761 | } | |
762 | }; | |
763 | ||
6b075b8a JQ |
764 | static const VMStateDescription vmstate_rtc = { |
765 | .name = "mc146818rtc", | |
56038ef6 | 766 | .version_id = 3, |
6b075b8a | 767 | .minimum_version_id = 1, |
6b075b8a | 768 | .post_load = rtc_post_load, |
d49805ae | 769 | .fields = (VMStateField[]) { |
6b075b8a JQ |
770 | VMSTATE_BUFFER(cmos_data, RTCState), |
771 | VMSTATE_UINT8(cmos_index, RTCState), | |
89166459 | 772 | VMSTATE_UNUSED(7*4), |
e720677e | 773 | VMSTATE_TIMER_PTR(periodic_timer, RTCState), |
6b075b8a | 774 | VMSTATE_INT64(next_periodic_time, RTCState), |
56038ef6 | 775 | VMSTATE_UNUSED(3*8), |
6b075b8a JQ |
776 | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), |
777 | VMSTATE_UINT32_V(period, RTCState, 2), | |
56038ef6 YZ |
778 | VMSTATE_UINT64_V(base_rtc, RTCState, 3), |
779 | VMSTATE_UINT64_V(last_update, RTCState, 3), | |
780 | VMSTATE_INT64_V(offset, RTCState, 3), | |
e720677e | 781 | VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3), |
00cf5774 | 782 | VMSTATE_UINT64_V(next_alarm_time, RTCState, 3), |
6b075b8a | 783 | VMSTATE_END_OF_LIST() |
0b102153 | 784 | }, |
5cd8cada JQ |
785 | .subsections = (const VMStateDescription*[]) { |
786 | &vmstate_rtc_irq_reinject_on_ack_count, | |
787 | NULL | |
6b075b8a JQ |
788 | } |
789 | }; | |
790 | ||
17604dac JK |
791 | static void rtc_notify_clock_reset(Notifier *notifier, void *data) |
792 | { | |
793 | RTCState *s = container_of(notifier, RTCState, clock_reset_notifier); | |
794 | int64_t now = *(int64_t *)data; | |
795 | ||
0e41271e | 796 | rtc_set_date_from_host(ISA_DEVICE(s)); |
c4c18e24 | 797 | periodic_timer_update(s, now); |
56038ef6 | 798 | check_update_timer(s); |
17604dac | 799 | #ifdef TARGET_I386 |
104059da | 800 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
17604dac JK |
801 | rtc_coalesced_timer_update(s); |
802 | } | |
803 | #endif | |
804 | } | |
805 | ||
da98c8eb GH |
806 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
807 | BIOS will read it and start S3 resume at POST Entry */ | |
808 | static void rtc_notify_suspend(Notifier *notifier, void *data) | |
809 | { | |
810 | RTCState *s = container_of(notifier, RTCState, suspend_notifier); | |
0e41271e | 811 | rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE); |
da98c8eb GH |
812 | } |
813 | ||
eeb7c03c GN |
814 | static void rtc_reset(void *opaque) |
815 | { | |
816 | RTCState *s = opaque; | |
817 | ||
72716184 AL |
818 | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
819 | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); | |
56038ef6 | 820 | check_update_timer(s); |
eeb7c03c | 821 | |
72716184 | 822 | qemu_irq_lower(s->irq); |
eeb7c03c GN |
823 | |
824 | #ifdef TARGET_I386 | |
104059da | 825 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
433acf0d | 826 | s->irq_coalesced = 0; |
172dbc52 | 827 | s->irq_reinject_on_ack_count = 0; |
433acf0d | 828 | } |
eeb7c03c GN |
829 | #endif |
830 | } | |
831 | ||
b2c5009b | 832 | static const MemoryRegionOps cmos_ops = { |
0da8c842 AG |
833 | .read = cmos_ioport_read, |
834 | .write = cmos_ioport_write, | |
835 | .impl = { | |
836 | .min_access_size = 1, | |
837 | .max_access_size = 1, | |
838 | }, | |
839 | .endianness = DEVICE_LITTLE_ENDIAN, | |
b2c5009b RH |
840 | }; |
841 | ||
8e099d14 | 842 | static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp) |
18297050 | 843 | { |
0e41271e | 844 | RTCState *s = MC146818_RTC(obj); |
18297050 | 845 | |
56038ef6 | 846 | rtc_update_time(s); |
8e099d14 | 847 | rtc_get_time(s, current_tm); |
18297050 AL |
848 | } |
849 | ||
db895a1e | 850 | static void rtc_realizefn(DeviceState *dev, Error **errp) |
dff38e7b | 851 | { |
db895a1e | 852 | ISADevice *isadev = ISA_DEVICE(dev); |
0e41271e | 853 | RTCState *s = MC146818_RTC(dev); |
32e0c826 | 854 | int base = 0x70; |
80cabfad | 855 | |
80cabfad FB |
856 | s->cmos_data[RTC_REG_A] = 0x26; |
857 | s->cmos_data[RTC_REG_B] = 0x02; | |
858 | s->cmos_data[RTC_REG_C] = 0x00; | |
859 | s->cmos_data[RTC_REG_D] = 0x80; | |
860 | ||
b8994faf PB |
861 | /* This is for historical reasons. The default base year qdev property |
862 | * was set to 2000 for most machine types before the century byte was | |
863 | * implemented. | |
864 | * | |
865 | * This if statement means that the century byte will be always 0 | |
866 | * (at least until 2079...) for base_year = 1980, but will be set | |
867 | * correctly for base_year = 2000. | |
868 | */ | |
869 | if (s->base_year == 2000) { | |
870 | s->base_year = 0; | |
871 | } | |
872 | ||
db895a1e | 873 | rtc_set_date_from_host(isadev); |
ea55ffb3 | 874 | |
93b66569 | 875 | #ifdef TARGET_I386 |
433acf0d | 876 | switch (s->lost_tick_policy) { |
104059da | 877 | case LOST_TICK_POLICY_SLEW: |
6875204c | 878 | s->coalesced_timer = |
884f17c2 | 879 | timer_new_ns(rtc_clock, rtc_coalesced_timer, s); |
433acf0d | 880 | break; |
104059da | 881 | case LOST_TICK_POLICY_DISCARD: |
433acf0d JK |
882 | break; |
883 | default: | |
db895a1e AF |
884 | error_setg(errp, "Invalid lost tick policy."); |
885 | return; | |
433acf0d | 886 | } |
93b66569 | 887 | #endif |
433acf0d | 888 | |
884f17c2 AB |
889 | s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s); |
890 | s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s); | |
56038ef6 | 891 | check_update_timer(s); |
dff38e7b | 892 | |
17604dac | 893 | s->clock_reset_notifier.notify = rtc_notify_clock_reset; |
13c0cbae | 894 | qemu_clock_register_reset_notifier(rtc_clock, |
884f17c2 | 895 | &s->clock_reset_notifier); |
17604dac | 896 | |
da98c8eb GH |
897 | s->suspend_notifier.notify = rtc_notify_suspend; |
898 | qemu_register_suspend_notifier(&s->suspend_notifier); | |
899 | ||
853dca12 | 900 | memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2); |
db895a1e | 901 | isa_register_ioport(isadev, &s->io, base); |
dff38e7b | 902 | |
db895a1e | 903 | qdev_set_legacy_instance_id(dev, base, 3); |
a08d4367 | 904 | qemu_register_reset(rtc_reset, s); |
18297050 | 905 | |
8e099d14 | 906 | object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL); |
654a36d8 MT |
907 | |
908 | object_property_add_alias(qdev_get_machine(), "rtc-time", | |
909 | OBJECT(s), "date", NULL); | |
32e0c826 GH |
910 | } |
911 | ||
48a18b3c | 912 | ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq) |
32e0c826 | 913 | { |
0e41271e AF |
914 | DeviceState *dev; |
915 | ISADevice *isadev; | |
7d932dfd | 916 | RTCState *s; |
eeb7c03c | 917 | |
0e41271e AF |
918 | isadev = isa_create(bus, TYPE_MC146818_RTC); |
919 | dev = DEVICE(isadev); | |
920 | s = MC146818_RTC(isadev); | |
921 | qdev_prop_set_int32(dev, "base_year", base_year); | |
922 | qdev_init_nofail(dev); | |
7d932dfd JK |
923 | if (intercept_irq) { |
924 | s->irq = intercept_irq; | |
925 | } else { | |
0e41271e | 926 | isa_init_irq(isadev, &s->irq, RTC_ISA_IRQ); |
7d932dfd | 927 | } |
f2ae8abf MT |
928 | QLIST_INSERT_HEAD(&rtc_devices, s, link); |
929 | ||
0e41271e | 930 | return isadev; |
80cabfad FB |
931 | } |
932 | ||
39bffca2 AL |
933 | static Property mc146818rtc_properties[] = { |
934 | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), | |
935 | DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState, | |
104059da | 936 | lost_tick_policy, LOST_TICK_POLICY_DISCARD), |
39bffca2 AL |
937 | DEFINE_PROP_END_OF_LIST(), |
938 | }; | |
939 | ||
8f04ee08 AL |
940 | static void rtc_class_initfn(ObjectClass *klass, void *data) |
941 | { | |
39bffca2 | 942 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e AF |
943 | |
944 | dc->realize = rtc_realizefn; | |
39bffca2 AL |
945 | dc->vmsd = &vmstate_rtc; |
946 | dc->props = mc146818rtc_properties; | |
f3b17640 MA |
947 | /* Reason: needs to be wired up by rtc_init() */ |
948 | dc->cannot_instantiate_with_device_add_yet = true; | |
8f04ee08 AL |
949 | } |
950 | ||
654a36d8 MT |
951 | static void rtc_finalize(Object *obj) |
952 | { | |
953 | object_property_del(qdev_get_machine(), "rtc", NULL); | |
954 | } | |
955 | ||
8c43a6f0 | 956 | static const TypeInfo mc146818rtc_info = { |
0e41271e | 957 | .name = TYPE_MC146818_RTC, |
39bffca2 AL |
958 | .parent = TYPE_ISA_DEVICE, |
959 | .instance_size = sizeof(RTCState), | |
960 | .class_init = rtc_class_initfn, | |
654a36d8 | 961 | .instance_finalize = rtc_finalize, |
32e0c826 GH |
962 | }; |
963 | ||
83f7d43a | 964 | static void mc146818rtc_register_types(void) |
100d9891 | 965 | { |
39bffca2 | 966 | type_register_static(&mc146818rtc_info); |
100d9891 | 967 | } |
83f7d43a AF |
968 | |
969 | type_init(mc146818rtc_register_types) |