hw/timer/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "config-target.h"
  26 #include "hw/hw.h"
  27 #include "qemu/timer.h"
  28 #include "sysemu/sysemu.h"
  29 #include "hw/timer/mc146818rtc.h"
  30 #include "qapi/visitor.h"
  31 #include "qapi-event.h"
  32 #include "qmp-commands.h"
  33
  34 #ifdef TARGET_I386
  35 #include "hw/i386/apic.h"
  36 #endif
  37
  38 //#define DEBUG_CMOS
  39 //#define DEBUG_COALESCED
  40
  41 #ifdef DEBUG_CMOS
  42 # define CMOS_DPRINTF(format, ...)      printf(format, ## __VA_ARGS__)
  43 #else
  44 # define CMOS_DPRINTF(format, ...)      do { } while (0)
  45 #endif
  46
  47 #ifdef DEBUG_COALESCED
  48 # define DPRINTF_C(format, ...)      printf(format, ## __VA_ARGS__)
  49 #else
  50 # define DPRINTF_C(format, ...)      do { } while (0)
  51 #endif
  52
  53 #define SEC_PER_MIN     60
  54 #define MIN_PER_HOUR    60
  55 #define SEC_PER_HOUR    3600
  56 #define HOUR_PER_DAY    24
  57 #define SEC_PER_DAY     86400
  58
  59 #define RTC_REINJECT_ON_ACK_COUNT 20
  60 #define RTC_CLOCK_RATE            32768
  61 #define UIP_HOLD_LENGTH           (8 * NANOSECONDS_PER_SECOND / 32768)
  62
  63 #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC)
  64
  65 typedef struct RTCState {
  66     ISADevice parent_obj;
  67
  68     MemoryRegion io;
  69     uint8_t cmos_data[128];
  70     uint8_t cmos_index;
  71     int32_t base_year;
  72     uint64_t base_rtc;
  73     uint64_t last_update;
  74     int64_t offset;
  75     qemu_irq irq;
  76     int it_shift;
  77     /* periodic timer */
  78     QEMUTimer *periodic_timer;
  79     int64_t next_periodic_time;
  80     /* update-ended timer */
  81     QEMUTimer *update_timer;
  82     uint64_t next_alarm_time;
  83     uint16_t irq_reinject_on_ack_count;
  84     uint32_t irq_coalesced;
  85     uint32_t period;
  86     QEMUTimer *coalesced_timer;
  87     Notifier clock_reset_notifier;
  88     LostTickPolicy lost_tick_policy;
  89     Notifier suspend_notifier;
  90     QLIST_ENTRY(RTCState) link;
  91 } RTCState;
  92
  93 static void rtc_set_time(RTCState *s);
  94 static void rtc_update_time(RTCState *s);
  95 static void rtc_set_cmos(RTCState *s, const struct tm *tm);
  96 static inline int rtc_from_bcd(RTCState *s, int a);
  97 static uint64_t get_next_alarm(RTCState *s);
  98
  99 static inline bool rtc_running(RTCState *s)
 100 {
 101     return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 102             (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20);
 103 }
 104
 105 static uint64_t get_guest_rtc_ns(RTCState *s)
 106 {
 107     uint64_t guest_rtc;
 108     uint64_t guest_clock = qemu_clock_get_ns(rtc_clock);
 109
 110     guest_rtc = s->base_rtc * NANOSECONDS_PER_SECOND +
 111         guest_clock - s->last_update + s->offset;
 112     return guest_rtc;
 113 }
 114
 115 #ifdef TARGET_I386
 116 static void rtc_coalesced_timer_update(RTCState *s)
 117 {
 118     if (s->irq_coalesced == 0) {
 119         timer_del(s->coalesced_timer);
 120     } else {
 121         /* divide each RTC interval to 2 - 8 smaller intervals */
 122         int c = MIN(s->irq_coalesced, 7) + 1;
 123         int64_t next_clock = qemu_clock_get_ns(rtc_clock) +
 124             muldiv64(s->period / c, NANOSECONDS_PER_SECOND, RTC_CLOCK_RATE);
 125         timer_mod(s->coalesced_timer, next_clock);
 126     }
 127 }
 128
 129 static void rtc_coalesced_timer(void *opaque)
 130 {
 131     RTCState *s = opaque;
 132
 133     if (s->irq_coalesced != 0) {
 134         apic_reset_irq_delivered();
 135         s->cmos_data[RTC_REG_C] |= 0xc0;
 136         DPRINTF_C("cmos: injecting from timer\n");
 137         qemu_irq_raise(s->irq);
 138         if (apic_get_irq_delivered()) {
 139             s->irq_coalesced--;
 140             DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 141                       s->irq_coalesced);
 142         }
 143     }
 144
 145     rtc_coalesced_timer_update(s);
 146 }
 147 #endif
 148
 149 /* handle periodic timer */
 150 static void periodic_timer_update(RTCState *s, int64_t current_time)
 151 {
 152     int period_code, period;
 153     int64_t cur_clock, next_irq_clock;
 154
 155     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 156     if (period_code != 0
 157         && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
 158         if (period_code <= 2)
 159             period_code += 7;
 160         /* period in 32 Khz cycles */
 161         period = 1 << (period_code - 1);
 162 #ifdef TARGET_I386
 163         if (period != s->period) {
 164             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 165             DPRINTF_C("cmos: coalesced irqs scaled to %d\n", s->irq_coalesced);
 166         }
 167         s->period = period;
 168 #endif
 169         /* compute 32 khz clock */
 170         cur_clock =
 171             muldiv64(current_time, RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND);
 172
 173         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 174         s->next_periodic_time = muldiv64(next_irq_clock, NANOSECONDS_PER_SECOND,
 175                                          RTC_CLOCK_RATE) + 1;
 176         timer_mod(s->periodic_timer, s->next_periodic_time);
 177     } else {
 178 #ifdef TARGET_I386
 179         s->irq_coalesced = 0;
 180 #endif
 181         timer_del(s->periodic_timer);
 182     }
 183 }
 184
 185 static void rtc_periodic_timer(void *opaque)
 186 {
 187     RTCState *s = opaque;
 188
 189     periodic_timer_update(s, s->next_periodic_time);
 190     s->cmos_data[RTC_REG_C] |= REG_C_PF;
 191     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 192         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 193 #ifdef TARGET_I386
 194         if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 195             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 196                 s->irq_reinject_on_ack_count = 0;
 197             apic_reset_irq_delivered();
 198             qemu_irq_raise(s->irq);
 199             if (!apic_get_irq_delivered()) {
 200                 s->irq_coalesced++;
 201                 rtc_coalesced_timer_update(s);
 202                 DPRINTF_C("cmos: coalesced irqs increased to %d\n",
 203                           s->irq_coalesced);
 204             }
 205         } else
 206 #endif
 207         qemu_irq_raise(s->irq);
 208     }
 209 }
 210
 211 /* handle update-ended timer */
 212 static void check_update_timer(RTCState *s)
 213 {
 214     uint64_t next_update_time;
 215     uint64_t guest_nsec;
 216     int next_alarm_sec;
 217
 218     /* From the data sheet: "Holding the dividers in reset prevents
 219      * interrupts from operating, while setting the SET bit allows"
 220      * them to occur.  However, it will prevent an alarm interrupt
 221      * from occurring, because the time of day is not updated.
 222      */
 223     if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) {
 224         timer_del(s->update_timer);
 225         return;
 226     }
 227     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 228         (s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 229         timer_del(s->update_timer);
 230         return;
 231     }
 232     if ((s->cmos_data[RTC_REG_C] & REG_C_UF) &&
 233         (s->cmos_data[RTC_REG_C] & REG_C_AF)) {
 234         timer_del(s->update_timer);
 235         return;
 236     }
 237
 238     guest_nsec = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
 239     /* if UF is clear, reprogram to next second */
 240     next_update_time = qemu_clock_get_ns(rtc_clock)
 241         + NANOSECONDS_PER_SECOND - guest_nsec;
 242
 243     /* Compute time of next alarm.  One second is already accounted
 244      * for in next_update_time.
 245      */
 246     next_alarm_sec = get_next_alarm(s);
 247     s->next_alarm_time = next_update_time +
 248                          (next_alarm_sec - 1) * NANOSECONDS_PER_SECOND;
 249
 250     if (s->cmos_data[RTC_REG_C] & REG_C_UF) {
 251         /* UF is set, but AF is clear.  Program the timer to target
 252          * the alarm time.  */
 253         next_update_time = s->next_alarm_time;
 254     }
 255     if (next_update_time != timer_expire_time_ns(s->update_timer)) {
 256         timer_mod(s->update_timer, next_update_time);
 257     }
 258 }
 259
 260 static inline uint8_t convert_hour(RTCState *s, uint8_t hour)
 261 {
 262     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 263         hour %= 12;
 264         if (s->cmos_data[RTC_HOURS] & 0x80) {
 265             hour += 12;
 266         }
 267     }
 268     return hour;
 269 }
 270
 271 static uint64_t get_next_alarm(RTCState *s)
 272 {
 273     int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec;
 274     int32_t hour, min, sec;
 275
 276     rtc_update_time(s);
 277
 278     alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]);
 279     alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]);
 280     alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]);
 281     alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour);
 282
 283     cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 284     cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 285     cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]);
 286     cur_hour = convert_hour(s, cur_hour);
 287
 288     if (alarm_hour == -1) {
 289         alarm_hour = cur_hour;
 290         if (alarm_min == -1) {
 291             alarm_min = cur_min;
 292             if (alarm_sec == -1) {
 293                 alarm_sec = cur_sec + 1;
 294             } else if (cur_sec > alarm_sec) {
 295                 alarm_min++;
 296             }
 297         } else if (cur_min == alarm_min) {
 298             if (alarm_sec == -1) {
 299                 alarm_sec = cur_sec + 1;
 300             } else {
 301                 if (cur_sec > alarm_sec) {
 302                     alarm_hour++;
 303                 }
 304             }
 305             if (alarm_sec == SEC_PER_MIN) {
 306                 /* wrap to next hour, minutes is not in don't care mode */
 307                 alarm_sec = 0;
 308                 alarm_hour++;
 309             }
 310         } else if (cur_min > alarm_min) {
 311             alarm_hour++;
 312         }
 313     } else if (cur_hour == alarm_hour) {
 314         if (alarm_min == -1) {
 315             alarm_min = cur_min;
 316             if (alarm_sec == -1) {
 317                 alarm_sec = cur_sec + 1;
 318             } else if (cur_sec > alarm_sec) {
 319                 alarm_min++;
 320             }
 321
 322             if (alarm_sec == SEC_PER_MIN) {
 323                 alarm_sec = 0;
 324                 alarm_min++;
 325             }
 326             /* wrap to next day, hour is not in don't care mode */
 327             alarm_min %= MIN_PER_HOUR;
 328         } else if (cur_min == alarm_min) {
 329             if (alarm_sec == -1) {
 330                 alarm_sec = cur_sec + 1;
 331             }
 332             /* wrap to next day, hours+minutes not in don't care mode */
 333             alarm_sec %= SEC_PER_MIN;
 334         }
 335     }
 336
 337     /* values that are still don't care fire at the next min/sec */
 338     if (alarm_min == -1) {
 339         alarm_min = 0;
 340     }
 341     if (alarm_sec == -1) {
 342         alarm_sec = 0;
 343     }
 344
 345     /* keep values in range */
 346     if (alarm_sec == SEC_PER_MIN) {
 347         alarm_sec = 0;
 348         alarm_min++;
 349     }
 350     if (alarm_min == MIN_PER_HOUR) {
 351         alarm_min = 0;
 352         alarm_hour++;
 353     }
 354     alarm_hour %= HOUR_PER_DAY;
 355
 356     hour = alarm_hour - cur_hour;
 357     min = hour * MIN_PER_HOUR + alarm_min - cur_min;
 358     sec = min * SEC_PER_MIN + alarm_sec - cur_sec;
 359     return sec <= 0 ? sec + SEC_PER_DAY : sec;
 360 }
 361
 362 static void rtc_update_timer(void *opaque)
 363 {
 364     RTCState *s = opaque;
 365     int32_t irqs = REG_C_UF;
 366     int32_t new_irqs;
 367
 368     assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60);
 369
 370     /* UIP might have been latched, update time and clear it.  */
 371     rtc_update_time(s);
 372     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 373
 374     if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) {
 375         irqs |= REG_C_AF;
 376         if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 377             qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC);
 378         }
 379     }
 380
 381     new_irqs = irqs & ~s->cmos_data[RTC_REG_C];
 382     s->cmos_data[RTC_REG_C] |= irqs;
 383     if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) {
 384         s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 385         qemu_irq_raise(s->irq);
 386     }
 387     check_update_timer(s);
 388 }
 389
 390 static void cmos_ioport_write(void *opaque, hwaddr addr,
 391                               uint64_t data, unsigned size)
 392 {
 393     RTCState *s = opaque;
 394
 395     if ((addr & 1) == 0) {
 396         s->cmos_index = data & 0x7f;
 397     } else {
 398         CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n",
 399                      s->cmos_index, data);
 400         switch(s->cmos_index) {
 401         case RTC_SECONDS_ALARM:
 402         case RTC_MINUTES_ALARM:
 403         case RTC_HOURS_ALARM:
 404             s->cmos_data[s->cmos_index] = data;
 405             check_update_timer(s);
 406             break;
 407         case RTC_IBM_PS2_CENTURY_BYTE:
 408             s->cmos_index = RTC_CENTURY;
 409             /* fall through */
 410         case RTC_CENTURY:
 411         case RTC_SECONDS:
 412         case RTC_MINUTES:
 413         case RTC_HOURS:
 414         case RTC_DAY_OF_WEEK:
 415         case RTC_DAY_OF_MONTH:
 416         case RTC_MONTH:
 417         case RTC_YEAR:
 418             s->cmos_data[s->cmos_index] = data;
 419             /* if in set mode, do not update the time */
 420             if (rtc_running(s)) {
 421                 rtc_set_time(s);
 422                 check_update_timer(s);
 423             }
 424             break;
 425         case RTC_REG_A:
 426             if ((data & 0x60) == 0x60) {
 427                 if (rtc_running(s)) {
 428                     rtc_update_time(s);
 429                 }
 430                 /* What happens to UIP when divider reset is enabled is
 431                  * unclear from the datasheet.  Shouldn't matter much
 432                  * though.
 433                  */
 434                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 435             } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) &&
 436                     (data & 0x70)  <= 0x20) {
 437                 /* when the divider reset is removed, the first update cycle
 438                  * begins one-half second later*/
 439                 if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 440                     s->offset = 500000000;
 441                     rtc_set_time(s);
 442                 }
 443                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 444             }
 445             /* UIP bit is read only */
 446             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 447                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 448             periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 449             check_update_timer(s);
 450             break;
 451         case RTC_REG_B:
 452             if (data & REG_B_SET) {
 453                 /* update cmos to when the rtc was stopping */
 454                 if (rtc_running(s)) {
 455                     rtc_update_time(s);
 456                 }
 457                 /* set mode: reset UIP mode */
 458                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 459                 data &= ~REG_B_UIE;
 460             } else {
 461                 /* if disabling set mode, update the time */
 462                 if ((s->cmos_data[RTC_REG_B] & REG_B_SET) &&
 463                     (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) {
 464                     s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND;
 465                     rtc_set_time(s);
 466                 }
 467             }
 468             /* if an interrupt flag is already set when the interrupt
 469              * becomes enabled, raise an interrupt immediately.  */
 470             if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) {
 471                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 472                 qemu_irq_raise(s->irq);
 473             } else {
 474                 s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF;
 475                 qemu_irq_lower(s->irq);
 476             }
 477             s->cmos_data[RTC_REG_B] = data;
 478             periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 479             check_update_timer(s);
 480             break;
 481         case RTC_REG_C:
 482         case RTC_REG_D:
 483             /* cannot write to them */
 484             break;
 485         default:
 486             s->cmos_data[s->cmos_index] = data;
 487             break;
 488         }
 489     }
 490 }
 491
 492 static inline int rtc_to_bcd(RTCState *s, int a)
 493 {
 494     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 495         return a;
 496     } else {
 497         return ((a / 10) << 4) | (a % 10);
 498     }
 499 }
 500
 501 static inline int rtc_from_bcd(RTCState *s, int a)
 502 {
 503     if ((a & 0xc0) == 0xc0) {
 504         return -1;
 505     }
 506     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 507         return a;
 508     } else {
 509         return ((a >> 4) * 10) + (a & 0x0f);
 510     }
 511 }
 512
 513 static void rtc_get_time(RTCState *s, struct tm *tm)
 514 {
 515     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 516     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 517     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 518     if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) {
 519         tm->tm_hour %= 12;
 520         if (s->cmos_data[RTC_HOURS] & 0x80) {
 521             tm->tm_hour += 12;
 522         }
 523     }
 524     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 525     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 526     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 527     tm->tm_year =
 528         rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year +
 529         rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900;
 530 }
 531
 532 static QLIST_HEAD(, RTCState) rtc_devices =
 533     QLIST_HEAD_INITIALIZER(rtc_devices);
 534
 535 #ifdef TARGET_I386
 536 void qmp_rtc_reset_reinjection(Error **errp)
 537 {
 538     RTCState *s;
 539
 540     QLIST_FOREACH(s, &rtc_devices, link) {
 541         s->irq_coalesced = 0;
 542     }
 543 }
 544 #endif
 545
 546 static void rtc_set_time(RTCState *s)
 547 {
 548     struct tm tm;
 549
 550     rtc_get_time(s, &tm);
 551     s->base_rtc = mktimegm(&tm);
 552     s->last_update = qemu_clock_get_ns(rtc_clock);
 553
 554     qapi_event_send_rtc_change(qemu_timedate_diff(&tm), &error_abort);
 555 }
 556
 557 static void rtc_set_cmos(RTCState *s, const struct tm *tm)
 558 {
 559     int year;
 560
 561     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 562     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 563     if (s->cmos_data[RTC_REG_B] & REG_B_24H) {
 564         /* 24 hour format */
 565         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 566     } else {
 567         /* 12 hour format */
 568         int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12;
 569         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h);
 570         if (tm->tm_hour >= 12)
 571             s->cmos_data[RTC_HOURS] |= 0x80;
 572     }
 573     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 574     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 575     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 576     year = tm->tm_year + 1900 - s->base_year;
 577     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100);
 578     s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100);
 579 }
 580
 581 static void rtc_update_time(RTCState *s)
 582 {
 583     struct tm ret;
 584     time_t guest_sec;
 585     int64_t guest_nsec;
 586
 587     guest_nsec = get_guest_rtc_ns(s);
 588     guest_sec = guest_nsec / NANOSECONDS_PER_SECOND;
 589     gmtime_r(&guest_sec, &ret);
 590
 591     /* Is SET flag of Register B disabled? */
 592     if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) {
 593         rtc_set_cmos(s, &ret);
 594     }
 595 }
 596
 597 static int update_in_progress(RTCState *s)
 598 {
 599     int64_t guest_nsec;
 600
 601     if (!rtc_running(s)) {
 602         return 0;
 603     }
 604     if (timer_pending(s->update_timer)) {
 605         int64_t next_update_time = timer_expire_time_ns(s->update_timer);
 606         /* Latch UIP until the timer expires.  */
 607         if (qemu_clock_get_ns(rtc_clock) >=
 608             (next_update_time - UIP_HOLD_LENGTH)) {
 609             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 610             return 1;
 611         }
 612     }
 613
 614     guest_nsec = get_guest_rtc_ns(s);
 615     /* UIP bit will be set at last 244us of every second. */
 616     if ((guest_nsec % NANOSECONDS_PER_SECOND) >=
 617         (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)) {
 618         return 1;
 619     }
 620     return 0;
 621 }
 622
 623 static uint64_t cmos_ioport_read(void *opaque, hwaddr addr,
 624                                  unsigned size)
 625 {
 626     RTCState *s = opaque;
 627     int ret;
 628     if ((addr & 1) == 0) {
 629         return 0xff;
 630     } else {
 631         switch(s->cmos_index) {
 632         case RTC_IBM_PS2_CENTURY_BYTE:
 633             s->cmos_index = RTC_CENTURY;
 634             /* fall through */
 635         case RTC_CENTURY:
 636         case RTC_SECONDS:
 637         case RTC_MINUTES:
 638         case RTC_HOURS:
 639         case RTC_DAY_OF_WEEK:
 640         case RTC_DAY_OF_MONTH:
 641         case RTC_MONTH:
 642         case RTC_YEAR:
 643             /* if not in set mode, calibrate cmos before
 644              * reading*/
 645             if (rtc_running(s)) {
 646                 rtc_update_time(s);
 647             }
 648             ret = s->cmos_data[s->cmos_index];
 649             break;
 650         case RTC_REG_A:
 651             if (update_in_progress(s)) {
 652                 s->cmos_data[s->cmos_index] |= REG_A_UIP;
 653             } else {
 654                 s->cmos_data[s->cmos_index] &= ~REG_A_UIP;
 655             }
 656             ret = s->cmos_data[s->cmos_index];
 657             break;
 658         case RTC_REG_C:
 659             ret = s->cmos_data[s->cmos_index];
 660             qemu_irq_lower(s->irq);
 661             s->cmos_data[RTC_REG_C] = 0x00;
 662             if (ret & (REG_C_UF | REG_C_AF)) {
 663                 check_update_timer(s);
 664             }
 665 #ifdef TARGET_I386
 666             if(s->irq_coalesced &&
 667                     (s->cmos_data[RTC_REG_B] & REG_B_PIE) &&
 668                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 669                 s->irq_reinject_on_ack_count++;
 670                 s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF;
 671                 apic_reset_irq_delivered();
 672                 DPRINTF_C("cmos: injecting on ack\n");
 673                 qemu_irq_raise(s->irq);
 674                 if (apic_get_irq_delivered()) {
 675                     s->irq_coalesced--;
 676                     DPRINTF_C("cmos: coalesced irqs decreased to %d\n",
 677                               s->irq_coalesced);
 678                 }
 679             }
 680 #endif
 681             break;
 682         default:
 683             ret = s->cmos_data[s->cmos_index];
 684             break;
 685         }
 686         CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n",
 687                      s->cmos_index, ret);
 688         return ret;
 689     }
 690 }
 691
 692 void rtc_set_memory(ISADevice *dev, int addr, int val)
 693 {
 694     RTCState *s = MC146818_RTC(dev);
 695     if (addr >= 0 && addr <= 127)
 696         s->cmos_data[addr] = val;
 697 }
 698
 699 int rtc_get_memory(ISADevice *dev, int addr)
 700 {
 701     RTCState *s = MC146818_RTC(dev);
 702     assert(addr >= 0 && addr <= 127);
 703     return s->cmos_data[addr];
 704 }
 705
 706 static void rtc_set_date_from_host(ISADevice *dev)
 707 {
 708     RTCState *s = MC146818_RTC(dev);
 709     struct tm tm;
 710
 711     qemu_get_timedate(&tm, 0);
 712
 713     s->base_rtc = mktimegm(&tm);
 714     s->last_update = qemu_clock_get_ns(rtc_clock);
 715     s->offset = 0;
 716
 717     /* set the CMOS date */
 718     rtc_set_cmos(s, &tm);
 719 }
 720
 721 static int rtc_post_load(void *opaque, int version_id)
 722 {
 723     RTCState *s = opaque;
 724
 725     if (version_id <= 2) {
 726         rtc_set_time(s);
 727         s->offset = 0;
 728         check_update_timer(s);
 729     }
 730
 731     uint64_t now = qemu_clock_get_ns(rtc_clock);
 732     if (now < s->next_periodic_time ||
 733         now > (s->next_periodic_time + get_max_clock_jump())) {
 734         periodic_timer_update(s, qemu_clock_get_ns(rtc_clock));
 735     }
 736
 737 #ifdef TARGET_I386
 738     if (version_id >= 2) {
 739         if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 740             rtc_coalesced_timer_update(s);
 741         }
 742     }
 743 #endif
 744     return 0;
 745 }
 746
 747 static bool rtc_irq_reinject_on_ack_count_needed(void *opaque)
 748 {
 749     RTCState *s = (RTCState *)opaque;
 750     return s->irq_reinject_on_ack_count != 0;
 751 }
 752
 753 static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = {
 754     .name = "mc146818rtc/irq_reinject_on_ack_count",
 755     .version_id = 1,
 756     .minimum_version_id = 1,
 757     .needed = rtc_irq_reinject_on_ack_count_needed,
 758     .fields = (VMStateField[]) {
 759         VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState),
 760         VMSTATE_END_OF_LIST()
 761     }
 762 };
 763
 764 static const VMStateDescription vmstate_rtc = {
 765     .name = "mc146818rtc",
 766     .version_id = 3,
 767     .minimum_version_id = 1,
 768     .post_load = rtc_post_load,
 769     .fields = (VMStateField[]) {
 770         VMSTATE_BUFFER(cmos_data, RTCState),
 771         VMSTATE_UINT8(cmos_index, RTCState),
 772         VMSTATE_UNUSED(7*4),
 773         VMSTATE_TIMER_PTR(periodic_timer, RTCState),
 774         VMSTATE_INT64(next_periodic_time, RTCState),
 775         VMSTATE_UNUSED(3*8),
 776         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 777         VMSTATE_UINT32_V(period, RTCState, 2),
 778         VMSTATE_UINT64_V(base_rtc, RTCState, 3),
 779         VMSTATE_UINT64_V(last_update, RTCState, 3),
 780         VMSTATE_INT64_V(offset, RTCState, 3),
 781         VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3),
 782         VMSTATE_UINT64_V(next_alarm_time, RTCState, 3),
 783         VMSTATE_END_OF_LIST()
 784     },
 785     .subsections = (const VMStateDescription*[]) {
 786         &vmstate_rtc_irq_reinject_on_ack_count,
 787         NULL
 788     }
 789 };
 790
 791 static void rtc_notify_clock_reset(Notifier *notifier, void *data)
 792 {
 793     RTCState *s = container_of(notifier, RTCState, clock_reset_notifier);
 794     int64_t now = *(int64_t *)data;
 795
 796     rtc_set_date_from_host(ISA_DEVICE(s));
 797     periodic_timer_update(s, now);
 798     check_update_timer(s);
 799 #ifdef TARGET_I386
 800     if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 801         rtc_coalesced_timer_update(s);
 802     }
 803 #endif
 804 }
 805
 806 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
 807    BIOS will read it and start S3 resume at POST Entry */
 808 static void rtc_notify_suspend(Notifier *notifier, void *data)
 809 {
 810     RTCState *s = container_of(notifier, RTCState, suspend_notifier);
 811     rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
 812 }
 813
 814 static void rtc_reset(void *opaque)
 815 {
 816     RTCState *s = opaque;
 817
 818     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 819     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 820     check_update_timer(s);
 821
 822     qemu_irq_lower(s->irq);
 823
 824 #ifdef TARGET_I386
 825     if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
 826         s->irq_coalesced = 0;
 827         s->irq_reinject_on_ack_count = 0;
 828     }
 829 #endif
 830 }
 831
 832 static const MemoryRegionOps cmos_ops = {
 833     .read = cmos_ioport_read,
 834     .write = cmos_ioport_write,
 835     .impl = {
 836         .min_access_size = 1,
 837         .max_access_size = 1,
 838     },
 839     .endianness = DEVICE_LITTLE_ENDIAN,
 840 };
 841
 842 static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp)
 843 {
 844     RTCState *s = MC146818_RTC(obj);
 845
 846     rtc_update_time(s);
 847     rtc_get_time(s, current_tm);
 848 }
 849
 850 static void rtc_realizefn(DeviceState *dev, Error **errp)
 851 {
 852     ISADevice *isadev = ISA_DEVICE(dev);
 853     RTCState *s = MC146818_RTC(dev);
 854     int base = 0x70;
 855
 856     s->cmos_data[RTC_REG_A] = 0x26;
 857     s->cmos_data[RTC_REG_B] = 0x02;
 858     s->cmos_data[RTC_REG_C] = 0x00;
 859     s->cmos_data[RTC_REG_D] = 0x80;
 860
 861     /* This is for historical reasons.  The default base year qdev property
 862      * was set to 2000 for most machine types before the century byte was
 863      * implemented.
 864      *
 865      * This if statement means that the century byte will be always 0
 866      * (at least until 2079...) for base_year = 1980, but will be set
 867      * correctly for base_year = 2000.
 868      */
 869     if (s->base_year == 2000) {
 870         s->base_year = 0;
 871     }
 872
 873     rtc_set_date_from_host(isadev);
 874
 875 #ifdef TARGET_I386
 876     switch (s->lost_tick_policy) {
 877     case LOST_TICK_POLICY_SLEW:
 878         s->coalesced_timer =
 879             timer_new_ns(rtc_clock, rtc_coalesced_timer, s);
 880         break;
 881     case LOST_TICK_POLICY_DISCARD:
 882         break;
 883     default:
 884         error_setg(errp, "Invalid lost tick policy.");
 885         return;
 886     }
 887 #endif
 888
 889     s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s);
 890     s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s);
 891     check_update_timer(s);
 892
 893     s->clock_reset_notifier.notify = rtc_notify_clock_reset;
 894     qemu_clock_register_reset_notifier(rtc_clock,
 895                                        &s->clock_reset_notifier);
 896
 897     s->suspend_notifier.notify = rtc_notify_suspend;
 898     qemu_register_suspend_notifier(&s->suspend_notifier);
 899
 900     memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2);
 901     isa_register_ioport(isadev, &s->io, base);
 902
 903     qdev_set_legacy_instance_id(dev, base, 3);
 904     qemu_register_reset(rtc_reset, s);
 905
 906     object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL);
 907
 908     object_property_add_alias(qdev_get_machine(), "rtc-time",
 909                               OBJECT(s), "date", NULL);
 910 }
 911
 912 ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
 913 {
 914     DeviceState *dev;
 915     ISADevice *isadev;
 916     RTCState *s;
 917
 918     isadev = isa_create(bus, TYPE_MC146818_RTC);
 919     dev = DEVICE(isadev);
 920     s = MC146818_RTC(isadev);
 921     qdev_prop_set_int32(dev, "base_year", base_year);
 922     qdev_init_nofail(dev);
 923     if (intercept_irq) {
 924         s->irq = intercept_irq;
 925     } else {
 926         isa_init_irq(isadev, &s->irq, RTC_ISA_IRQ);
 927     }
 928     QLIST_INSERT_HEAD(&rtc_devices, s, link);
 929
 930     return isadev;
 931 }
 932
 933 static Property mc146818rtc_properties[] = {
 934     DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 935     DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
 936                                lost_tick_policy, LOST_TICK_POLICY_DISCARD),
 937     DEFINE_PROP_END_OF_LIST(),
 938 };
 939
 940 static void rtc_class_initfn(ObjectClass *klass, void *data)
 941 {
 942     DeviceClass *dc = DEVICE_CLASS(klass);
 943
 944     dc->realize = rtc_realizefn;
 945     dc->vmsd = &vmstate_rtc;
 946     dc->props = mc146818rtc_properties;
 947     /* Reason: needs to be wired up by rtc_init() */
 948     dc->cannot_instantiate_with_device_add_yet = true;
 949 }
 950
 951 static void rtc_finalize(Object *obj)
 952 {
 953     object_property_del(qdev_get_machine(), "rtc", NULL);
 954 }
 955
 956 static const TypeInfo mc146818rtc_info = {
 957     .name          = TYPE_MC146818_RTC,
 958     .parent        = TYPE_ISA_DEVICE,
 959     .instance_size = sizeof(RTCState),
 960     .class_init    = rtc_class_initfn,
 961     .instance_finalize = rtc_finalize,
 962 };
 963
 964 static void mc146818rtc_register_types(void)
 965 {
 966     type_register_static(&mc146818rtc_info);
 967 }
 968
 969 type_init(mc146818rtc_register_types)