[qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "pci.h"

typedef target_phys_addr_t pci_addr_t;
#include "pci_host.h"

typedef PCIHostState UNINState;

static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
                                         uint32_t val)
{
    UNINState *s = opaque;
    int i;

#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif

    for (i = 11; i < 32; i++) {
        if ((val & (1 << i)) != 0)
            break;
    }
#if 0
    s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
#else
    s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
#endif
}

static uint32_t pci_unin_main_config_readl (void *opaque,
                                            target_phys_addr_t addr)
{
    UNINState *s = opaque;
    uint32_t val;
    int devfn;

    devfn = (s->config_reg >> 8) & 0xFF;
    val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif

    return val;
}

static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
    &pci_unin_main_config_writel,
    &pci_unin_main_config_writel,
    &pci_unin_main_config_writel,
};

static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
    &pci_unin_main_config_readl,
    &pci_unin_main_config_readl,
    &pci_unin_main_config_readl,
};

static CPUWriteMemoryFunc *pci_unin_main_write[] = {
    &pci_host_data_writeb,
    &pci_host_data_writew,
    &pci_host_data_writel,
};

static CPUReadMemoryFunc *pci_unin_main_read[] = {
    &pci_host_data_readb,
    &pci_host_data_readw,
    &pci_host_data_readl,
};

#if 0

static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
                                    uint32_t val)
{
    UNINState *s = opaque;

#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif
    s->config_reg = 0x80000000 | (val & ~0x00000001);
}

static uint32_t pci_unin_config_readl (void *opaque,
                                       target_phys_addr_t addr)
{
    UNINState *s = opaque;
    uint32_t val;

    val = (s->config_reg | 0x00000001) & ~0x80000000;
#ifdef TARGET_WORDS_BIGENDIAN
    val = bswap32(val);
#endif

    return val;
}

static CPUWriteMemoryFunc *pci_unin_config_write[] = {
    &pci_unin_config_writel,
    &pci_unin_config_writel,
    &pci_unin_config_writel,
};

static CPUReadMemoryFunc *pci_unin_config_read[] = {
    &pci_unin_config_readl,
    &pci_unin_config_readl,
    &pci_unin_config_readl,
};

static CPUWriteMemoryFunc *pci_unin_write[] = {
    &pci_host_pci_writeb,
    &pci_host_pci_writew,
    &pci_host_pci_writel,
};

static CPUReadMemoryFunc *pci_unin_read[] = {
    &pci_host_pci_readb,
    &pci_host_pci_readw,
    &pci_host_pci_readl,
};
#endif

/* Don't know if this matches real hardware, but it agrees with OHW.  */
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    return (irq_num + (pci_dev->devfn >> 3)) & 3;
}

static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level)
{
    qemu_set_irq(pic[irq_num + 8], level);
}

PCIBus *pci_pmac_init(qemu_irq *pic)
{
    UNINState *s;
    PCIDevice *d;
    int pci_mem_config, pci_mem_data;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    s = qemu_mallocz(sizeof(UNINState));
    s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq,
                              pic, 11 << 3, 4);

    pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
                                            pci_unin_main_config_write, s);
    pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
                                          pci_unin_main_write, s);
    cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
    cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
    d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
                            11 << 3, NULL, NULL);
    d->config[0x00] = 0x6b; // vendor_id : Apple
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x1F; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x00; // revision
    d->config[0x0A] = 0x00; // class_sub = pci host
    d->config[0x0B] = 0x06; // class_base = PCI_bridge
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x0E] = 0x00; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer

#if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
    /* pci-to-pci bridge */
    d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
                            NULL, NULL);
    d->config[0x00] = 0x11; // vendor_id : TI
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x26; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x05; // revision
    d->config[0x0A] = 0x04; // class_sub = pci2pci
    d->config[0x0B] = 0x06; // class_base = PCI_bridge
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x20; // latency_timer
    d->config[0x0E] = 0x01; // header_type

    d->config[0x18] = 0x01; // primary_bus
    d->config[0x19] = 0x02; // secondary_bus
    d->config[0x1A] = 0x02; // subordinate_bus
    d->config[0x1B] = 0x20; // secondary_latency_timer
    d->config[0x1C] = 0x11; // io_base
    d->config[0x1D] = 0x01; // io_limit
    d->config[0x20] = 0x00; // memory_base
    d->config[0x21] = 0x80;
    d->config[0x22] = 0x00; // memory_limit
    d->config[0x23] = 0x80;
    d->config[0x24] = 0x01; // prefetchable_memory_base
    d->config[0x25] = 0x80;
    d->config[0x26] = 0xF1; // prefectchable_memory_limit
    d->config[0x27] = 0x7F;
    // d->config[0x34] = 0xdc // capabilities_pointer
#endif
#if 0 // XXX: not needed for now
    /* Uninorth AGP bus */
    s = &pci_bridge[1];
    pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
                                            pci_unin_config_write, s);
    pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
                                          pci_unin_write, s);
    cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
    cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);

    d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
                            NULL, NULL);
    d->config[0x00] = 0x6b; // vendor_id : Apple
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x20; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x00; // revision
    d->config[0x0A] = 0x00; // class_sub = pci host
    d->config[0x0B] = 0x06; // class_base = PCI_bridge
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x0E] = 0x00; // header_type
    //    d->config[0x34] = 0x80; // capabilities_pointer
#endif

#if 0 // XXX: not needed for now
    /* Uninorth internal bus */
    s = &pci_bridge[2];
    pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
                                            pci_unin_config_write, s);
    pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
                                          pci_unin_write, s);
    cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
    cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);

    d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
                            3, 11 << 3, NULL, NULL);
    d->config[0x00] = 0x6b; // vendor_id : Apple
    d->config[0x01] = 0x10;
    d->config[0x02] = 0x1E; // device_id
    d->config[0x03] = 0x00;
    d->config[0x08] = 0x00; // revision
    d->config[0x0A] = 0x00; // class_sub = pci host
    d->config[0x0B] = 0x06; // class_base = PCI_bridge
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x0E] = 0x00; // header_type
    d->config[0x34] = 0x00; // capabilities_pointer
#endif
    return s->bus;
}
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "ppc_mac.h"
	26	#include "pci.h"
	27
502a5395 PB	28	typedef target_phys_addr_t pci_addr_t;
	29	#include "pci_host.h"
	30
	31	typedef PCIHostState UNINState;
	32
	33	static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
	34	uint32_t val)
	35	{
	36	UNINState *s = opaque;
	37	int i;
	38
	39	#ifdef TARGET_WORDS_BIGENDIAN
	40	val = bswap32(val);
	41	#endif
	42
	43	for (i = 11; i < 32; i++) {
	44	if ((val & (1 << i)) != 0)
	45	break;
	46	}
	47	#if 0
	48	s->config_reg = 0x80000000 \| (1 << 16) \| (val & 0x7FC) \| (i << 11);
	49	#else
	50	s->config_reg = 0x80000000 \| (0 << 16) \| (val & 0x7FC) \| (i << 11);
	51	#endif
	52	}
	53
	54	static uint32_t pci_unin_main_config_readl (void *opaque,
	55	target_phys_addr_t addr)
	56	{
	57	UNINState *s = opaque;
	58	uint32_t val;
	59	int devfn;
	60
	61	devfn = (s->config_reg >> 8) & 0xFF;
	62	val = (1 << (devfn >> 3)) \| ((devfn & 0x07) << 8) \| (s->config_reg & 0xFC);
	63	#ifdef TARGET_WORDS_BIGENDIAN
	64	val = bswap32(val);
	65	#endif
	66
	67	return val;
	68	}
	69
	70	static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
	71	&pci_unin_main_config_writel,
	72	&pci_unin_main_config_writel,
	73	&pci_unin_main_config_writel,
	74	};
	75
	76	static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
	77	&pci_unin_main_config_readl,
	78	&pci_unin_main_config_readl,
	79	&pci_unin_main_config_readl,
	80	};
	81
	82	static CPUWriteMemoryFunc *pci_unin_main_write[] = {
	83	&pci_host_data_writeb,
	84	&pci_host_data_writew,
	85	&pci_host_data_writel,
	86	};
	87
	88	static CPUReadMemoryFunc *pci_unin_main_read[] = {
	89	&pci_host_data_readb,
	90	&pci_host_data_readw,
	91	&pci_host_data_readl,
92	};
93
94	#if 0
95
96	static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
97	uint32_t val)
98	{
99	UNINState *s = opaque;
100
101	#ifdef TARGET_WORDS_BIGENDIAN
102	val = bswap32(val);
103	#endif
104	s->config_reg = 0x80000000 \| (val & ~0x00000001);
105	}
106
107	static uint32_t pci_unin_config_readl (void *opaque,
108	target_phys_addr_t addr)
109	{
110	UNINState *s = opaque;
111	uint32_t val;
112
113	val = (s->config_reg \| 0x00000001) & ~0x80000000;
114	#ifdef TARGET_WORDS_BIGENDIAN
115	val = bswap32(val);
116	#endif
117
118	return val;
119	}
120
121	static CPUWriteMemoryFunc *pci_unin_config_write[] = {
122	&pci_unin_config_writel,
123	&pci_unin_config_writel,
124	&pci_unin_config_writel,
125	};
126
127	static CPUReadMemoryFunc *pci_unin_config_read[] = {
128	&pci_unin_config_readl,
129	&pci_unin_config_readl,
130	&pci_unin_config_readl,
131	};
132
133	static CPUWriteMemoryFunc *pci_unin_write[] = {
134	&pci_host_pci_writeb,
135	&pci_host_pci_writew,
136	&pci_host_pci_writel,
137	};
138
139	static CPUReadMemoryFunc *pci_unin_read[] = {
140	&pci_host_pci_readb,
141	&pci_host_pci_readw,
142	&pci_host_pci_readl,
143	};
144	#endif
145
d2b59317 PB	146	/* Don't know if this matches real hardware, but it agrees with OHW. */
d2b59317 PB	147	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	148	{
d2b59317 PB	149	return (irq_num + (pci_dev->devfn >> 3)) & 3;
	150	}
	151
d537cf6c	152	static void pci_unin_set_irq(qemu_irq *pic, int irq_num, int level)
d2b59317	153	{
d537cf6c	154	qemu_set_irq(pic[irq_num + 8], level);
502a5395 PB	155	}
502a5395 PB	156
d537cf6c	157	PCIBus pci_pmac_init(qemu_irq pic)
502a5395 PB	158	{
	159	UNINState *s;
	160	PCIDevice *d;
	161	int pci_mem_config, pci_mem_data;
	162
	163	/* Use values found on a real PowerMac */
	164	/* Uninorth main bus */
	165	s = qemu_mallocz(sizeof(UNINState));
d2b59317	166	s->bus = pci_register_bus(pci_unin_set_irq, pci_unin_map_irq,
80b3ada7	167	pic, 11 << 3, 4);
502a5395	168
5fafdf24	169	pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
502a5395 PB	170	pci_unin_main_config_write, s);
	171	pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
	172	pci_unin_main_write, s);
	173	cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
	174	cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
5fafdf24	175	d = pci_register_device(s->bus, "Uni-north main", sizeof(PCIDevice),
502a5395 PB	176	11 << 3, NULL, NULL);
	177	d->config[0x00] = 0x6b; // vendor_id : Apple
	178	d->config[0x01] = 0x10;
	179	d->config[0x02] = 0x1F; // device_id
	180	d->config[0x03] = 0x00;
	181	d->config[0x08] = 0x00; // revision
	182	d->config[0x0A] = 0x00; // class_sub = pci host
	183	d->config[0x0B] = 0x06; // class_base = PCI_bridge
	184	d->config[0x0C] = 0x08; // cache_line_size
	185	d->config[0x0D] = 0x10; // latency_timer
	186	d->config[0x0E] = 0x00; // header_type
	187	d->config[0x34] = 0x00; // capabilities_pointer
	188
9f083493	189	#if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
502a5395 PB	190	/* pci-to-pci bridge */
	191	d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
	192	NULL, NULL);
	193	d->config[0x00] = 0x11; // vendor_id : TI
	194	d->config[0x01] = 0x10;
	195	d->config[0x02] = 0x26; // device_id
	196	d->config[0x03] = 0x00;
	197	d->config[0x08] = 0x05; // revision
	198	d->config[0x0A] = 0x04; // class_sub = pci2pci
	199	d->config[0x0B] = 0x06; // class_base = PCI_bridge
	200	d->config[0x0C] = 0x08; // cache_line_size
	201	d->config[0x0D] = 0x20; // latency_timer
	202	d->config[0x0E] = 0x01; // header_type
	203
	204	d->config[0x18] = 0x01; // primary_bus
	205	d->config[0x19] = 0x02; // secondary_bus
	206	d->config[0x1A] = 0x02; // subordinate_bus
	207	d->config[0x1B] = 0x20; // secondary_latency_timer
	208	d->config[0x1C] = 0x11; // io_base
	209	d->config[0x1D] = 0x01; // io_limit
	210	d->config[0x20] = 0x00; // memory_base
	211	d->config[0x21] = 0x80;
	212	d->config[0x22] = 0x00; // memory_limit
	213	d->config[0x23] = 0x80;
	214	d->config[0x24] = 0x01; // prefetchable_memory_base
	215	d->config[0x25] = 0x80;
	216	d->config[0x26] = 0xF1; // prefectchable_memory_limit
	217	d->config[0x27] = 0x7F;
	218	// d->config[0x34] = 0xdc // capabilities_pointer
	219	#endif
	220	#if 0 // XXX: not needed for now
	221	/* Uninorth AGP bus */
	222	s = &pci_bridge[1];
5fafdf24	223	pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
502a5395 PB	224	pci_unin_config_write, s);
	225	pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
	226	pci_unin_write, s);
	227	cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
	228	cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
	229
	230	d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
	231	NULL, NULL);
	232	d->config[0x00] = 0x6b; // vendor_id : Apple
	233	d->config[0x01] = 0x10;
	234	d->config[0x02] = 0x20; // device_id
	235	d->config[0x03] = 0x00;
	236	d->config[0x08] = 0x00; // revision
	237	d->config[0x0A] = 0x00; // class_sub = pci host
	238	d->config[0x0B] = 0x06; // class_base = PCI_bridge
	239	d->config[0x0C] = 0x08; // cache_line_size
	240	d->config[0x0D] = 0x10; // latency_timer
	241	d->config[0x0E] = 0x00; // header_type
	242	// d->config[0x34] = 0x80; // capabilities_pointer
	243	#endif
	244
	245	#if 0 // XXX: not needed for now
	246	/* Uninorth internal bus */
	247	s = &pci_bridge[2];
5fafdf24	248	pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
502a5395 PB	249	pci_unin_config_write, s);
	250	pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
	251	pci_unin_write, s);
	252	cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
	253	cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
	254
	255	d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
	256	3, 11 << 3, NULL, NULL);
	257	d->config[0x00] = 0x6b; // vendor_id : Apple
	258	d->config[0x01] = 0x10;
	259	d->config[0x02] = 0x1E; // device_id
	260	d->config[0x03] = 0x00;
	261	d->config[0x08] = 0x00; // revision
	262	d->config[0x0A] = 0x00; // class_sub = pci host
	263	d->config[0x0B] = 0x06; // class_base = PCI_bridge
	264	d->config[0x0C] = 0x08; // cache_line_size
	265	d->config[0x0D] = 0x10; // latency_timer
	266	d->config[0x0E] = 0x00; // header_type
	267	d->config[0x34] = 0x00; // capabilities_pointer
	268	#endif
	269	return s->bus;
	270	}
	271