[qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "pci.h"
#include "pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

typedef struct UNINState {
    SysBusDevice busdev;
    PCIHostState host_state;
    ReadWriteHandler data_handler;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int retval;
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;

    return retval;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static void pci_unin_reset(void *opaque)
{
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ffs(reg & 0xfffff800) - 1;
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(ReadWriteHandler *handler,
                            pcibus_t addr, uint32_t val, int len)
{
    UNINState *s = container_of(handler, UNINState, data_handler);
    UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
    pci_data_write(s->host_state.bus,
                   unin_get_config_reg(s->host_state.config_reg, addr),
                   val, len);
}

static uint32_t unin_data_read(ReadWriteHandler *handler,
                               pcibus_t addr, int len)
{
    UNINState *s = container_of(handler, UNINState, data_handler);
    uint32_t val;

    val = pci_data_read(s->host_state.bus,
                        unin_get_config_reg(s->host_state.config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
    return val;
}

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
                                                 DEVICE_LITTLE_ENDIAN);
    s->data_handler.read = unin_data_read;
    s->data_handler.write = unin_data_write;
    pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
                                                 DEVICE_LITTLE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    qemu_register_reset(pci_unin_reset, &s->host_state);
    return 0;
}

static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth U3 AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
                                                 DEVICE_LITTLE_ENDIAN);
    s->data_handler.read = unin_data_read;
    s->data_handler.write = unin_data_write;
    pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
                                                 DEVICE_LITTLE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    qemu_register_reset(pci_unin_reset, &s->host_state);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
                                                 DEVICE_LITTLE_ENDIAN);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state,
                                               DEVICE_LITTLE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth internal bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
                                                 DEVICE_LITTLE_ENDIAN);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state,
                                               DEVICE_LITTLE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic,
                      MemoryRegion *address_space_mem,
                      MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, "uni-north");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic,
                                         address_space_mem,
                                         address_space_io,
                                         PCI_DEVFN(11, 0), 4);

#if 0
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, "uni-north-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
    dev = qdev_create(NULL, "uni-north-pci");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return d->host_state.bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic,
                         MemoryRegion *address_space_mem,
                         MemoryRegion *address_space_io)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, "u3-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);

    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic,
                                         address_space_mem,
                                         address_space_io,
                                         PCI_DEVFN(11, 0), 4);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");

    return d->host_state.bus;
}

static int unin_main_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static int unin_agp_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
    return 0;
}

static int u3_agp_pci_host_init(PCIDevice *d)
{
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
    return 0;
}

static int unin_internal_pci_host_init(PCIDevice *d)
{
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static PCIDeviceInfo unin_main_pci_host_info = {
    .qdev.name = "uni-north",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_main_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static PCIDeviceInfo u3_agp_pci_host_info = {
    .qdev.name = "u3-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = u3_agp_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static PCIDeviceInfo unin_agp_pci_host_info = {
    .qdev.name = "uni-north-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_agp_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static PCIDeviceInfo unin_internal_pci_host_info = {
    .qdev.name = "uni-north-pci",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_internal_pci_host_init,
    .vendor_id = PCI_VENDOR_ID_APPLE,
    .device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
    .revision  = 0x00,
    .class_id  = PCI_CLASS_BRIDGE_HOST,
};

static void unin_register_devices(void)
{
    sysbus_register_dev("uni-north", sizeof(UNINState),
                        pci_unin_main_init_device);
    pci_qdev_register(&unin_main_pci_host_info);
    sysbus_register_dev("u3-agp", sizeof(UNINState),
                        pci_u3_agp_init_device);
    pci_qdev_register(&u3_agp_pci_host_info);
    sysbus_register_dev("uni-north-agp", sizeof(UNINState),
                        pci_unin_agp_init_device);
    pci_qdev_register(&unin_agp_pci_host_info);
    sysbus_register_dev("uni-north-pci", sizeof(UNINState),
                        pci_unin_internal_init_device);
    pci_qdev_register(&unin_internal_pci_host_info);
}

device_init(unin_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "ppc_mac.h"
	26	#include "pci.h"
4f5e19e6	27	#include "pci_host.h"
87ecb68b	28
f3902383 BS	29	/* debug UniNorth */
	30	//#define DEBUG_UNIN
	31
	32	#ifdef DEBUG_UNIN
001faf32 BS	33	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	35	#else
001faf32	36	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	37	#endif
f3902383 BS	38
fa0be69a AG	39	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	40
2e29bd04 BS	41	typedef struct UNINState {
	42	SysBusDevice busdev;
	43	PCIHostState host_state;
01e0451a	44	ReadWriteHandler data_handler;
2e29bd04	45	} UNINState;
502a5395	46
d2b59317	47	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	48	{
fa0be69a AG	49	int retval;
	50	int devfn = pci_dev->devfn & 0x00FFFFFF;
	51
	52	retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
	53
	54	return retval;
d2b59317 PB	55	}
d2b59317 PB	56
5d4e84c8	57	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	58	{
5d4e84c8 JQ	59	qemu_irq *pic = opaque;
5d4e84c8 JQ	60
fa0be69a AG	61	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	62	unin_irq_line[irq_num], level);
	63	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	64	}
502a5395 PB	65
f3902383 BS	66	static void pci_unin_reset(void *opaque)
	67	{
	68	}
	69
d86f0e32 AG	70	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	71	{
	72	uint32_t retval;
	73
	74	if (reg & (1u << 31)) {
	75	/* XXX OpenBIOS compatibility hack */
	76	retval = reg \| (addr & 3);
	77	} else if (reg & 1) {
	78	/* CFA1 style */
	79	retval = (reg & ~7u) \| (addr & 7);
	80	} else {
	81	uint32_t slot, func;
	82
	83	/* Grab CFA0 style values */
	84	slot = ffs(reg & 0xfffff800) - 1;
	85	func = (reg >> 8) & 7;
	86
	87	/* ... and then convert them to x86 format */
	88	/* config pointer */
	89	retval = (reg & (0xff - 7)) \| (addr & 7);
	90	/* slot */
	91	retval \|= slot << 11;
	92	/* fn */
	93	retval \|= func << 8;
	94	}
	95
	96
	97	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	98	reg, addr, retval);
	99
	100	return retval;
	101	}
	102
01e0451a AL	103	static void unin_data_write(ReadWriteHandler *handler,
01e0451a AL	104	pcibus_t addr, uint32_t val, int len)
d86f0e32	105	{
01e0451a AL	106	UNINState *s = container_of(handler, UNINState, data_handler);
01e0451a AL	107	UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
d86f0e32 AG	108	pci_data_write(s->host_state.bus,
	109	unin_get_config_reg(s->host_state.config_reg, addr),
	110	val, len);
	111	}
	112
01e0451a AL	113	static uint32_t unin_data_read(ReadWriteHandler *handler,
01e0451a AL	114	pcibus_t addr, int len)
d86f0e32	115	{
01e0451a	116	UNINState *s = container_of(handler, UNINState, data_handler);
d86f0e32 AG	117	uint32_t val;
	118
	119	val = pci_data_read(s->host_state.bus,
	120	unin_get_config_reg(s->host_state.config_reg, addr),
	121	len);
01e0451a	122	UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
d86f0e32 AG	123	return val;
	124	}
	125
81a322d4	126	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395 PB	127	{
502a5395 PB	128	UNINState *s;
01e0451a	129	int pci_mem_config, pci_mem_data;
502a5395 PB	130
	131	/* Use values found on a real PowerMac */
	132	/* Uninorth main bus */
2e29bd04	133	s = FROM_SYSBUS(UNINState, dev);
502a5395	134
01e0451a AL	135	pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
	136	DEVICE_LITTLE_ENDIAN);
	137	s->data_handler.read = unin_data_read;
	138	s->data_handler.write = unin_data_write;
	139	pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
	140	DEVICE_LITTLE_ENDIAN);
	141	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	142	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
2e29bd04	143
2e29bd04	144	qemu_register_reset(pci_unin_reset, &s->host_state);
81a322d4	145	return 0;
2e29bd04 BS	146	}
2e29bd04 BS	147
0f921197 AG	148	static int pci_u3_agp_init_device(SysBusDevice *dev)
	149	{
	150	UNINState *s;
01e0451a	151	int pci_mem_config, pci_mem_data;
0f921197 AG	152
	153	/* Uninorth U3 AGP bus */
	154	s = FROM_SYSBUS(UNINState, dev);
	155
01e0451a AL	156	pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
	157	DEVICE_LITTLE_ENDIAN);
	158	s->data_handler.read = unin_data_read;
	159	s->data_handler.write = unin_data_write;
	160	pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
	161	DEVICE_LITTLE_ENDIAN);
	162	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	163	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
0f921197	164
0f921197 AG	165	qemu_register_reset(pci_unin_reset, &s->host_state);
	166
	167	return 0;
	168	}
	169
81a322d4	170	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04 BS	171	{
2e29bd04 BS	172	UNINState *s;
01e0451a	173	int pci_mem_config, pci_mem_data;
2e29bd04 BS	174
	175	/* Uninorth AGP bus */
	176	s = FROM_SYSBUS(UNINState, dev);
	177
01e0451a AL	178	pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
	179	DEVICE_LITTLE_ENDIAN);
	180	pci_mem_data = pci_host_data_register_mmio(&s->host_state,
	181	DEVICE_LITTLE_ENDIAN);
	182	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	183	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	184	return 0;
2e29bd04 BS	185	}
2e29bd04 BS	186
81a322d4	187	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04 BS	188	{
2e29bd04 BS	189	UNINState *s;
01e0451a	190	int pci_mem_config, pci_mem_data;
2e29bd04 BS	191
	192	/* Uninorth internal bus */
	193	s = FROM_SYSBUS(UNINState, dev);
	194
01e0451a AL	195	pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
	196	DEVICE_LITTLE_ENDIAN);
	197	pci_mem_data = pci_host_data_register_mmio(&s->host_state,
	198	DEVICE_LITTLE_ENDIAN);
	199	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	200	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	201	return 0;
2e29bd04 BS	202	}
2e29bd04 BS	203
aee97b84 AK	204	PCIBus pci_pmac_init(qemu_irq pic,
	205	MemoryRegion *address_space_mem,
	206	MemoryRegion *address_space_io)
2e29bd04 BS	207	{
	208	DeviceState *dev;
	209	SysBusDevice *s;
	210	UNINState *d;
	211
	212	/* Use values found on a real PowerMac */
	213	/* Uninorth main bus */
18dd19a7	214	dev = qdev_create(NULL, "uni-north");
e23a1b33	215	qdev_init_nofail(dev);
2e29bd04 BS	216	s = sysbus_from_qdev(dev);
2e29bd04 BS	217	d = FROM_SYSBUS(UNINState, s);
cdd0935c	218	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
2e29bd04	219	pci_unin_set_irq, pci_unin_map_irq,
aee97b84 AK	220	pic,
	221	address_space_mem,
	222	address_space_io,
1e39101c	223	PCI_DEVFN(11, 0), 4);
2e29bd04	224
60398748	225	#if 0
520128bd	226	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
60398748	227	#endif
2e29bd04 BS	228
	229	sysbus_mmio_map(s, 0, 0xf2800000);
	230	sysbus_mmio_map(s, 1, 0xf2c00000);
	231
	232	/* DEC 21154 bridge */
	233	#if 0
	234	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
520128bd	235	pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	236	#endif
	237
	238	/* Uninorth AGP bus */
520128bd	239	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
18dd19a7	240	dev = qdev_create(NULL, "uni-north-agp");
d27d06f2 BS	241	qdev_init_nofail(dev);
	242	s = sysbus_from_qdev(dev);
	243	sysbus_mmio_map(s, 0, 0xf0800000);
	244	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	245
	246	/* Uninorth internal bus */
	247	#if 0
	248	/* XXX: not needed for now */
520128bd	249	pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
18dd19a7	250	dev = qdev_create(NULL, "uni-north-pci");
d27d06f2 BS	251	qdev_init_nofail(dev);
	252	s = sysbus_from_qdev(dev);
	253	sysbus_mmio_map(s, 0, 0xf4800000);
	254	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	255	#endif
	256
	257	return d->host_state.bus;
	258	}
	259
aee97b84 AK	260	PCIBus pci_pmac_u3_init(qemu_irq pic,
	261	MemoryRegion *address_space_mem,
	262	MemoryRegion *address_space_io)
0f921197 AG	263	{
	264	DeviceState *dev;
	265	SysBusDevice *s;
	266	UNINState *d;
	267
	268	/* Uninorth AGP bus */
	269
	270	dev = qdev_create(NULL, "u3-agp");
	271	qdev_init_nofail(dev);
	272	s = sysbus_from_qdev(dev);
	273	d = FROM_SYSBUS(UNINState, s);
	274
	275	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
	276	pci_unin_set_irq, pci_unin_map_irq,
aee97b84 AK	277	pic,
	278	address_space_mem,
	279	address_space_io,
1e39101c	280	PCI_DEVFN(11, 0), 4);
0f921197 AG	281
	282	sysbus_mmio_map(s, 0, 0xf0800000);
	283	sysbus_mmio_map(s, 1, 0xf0c00000);
	284
	285	pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
	286
	287	return d->host_state.bus;
	288	}
	289
81a322d4	290	static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04	291	{
502a5395 PB	292	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	293	d->config[0x0D] = 0x10; // latency_timer
502a5395	294	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	295	return 0;
2e29bd04	296	}
502a5395	297
81a322d4	298	static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04	299	{
502a5395 PB	300	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	301	d->config[0x0D] = 0x10; // latency_timer
502a5395	302	// d->config[0x34] = 0x80; // capabilities_pointer
81a322d4	303	return 0;
2e29bd04	304	}
502a5395	305
0f921197 AG	306	static int u3_agp_pci_host_init(PCIDevice *d)
0f921197 AG	307	{
0f921197 AG	308	/* cache line size */
	309	d->config[0x0C] = 0x08;
	310	/* latency timer */
	311	d->config[0x0D] = 0x10;
0f921197 AG	312	return 0;
	313	}
	314
81a322d4	315	static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04	316	{
502a5395 PB	317	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	318	d->config[0x0D] = 0x10; // latency_timer
502a5395	319	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	320	return 0;
2e29bd04 BS	321	}
	322
	323	static PCIDeviceInfo unin_main_pci_host_info = {
18dd19a7	324	.qdev.name = "uni-north",
2e29bd04 BS	325	.qdev.size = sizeof(PCIDevice),
2e29bd04 BS	326	.init = unin_main_pci_host_init,
d7b61ecc IY	327	.vendor_id = PCI_VENDOR_ID_APPLE,
	328	.device_id = PCI_DEVICE_ID_APPLE_UNI_N_PCI,
	329	.revision = 0x00,
	330	.class_id = PCI_CLASS_BRIDGE_HOST,
2e29bd04 BS	331	};
2e29bd04 BS	332
0f921197 AG	333	static PCIDeviceInfo u3_agp_pci_host_info = {
	334	.qdev.name = "u3-agp",
	335	.qdev.size = sizeof(PCIDevice),
	336	.init = u3_agp_pci_host_init,
d7b61ecc IY	337	.vendor_id = PCI_VENDOR_ID_APPLE,
	338	.device_id = PCI_DEVICE_ID_APPLE_U3_AGP,
	339	.revision = 0x00,
	340	.class_id = PCI_CLASS_BRIDGE_HOST,
0f921197 AG	341	};
0f921197 AG	342
2e29bd04	343	static PCIDeviceInfo unin_agp_pci_host_info = {
18dd19a7	344	.qdev.name = "uni-north-agp",
2e29bd04 BS	345	.qdev.size = sizeof(PCIDevice),
2e29bd04 BS	346	.init = unin_agp_pci_host_init,
d7b61ecc IY	347	.vendor_id = PCI_VENDOR_ID_APPLE,
	348	.device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP,
	349	.revision = 0x00,
	350	.class_id = PCI_CLASS_BRIDGE_HOST,
2e29bd04 BS	351	};
	352
	353	static PCIDeviceInfo unin_internal_pci_host_info = {
18dd19a7	354	.qdev.name = "uni-north-pci",
2e29bd04 BS	355	.qdev.size = sizeof(PCIDevice),
2e29bd04 BS	356	.init = unin_internal_pci_host_init,
d7b61ecc IY	357	.vendor_id = PCI_VENDOR_ID_APPLE,
	358	.device_id = PCI_DEVICE_ID_APPLE_UNI_N_I_PCI,
	359	.revision = 0x00,
	360	.class_id = PCI_CLASS_BRIDGE_HOST,
2e29bd04 BS	361	};
	362
	363	static void unin_register_devices(void)
	364	{
18dd19a7	365	sysbus_register_dev("uni-north", sizeof(UNINState),
2e29bd04 BS	366	pci_unin_main_init_device);
2e29bd04 BS	367	pci_qdev_register(&unin_main_pci_host_info);
0f921197 AG	368	sysbus_register_dev("u3-agp", sizeof(UNINState),
	369	pci_u3_agp_init_device);
	370	pci_qdev_register(&u3_agp_pci_host_info);
18dd19a7	371	sysbus_register_dev("uni-north-agp", sizeof(UNINState),
2e29bd04 BS	372	pci_unin_agp_init_device);
2e29bd04 BS	373	pci_qdev_register(&unin_agp_pci_host_info);
18dd19a7	374	sysbus_register_dev("uni-north-pci", sizeof(UNINState),
2e29bd04 BS	375	pci_unin_internal_init_device);
2e29bd04 BS	376	pci_qdev_register(&unin_internal_pci_host_info);
502a5395	377	}
2e29bd04 BS	378
2e29bd04 BS	379	device_init(unin_register_devices)