[qemu.git] / hw / unin_pci.c

/*
 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "ppc_mac.h"
#include "pci.h"
#include "pci_host.h"

/* debug UniNorth */
//#define DEBUG_UNIN

#ifdef DEBUG_UNIN
#define UNIN_DPRINTF(fmt, ...)                                  \
    do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
#else
#define UNIN_DPRINTF(fmt, ...)
#endif

static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };

typedef struct UNINState {
    SysBusDevice busdev;
    PCIHostState host_state;
    ReadWriteHandler data_handler;
} UNINState;

static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
{
    int retval;
    int devfn = pci_dev->devfn & 0x00FFFFFF;

    retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;

    return retval;
}

static void pci_unin_set_irq(void *opaque, int irq_num, int level)
{
    qemu_irq *pic = opaque;

    UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
                 unin_irq_line[irq_num], level);
    qemu_set_irq(pic[unin_irq_line[irq_num]], level);
}

static void pci_unin_save(QEMUFile* f, void *opaque)
{
    PCIDevice *d = opaque;

    pci_device_save(d, f);
}

static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
{
    PCIDevice *d = opaque;

    if (version_id != 1)
        return -EINVAL;

    return pci_device_load(d, f);
}

static void pci_unin_reset(void *opaque)
{
}

static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
{
    uint32_t retval;

    if (reg & (1u << 31)) {
        /* XXX OpenBIOS compatibility hack */
        retval = reg | (addr & 3);
    } else if (reg & 1) {
        /* CFA1 style */
        retval = (reg & ~7u) | (addr & 7);
    } else {
        uint32_t slot, func;

        /* Grab CFA0 style values */
        slot = ffs(reg & 0xfffff800) - 1;
        func = (reg >> 8) & 7;

        /* ... and then convert them to x86 format */
        /* config pointer */
        retval = (reg & (0xff - 7)) | (addr & 7);
        /* slot */
        retval |= slot << 11;
        /* fn */
        retval |= func << 8;
    }


    UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
                 reg, addr, retval);

    return retval;
}

static void unin_data_write(ReadWriteHandler *handler,
                            pcibus_t addr, uint32_t val, int len)
{
    UNINState *s = container_of(handler, UNINState, data_handler);
    val = qemu_bswap_len(val, len);
    UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
    pci_data_write(s->host_state.bus,
                   unin_get_config_reg(s->host_state.config_reg, addr),
                   val, len);
}

static uint32_t unin_data_read(ReadWriteHandler *handler,
                               pcibus_t addr, int len)
{
    UNINState *s = container_of(handler, UNINState, data_handler);
    uint32_t val;

    val = pci_data_read(s->host_state.bus,
                        unin_get_config_reg(s->host_state.config_reg, addr),
                        len);
    UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
    val = qemu_bswap_len(val, len);
    return val;
}

static int pci_unin_main_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
                                                 DEVICE_LITTLE_ENDIAN);
    s->data_handler.read = unin_data_read;
    s->data_handler.write = unin_data_write;
    pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
                                                 DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    register_savevm(&dev->qdev, "uninorth", 0, 1,
                    pci_unin_save, pci_unin_load, &s->host_state);
    qemu_register_reset(pci_unin_reset, &s->host_state);
    return 0;
}

static int pci_u3_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth U3 AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
                                                 DEVICE_LITTLE_ENDIAN);
    s->data_handler.read = unin_data_read;
    s->data_handler.write = unin_data_write;
    pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
                                                 DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);

    register_savevm(&dev->qdev, "uninorth", 0, 1,
                    pci_unin_save, pci_unin_load, &s->host_state);
    qemu_register_reset(pci_unin_reset, &s->host_state);

    return 0;
}

static int pci_unin_agp_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth AGP bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
                                                 DEVICE_LITTLE_ENDIAN);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state,
                                               DEVICE_LITTLE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

static int pci_unin_internal_init_device(SysBusDevice *dev)
{
    UNINState *s;
    int pci_mem_config, pci_mem_data;

    /* Uninorth internal bus */
    s = FROM_SYSBUS(UNINState, dev);

    pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
                                                 DEVICE_LITTLE_ENDIAN);
    pci_mem_data = pci_host_data_register_mmio(&s->host_state,
                                               DEVICE_LITTLE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, pci_mem_config);
    sysbus_init_mmio(dev, 0x1000, pci_mem_data);
    return 0;
}

PCIBus *pci_pmac_init(qemu_irq *pic)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Use values found on a real PowerMac */
    /* Uninorth main bus */
    dev = qdev_create(NULL, "uni-north");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);
    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic, PCI_DEVFN(11, 0), 4);

#if 0
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
#endif

    sysbus_mmio_map(s, 0, 0xf2800000);
    sysbus_mmio_map(s, 1, 0xf2c00000);

    /* DEC 21154 bridge */
#if 0
    /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
#endif

    /* Uninorth AGP bus */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
    dev = qdev_create(NULL, "uni-north-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    /* Uninorth internal bus */
#if 0
    /* XXX: not needed for now */
    pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
    dev = qdev_create(NULL, "uni-north-pci");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    sysbus_mmio_map(s, 0, 0xf4800000);
    sysbus_mmio_map(s, 1, 0xf4c00000);
#endif

    return d->host_state.bus;
}

PCIBus *pci_pmac_u3_init(qemu_irq *pic)
{
    DeviceState *dev;
    SysBusDevice *s;
    UNINState *d;

    /* Uninorth AGP bus */

    dev = qdev_create(NULL, "u3-agp");
    qdev_init_nofail(dev);
    s = sysbus_from_qdev(dev);
    d = FROM_SYSBUS(UNINState, s);

    d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
                                         pci_unin_set_irq, pci_unin_map_irq,
                                         pic, PCI_DEVFN(11, 0), 4);

    sysbus_mmio_map(s, 0, 0xf0800000);
    sysbus_mmio_map(s, 1, 0xf0c00000);

    pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");

    return d->host_state.bus;
}

static int unin_main_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static int unin_agp_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    //    d->config[0x34] = 0x80; // capabilities_pointer
    return 0;
}

static int u3_agp_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP);
    /* revision */
    d->config[0x08] = 0x00;
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    /* cache line size */
    d->config[0x0C] = 0x08;
    /* latency timer */
    d->config[0x0D] = 0x10;
    return 0;
}

static int unin_internal_pci_host_init(PCIDevice *d)
{
    pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
    pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
    d->config[0x08] = 0x00; // revision
    pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
    d->config[0x0C] = 0x08; // cache_line_size
    d->config[0x0D] = 0x10; // latency_timer
    d->config[0x34] = 0x00; // capabilities_pointer
    return 0;
}

static PCIDeviceInfo unin_main_pci_host_info = {
    .qdev.name = "uni-north",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_main_pci_host_init,
};

static PCIDeviceInfo u3_agp_pci_host_info = {
    .qdev.name = "u3-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = u3_agp_pci_host_init,
};

static PCIDeviceInfo unin_agp_pci_host_info = {
    .qdev.name = "uni-north-agp",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_agp_pci_host_init,
};

static PCIDeviceInfo unin_internal_pci_host_info = {
    .qdev.name = "uni-north-pci",
    .qdev.size = sizeof(PCIDevice),
    .init      = unin_internal_pci_host_init,
};

static void unin_register_devices(void)
{
    sysbus_register_dev("uni-north", sizeof(UNINState),
                        pci_unin_main_init_device);
    pci_qdev_register(&unin_main_pci_host_info);
    sysbus_register_dev("u3-agp", sizeof(UNINState),
                        pci_u3_agp_init_device);
    pci_qdev_register(&u3_agp_pci_host_info);
    sysbus_register_dev("uni-north-agp", sizeof(UNINState),
                        pci_unin_agp_init_device);
    pci_qdev_register(&unin_agp_pci_host_info);
    sysbus_register_dev("uni-north-pci", sizeof(UNINState),
                        pci_unin_internal_init_device);
    pci_qdev_register(&unin_internal_pci_host_info);
}

device_init(unin_register_devices)
Commit	Line	Data
502a5395 PB	1	/*
	2	* QEMU Uninorth PCI host (for all Mac99 and newer machines)
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
5fafdf24	5	*
502a5395 PB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "ppc_mac.h"
	26	#include "pci.h"
4f5e19e6	27	#include "pci_host.h"
87ecb68b	28
f3902383 BS	29	/* debug UniNorth */
	30	//#define DEBUG_UNIN
	31
	32	#ifdef DEBUG_UNIN
001faf32 BS	33	#define UNIN_DPRINTF(fmt, ...) \
001faf32 BS	34	do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
f3902383	35	#else
001faf32	36	#define UNIN_DPRINTF(fmt, ...)
f3902383 BS	37	#endif
f3902383 BS	38
fa0be69a AG	39	static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
fa0be69a AG	40
2e29bd04 BS	41	typedef struct UNINState {
	42	SysBusDevice busdev;
	43	PCIHostState host_state;
d86f0e32	44	ReadWriteHandler data_handler;
2e29bd04	45	} UNINState;
502a5395	46
d2b59317	47	static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
502a5395	48	{
fa0be69a AG	49	int retval;
	50	int devfn = pci_dev->devfn & 0x00FFFFFF;
	51
	52	retval = (((devfn >> 11) & 0x1F) + irq_num) & 3;
	53
	54	return retval;
d2b59317 PB	55	}
d2b59317 PB	56
5d4e84c8	57	static void pci_unin_set_irq(void *opaque, int irq_num, int level)
d2b59317	58	{
5d4e84c8 JQ	59	qemu_irq *pic = opaque;
5d4e84c8 JQ	60
fa0be69a AG	61	UNIN_DPRINTF("%s: setting INT %d = %d\n", __func__,
	62	unin_irq_line[irq_num], level);
	63	qemu_set_irq(pic[unin_irq_line[irq_num]], level);
502a5395 PB	64	}
502a5395 PB	65
f3902383 BS	66	static void pci_unin_save(QEMUFile* f, void *opaque)
	67	{
	68	PCIDevice *d = opaque;
	69
	70	pci_device_save(d, f);
	71	}
	72
	73	static int pci_unin_load(QEMUFile* f, void *opaque, int version_id)
	74	{
	75	PCIDevice *d = opaque;
	76
	77	if (version_id != 1)
	78	return -EINVAL;
	79
	80	return pci_device_load(d, f);
	81	}
	82
	83	static void pci_unin_reset(void *opaque)
	84	{
	85	}
	86
d86f0e32 AG	87	static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
	88	{
	89	uint32_t retval;
	90
	91	if (reg & (1u << 31)) {
	92	/* XXX OpenBIOS compatibility hack */
	93	retval = reg \| (addr & 3);
	94	} else if (reg & 1) {
	95	/* CFA1 style */
	96	retval = (reg & ~7u) \| (addr & 7);
	97	} else {
	98	uint32_t slot, func;
	99
	100	/* Grab CFA0 style values */
	101	slot = ffs(reg & 0xfffff800) - 1;
	102	func = (reg >> 8) & 7;
	103
	104	/* ... and then convert them to x86 format */
	105	/* config pointer */
	106	retval = (reg & (0xff - 7)) \| (addr & 7);
	107	/* slot */
	108	retval \|= slot << 11;
	109	/* fn */
	110	retval \|= func << 8;
	111	}
	112
	113
	114	UNIN_DPRINTF("Converted config space accessor %08x/%08x -> %08x\n",
	115	reg, addr, retval);
	116
	117	return retval;
	118	}
	119
	120	static void unin_data_write(ReadWriteHandler *handler,
	121	pcibus_t addr, uint32_t val, int len)
	122	{
	123	UNINState *s = container_of(handler, UNINState, data_handler);
d86f0e32	124	val = qemu_bswap_len(val, len);
d86f0e32 AG	125	UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
	126	pci_data_write(s->host_state.bus,
	127	unin_get_config_reg(s->host_state.config_reg, addr),
	128	val, len);
	129	}
	130
	131	static uint32_t unin_data_read(ReadWriteHandler *handler,
	132	pcibus_t addr, int len)
	133	{
	134	UNINState *s = container_of(handler, UNINState, data_handler);
	135	uint32_t val;
	136
	137	val = pci_data_read(s->host_state.bus,
	138	unin_get_config_reg(s->host_state.config_reg, addr),
	139	len);
	140	UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
d86f0e32	141	val = qemu_bswap_len(val, len);
d86f0e32 AG	142	return val;
	143	}
	144
81a322d4	145	static int pci_unin_main_init_device(SysBusDevice *dev)
502a5395 PB	146	{
502a5395 PB	147	UNINState *s;
502a5395 PB	148	int pci_mem_config, pci_mem_data;
	149
	150	/* Use values found on a real PowerMac */
	151	/* Uninorth main bus */
2e29bd04	152	s = FROM_SYSBUS(UNINState, dev);
502a5395	153
6ebf5905 AG	154	pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
6ebf5905 AG	155	DEVICE_LITTLE_ENDIAN);
d86f0e32 AG	156	s->data_handler.read = unin_data_read;
d86f0e32 AG	157	s->data_handler.write = unin_data_write;
6bef0436 AG	158	pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
6bef0436 AG	159	DEVICE_NATIVE_ENDIAN);
2e29bd04 BS	160	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	161	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
	162
0be71e32 AW	163	register_savevm(&dev->qdev, "uninorth", 0, 1,
0be71e32 AW	164	pci_unin_save, pci_unin_load, &s->host_state);
2e29bd04	165	qemu_register_reset(pci_unin_reset, &s->host_state);
81a322d4	166	return 0;
2e29bd04 BS	167	}
2e29bd04 BS	168
0f921197 AG	169	static int pci_u3_agp_init_device(SysBusDevice *dev)
	170	{
	171	UNINState *s;
	172	int pci_mem_config, pci_mem_data;
	173
	174	/* Uninorth U3 AGP bus */
	175	s = FROM_SYSBUS(UNINState, dev);
	176
6ebf5905 AG	177	pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
6ebf5905 AG	178	DEVICE_LITTLE_ENDIAN);
0f921197 AG	179	s->data_handler.read = unin_data_read;
0f921197 AG	180	s->data_handler.write = unin_data_write;
6bef0436 AG	181	pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
6bef0436 AG	182	DEVICE_NATIVE_ENDIAN);
0f921197 AG	183	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
	184	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
	185
0be71e32 AW	186	register_savevm(&dev->qdev, "uninorth", 0, 1,
0be71e32 AW	187	pci_unin_save, pci_unin_load, &s->host_state);
0f921197 AG	188	qemu_register_reset(pci_unin_reset, &s->host_state);
	189
	190	return 0;
	191	}
	192
81a322d4	193	static int pci_unin_agp_init_device(SysBusDevice *dev)
2e29bd04 BS	194	{
	195	UNINState *s;
	196	int pci_mem_config, pci_mem_data;
	197
	198	/* Uninorth AGP bus */
	199	s = FROM_SYSBUS(UNINState, dev);
	200
6ebf5905 AG	201	pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
	202	DEVICE_LITTLE_ENDIAN);
	203	pci_mem_data = pci_host_data_register_mmio(&s->host_state,
	204	DEVICE_LITTLE_ENDIAN);
2e29bd04 BS	205	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
2e29bd04 BS	206	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	207	return 0;
2e29bd04 BS	208	}
2e29bd04 BS	209
81a322d4	210	static int pci_unin_internal_init_device(SysBusDevice *dev)
2e29bd04 BS	211	{
	212	UNINState *s;
	213	int pci_mem_config, pci_mem_data;
	214
	215	/* Uninorth internal bus */
	216	s = FROM_SYSBUS(UNINState, dev);
	217
6ebf5905 AG	218	pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
	219	DEVICE_LITTLE_ENDIAN);
	220	pci_mem_data = pci_host_data_register_mmio(&s->host_state,
	221	DEVICE_LITTLE_ENDIAN);
2e29bd04 BS	222	sysbus_init_mmio(dev, 0x1000, pci_mem_config);
2e29bd04 BS	223	sysbus_init_mmio(dev, 0x1000, pci_mem_data);
81a322d4	224	return 0;
2e29bd04 BS	225	}
	226
	227	PCIBus pci_pmac_init(qemu_irq pic)
	228	{
	229	DeviceState *dev;
	230	SysBusDevice *s;
	231	UNINState *d;
	232
	233	/* Use values found on a real PowerMac */
	234	/* Uninorth main bus */
18dd19a7	235	dev = qdev_create(NULL, "uni-north");
e23a1b33	236	qdev_init_nofail(dev);
2e29bd04 BS	237	s = sysbus_from_qdev(dev);
2e29bd04 BS	238	d = FROM_SYSBUS(UNINState, s);
cdd0935c	239	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
2e29bd04	240	pci_unin_set_irq, pci_unin_map_irq,
520128bd	241	pic, PCI_DEVFN(11, 0), 4);
2e29bd04	242
60398748	243	#if 0
520128bd	244	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north");
60398748	245	#endif
2e29bd04 BS	246
	247	sysbus_mmio_map(s, 0, 0xf2800000);
	248	sysbus_mmio_map(s, 1, 0xf2c00000);
	249
	250	/* DEC 21154 bridge */
	251	#if 0
	252	/* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
520128bd	253	pci_create_simple(d->host_state.bus, PCI_DEVFN(12, 0), "dec-21154");
2e29bd04 BS	254	#endif
	255
	256	/* Uninorth AGP bus */
520128bd	257	pci_create_simple(d->host_state.bus, PCI_DEVFN(11, 0), "uni-north-agp");
18dd19a7	258	dev = qdev_create(NULL, "uni-north-agp");
d27d06f2 BS	259	qdev_init_nofail(dev);
	260	s = sysbus_from_qdev(dev);
	261	sysbus_mmio_map(s, 0, 0xf0800000);
	262	sysbus_mmio_map(s, 1, 0xf0c00000);
2e29bd04 BS	263
	264	/* Uninorth internal bus */
	265	#if 0
	266	/* XXX: not needed for now */
520128bd	267	pci_create_simple(d->host_state.bus, PCI_DEVFN(14, 0), "uni-north-pci");
18dd19a7	268	dev = qdev_create(NULL, "uni-north-pci");
d27d06f2 BS	269	qdev_init_nofail(dev);
	270	s = sysbus_from_qdev(dev);
	271	sysbus_mmio_map(s, 0, 0xf4800000);
	272	sysbus_mmio_map(s, 1, 0xf4c00000);
2e29bd04 BS	273	#endif
	274
	275	return d->host_state.bus;
	276	}
	277
0f921197 AG	278	PCIBus pci_pmac_u3_init(qemu_irq pic)
	279	{
	280	DeviceState *dev;
	281	SysBusDevice *s;
	282	UNINState *d;
	283
	284	/* Uninorth AGP bus */
	285
	286	dev = qdev_create(NULL, "u3-agp");
	287	qdev_init_nofail(dev);
	288	s = sysbus_from_qdev(dev);
	289	d = FROM_SYSBUS(UNINState, s);
	290
	291	d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
	292	pci_unin_set_irq, pci_unin_map_irq,
520128bd	293	pic, PCI_DEVFN(11, 0), 4);
0f921197 AG	294
	295	sysbus_mmio_map(s, 0, 0xf0800000);
	296	sysbus_mmio_map(s, 1, 0xf0c00000);
	297
	298	pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp");
	299
	300	return d->host_state.bus;
	301	}
	302
81a322d4	303	static int unin_main_pci_host_init(PCIDevice *d)
2e29bd04	304	{
deb54399	305	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	306	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
502a5395	307	d->config[0x08] = 0x00; // revision
173a543b	308	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	309	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	310	d->config[0x0D] = 0x10; // latency_timer
502a5395	311	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	312	return 0;
2e29bd04	313	}
502a5395	314
81a322d4	315	static int unin_agp_pci_host_init(PCIDevice *d)
2e29bd04	316	{
deb54399 AL	317	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
deb54399 AL	318	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
502a5395	319	d->config[0x08] = 0x00; // revision
173a543b	320	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	321	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	322	d->config[0x0D] = 0x10; // latency_timer
502a5395	323	// d->config[0x34] = 0x80; // capabilities_pointer
81a322d4	324	return 0;
2e29bd04	325	}
502a5395	326
0f921197 AG	327	static int u3_agp_pci_host_init(PCIDevice *d)
	328	{
	329	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
	330	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP);
	331	/* revision */
	332	d->config[0x08] = 0x00;
	333	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
	334	/* cache line size */
	335	d->config[0x0C] = 0x08;
	336	/* latency timer */
	337	d->config[0x0D] = 0x10;
0f921197 AG	338	return 0;
	339	}
	340
81a322d4	341	static int unin_internal_pci_host_init(PCIDevice *d)
2e29bd04	342	{
deb54399	343	pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
4ebcf884	344	pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
502a5395	345	d->config[0x08] = 0x00; // revision
173a543b	346	pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
502a5395 PB	347	d->config[0x0C] = 0x08; // cache_line_size
502a5395 PB	348	d->config[0x0D] = 0x10; // latency_timer
502a5395	349	d->config[0x34] = 0x00; // capabilities_pointer
81a322d4	350	return 0;
2e29bd04 BS	351	}
	352
	353	static PCIDeviceInfo unin_main_pci_host_info = {
18dd19a7	354	.qdev.name = "uni-north",
2e29bd04 BS	355	.qdev.size = sizeof(PCIDevice),
	356	.init = unin_main_pci_host_init,
	357	};
	358
0f921197 AG	359	static PCIDeviceInfo u3_agp_pci_host_info = {
	360	.qdev.name = "u3-agp",
	361	.qdev.size = sizeof(PCIDevice),
	362	.init = u3_agp_pci_host_init,
	363	};
	364
2e29bd04	365	static PCIDeviceInfo unin_agp_pci_host_info = {
18dd19a7	366	.qdev.name = "uni-north-agp",
2e29bd04 BS	367	.qdev.size = sizeof(PCIDevice),
	368	.init = unin_agp_pci_host_init,
	369	};
	370
	371	static PCIDeviceInfo unin_internal_pci_host_info = {
18dd19a7	372	.qdev.name = "uni-north-pci",
2e29bd04 BS	373	.qdev.size = sizeof(PCIDevice),
	374	.init = unin_internal_pci_host_init,
	375	};
	376
	377	static void unin_register_devices(void)
	378	{
18dd19a7	379	sysbus_register_dev("uni-north", sizeof(UNINState),
2e29bd04 BS	380	pci_unin_main_init_device);
2e29bd04 BS	381	pci_qdev_register(&unin_main_pci_host_info);
0f921197 AG	382	sysbus_register_dev("u3-agp", sizeof(UNINState),
	383	pci_u3_agp_init_device);
	384	pci_qdev_register(&u3_agp_pci_host_info);
18dd19a7	385	sysbus_register_dev("uni-north-agp", sizeof(UNINState),
2e29bd04 BS	386	pci_unin_agp_init_device);
2e29bd04 BS	387	pci_qdev_register(&unin_agp_pci_host_info);
18dd19a7	388	sysbus_register_dev("uni-north-pci", sizeof(UNINState),
2e29bd04 BS	389	pci_unin_internal_init_device);
2e29bd04 BS	390	pci_qdev_register(&unin_internal_pci_host_info);
502a5395	391	}
2e29bd04 BS	392
2e29bd04 BS	393	device_init(unin_register_devices)