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94527ead GH |
1 | /* |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
5 | * | |
6 | * EHCI project was started by Mark Burkley, with contributions by | |
7 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
8 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
9 | * | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or(at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
94527ead GH |
23 | */ |
24 | ||
f1ae32a1 | 25 | #include "hw/hw.h" |
94527ead | 26 | #include "qemu-timer.h" |
f1ae32a1 GH |
27 | #include "hw/usb.h" |
28 | #include "hw/pci.h" | |
94527ead | 29 | #include "monitor.h" |
439a97cc | 30 | #include "trace.h" |
0ce668bc | 31 | #include "dma.h" |
94527ead GH |
32 | |
33 | #define EHCI_DEBUG 0 | |
94527ead | 34 | |
26d53979 | 35 | #if EHCI_DEBUG |
94527ead GH |
36 | #define DPRINTF printf |
37 | #else | |
38 | #define DPRINTF(...) | |
39 | #endif | |
40 | ||
94527ead GH |
41 | /* internal processing - reset HC to try and recover */ |
42 | #define USB_RET_PROCERR (-99) | |
43 | ||
44 | #define MMIO_SIZE 0x1000 | |
45 | ||
46 | /* Capability Registers Base Address - section 2.2 */ | |
47 | #define CAPREGBASE 0x0000 | |
48 | #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved | |
49 | #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # | |
50 | #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params | |
51 | #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params | |
52 | #define EECP HCCPARAMS + 1 | |
53 | #define HCSPPORTROUTE1 CAPREGBASE + 0x000c | |
54 | #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 | |
55 | ||
56 | #define OPREGBASE 0x0020 // Operational Registers Base Address | |
57 | ||
58 | #define USBCMD OPREGBASE + 0x0000 | |
59 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop | |
60 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
61 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
62 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
63 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
64 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
65 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
66 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
67 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
68 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
69 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
70 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
71 | ||
72 | #define USBSTS OPREGBASE + 0x0004 | |
73 | #define USBSTS_RO_MASK 0x0000003f | |
74 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
75 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
76 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
77 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
78 | #define USBSTS_HSE (1 << 4) // Host System Error | |
79 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
80 | #define USBSTS_HALT (1 << 12) // HC Halted | |
81 | #define USBSTS_REC (1 << 13) // Reclamation | |
82 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
83 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
84 | ||
85 | /* | |
86 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
87 | * so no need to redefine here. | |
88 | */ | |
89 | #define USBINTR OPREGBASE + 0x0008 | |
90 | #define USBINTR_MASK 0x0000003f | |
91 | ||
92 | #define FRINDEX OPREGBASE + 0x000c | |
93 | #define CTRLDSSEGMENT OPREGBASE + 0x0010 | |
94 | #define PERIODICLISTBASE OPREGBASE + 0x0014 | |
95 | #define ASYNCLISTADDR OPREGBASE + 0x0018 | |
96 | #define ASYNCLISTADDR_MASK 0xffffffe0 | |
97 | ||
98 | #define CONFIGFLAG OPREGBASE + 0x0040 | |
99 | ||
100 | #define PORTSC (OPREGBASE + 0x0044) | |
101 | #define PORTSC_BEGIN PORTSC | |
102 | #define PORTSC_END (PORTSC + 4 * NB_PORTS) | |
103 | /* | |
c44fd61c | 104 | * Bits that are reserved or are read-only are masked out of values |
94527ead GH |
105 | * written to us by software |
106 | */ | |
a0a3167a | 107 | #define PORTSC_RO_MASK 0x007001c0 |
94527ead GH |
108 | #define PORTSC_RWC_MASK 0x0000002a |
109 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
110 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
111 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
112 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
113 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
114 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
115 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
116 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
117 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
118 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
119 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
120 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
121 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
122 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
123 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
124 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
125 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
126 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
127 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
128 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
129 | ||
130 | #define FRAME_TIMER_FREQ 1000 | |
adddecb1 | 131 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
94527ead GH |
132 | |
133 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
5cc194ca | 134 | #define NB_PORTS 6 // Number of downstream ports |
94527ead GH |
135 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
136 | #define MAX_ITERATIONS 20 // Max number of QH before we break the loop | |
137 | #define MAX_QH 100 // Max allowable queue heads in a chain | |
138 | ||
139 | /* Internal periodic / asynchronous schedule state machine states | |
140 | */ | |
141 | typedef enum { | |
142 | EST_INACTIVE = 1000, | |
143 | EST_ACTIVE, | |
144 | EST_EXECUTING, | |
145 | EST_SLEEPING, | |
146 | /* The following states are internal to the state machine function | |
147 | */ | |
148 | EST_WAITLISTHEAD, | |
149 | EST_FETCHENTRY, | |
150 | EST_FETCHQH, | |
151 | EST_FETCHITD, | |
2fe80192 | 152 | EST_FETCHSITD, |
94527ead GH |
153 | EST_ADVANCEQUEUE, |
154 | EST_FETCHQTD, | |
155 | EST_EXECUTE, | |
156 | EST_WRITEBACK, | |
157 | EST_HORIZONTALQH | |
158 | } EHCI_STATES; | |
159 | ||
160 | /* macros for accessing fields within next link pointer entry */ | |
161 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
162 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
163 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
164 | ||
165 | /* link pointer types */ | |
166 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
167 | #define NLPTR_TYPE_QH 1 // queue head | |
168 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
169 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
170 | ||
171 | ||
172 | /* EHCI spec version 1.0 Section 3.3 | |
173 | */ | |
174 | typedef struct EHCIitd { | |
175 | uint32_t next; | |
176 | ||
177 | uint32_t transact[8]; | |
178 | #define ITD_XACT_ACTIVE (1 << 31) | |
179 | #define ITD_XACT_DBERROR (1 << 30) | |
180 | #define ITD_XACT_BABBLE (1 << 29) | |
181 | #define ITD_XACT_XACTERR (1 << 28) | |
182 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 | |
183 | #define ITD_XACT_LENGTH_SH 16 | |
184 | #define ITD_XACT_IOC (1 << 15) | |
185 | #define ITD_XACT_PGSEL_MASK 0x00007000 | |
186 | #define ITD_XACT_PGSEL_SH 12 | |
187 | #define ITD_XACT_OFFSET_MASK 0x00000fff | |
188 | ||
189 | uint32_t bufptr[7]; | |
190 | #define ITD_BUFPTR_MASK 0xfffff000 | |
191 | #define ITD_BUFPTR_SH 12 | |
192 | #define ITD_BUFPTR_EP_MASK 0x00000f00 | |
193 | #define ITD_BUFPTR_EP_SH 8 | |
194 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f | |
195 | #define ITD_BUFPTR_DEVADDR_SH 0 | |
196 | #define ITD_BUFPTR_DIRECTION (1 << 11) | |
197 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff | |
198 | #define ITD_BUFPTR_MAXPKT_SH 0 | |
199 | #define ITD_BUFPTR_MULT_MASK 0x00000003 | |
e654887f | 200 | #define ITD_BUFPTR_MULT_SH 0 |
94527ead GH |
201 | } EHCIitd; |
202 | ||
203 | /* EHCI spec version 1.0 Section 3.4 | |
204 | */ | |
205 | typedef struct EHCIsitd { | |
206 | uint32_t next; // Standard next link pointer | |
207 | uint32_t epchar; | |
208 | #define SITD_EPCHAR_IO (1 << 31) | |
209 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 | |
210 | #define SITD_EPCHAR_PORTNUM_SH 24 | |
211 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 | |
212 | #define SITD_EPCHAR_HUBADDR_SH 16 | |
213 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 | |
214 | #define SITD_EPCHAR_EPNUM_SH 8 | |
215 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f | |
216 | ||
217 | uint32_t uframe; | |
218 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 | |
219 | #define SITD_UFRAME_CMASK_SH 8 | |
220 | #define SITD_UFRAME_SMASK_MASK 0x000000ff | |
221 | ||
222 | uint32_t results; | |
223 | #define SITD_RESULTS_IOC (1 << 31) | |
224 | #define SITD_RESULTS_PGSEL (1 << 30) | |
225 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 | |
226 | #define SITD_RESULTS_TYBYTES_SH 16 | |
227 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 | |
228 | #define SITD_RESULTS_CPROGMASK_SH 8 | |
229 | #define SITD_RESULTS_ACTIVE (1 << 7) | |
230 | #define SITD_RESULTS_ERR (1 << 6) | |
231 | #define SITD_RESULTS_DBERR (1 << 5) | |
232 | #define SITD_RESULTS_BABBLE (1 << 4) | |
233 | #define SITD_RESULTS_XACTERR (1 << 3) | |
234 | #define SITD_RESULTS_MISSEDUF (1 << 2) | |
235 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) | |
236 | ||
237 | uint32_t bufptr[2]; | |
238 | #define SITD_BUFPTR_MASK 0xfffff000 | |
239 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff | |
240 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 | |
241 | #define SITD_BUFPTR_TPOS_SH 3 | |
242 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 | |
243 | ||
244 | uint32_t backptr; // Standard next link pointer | |
245 | } EHCIsitd; | |
246 | ||
247 | /* EHCI spec version 1.0 Section 3.5 | |
248 | */ | |
249 | typedef struct EHCIqtd { | |
250 | uint32_t next; // Standard next link pointer | |
251 | uint32_t altnext; // Standard next link pointer | |
252 | uint32_t token; | |
253 | #define QTD_TOKEN_DTOGGLE (1 << 31) | |
254 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 | |
255 | #define QTD_TOKEN_TBYTES_SH 16 | |
256 | #define QTD_TOKEN_IOC (1 << 15) | |
257 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 | |
258 | #define QTD_TOKEN_CPAGE_SH 12 | |
259 | #define QTD_TOKEN_CERR_MASK 0x00000c00 | |
260 | #define QTD_TOKEN_CERR_SH 10 | |
261 | #define QTD_TOKEN_PID_MASK 0x00000300 | |
262 | #define QTD_TOKEN_PID_SH 8 | |
263 | #define QTD_TOKEN_ACTIVE (1 << 7) | |
264 | #define QTD_TOKEN_HALT (1 << 6) | |
265 | #define QTD_TOKEN_DBERR (1 << 5) | |
266 | #define QTD_TOKEN_BABBLE (1 << 4) | |
267 | #define QTD_TOKEN_XACTERR (1 << 3) | |
268 | #define QTD_TOKEN_MISSEDUF (1 << 2) | |
269 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) | |
270 | #define QTD_TOKEN_PING (1 << 0) | |
271 | ||
272 | uint32_t bufptr[5]; // Standard buffer pointer | |
273 | #define QTD_BUFPTR_MASK 0xfffff000 | |
0ce668bc | 274 | #define QTD_BUFPTR_SH 12 |
94527ead GH |
275 | } EHCIqtd; |
276 | ||
277 | /* EHCI spec version 1.0 Section 3.6 | |
278 | */ | |
279 | typedef struct EHCIqh { | |
280 | uint32_t next; // Standard next link pointer | |
281 | ||
282 | /* endpoint characteristics */ | |
283 | uint32_t epchar; | |
284 | #define QH_EPCHAR_RL_MASK 0xf0000000 | |
285 | #define QH_EPCHAR_RL_SH 28 | |
286 | #define QH_EPCHAR_C (1 << 27) | |
287 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 | |
288 | #define QH_EPCHAR_MPLEN_SH 16 | |
289 | #define QH_EPCHAR_H (1 << 15) | |
290 | #define QH_EPCHAR_DTC (1 << 14) | |
291 | #define QH_EPCHAR_EPS_MASK 0x00003000 | |
292 | #define QH_EPCHAR_EPS_SH 12 | |
293 | #define EHCI_QH_EPS_FULL 0 | |
294 | #define EHCI_QH_EPS_LOW 1 | |
295 | #define EHCI_QH_EPS_HIGH 2 | |
296 | #define EHCI_QH_EPS_RESERVED 3 | |
297 | ||
298 | #define QH_EPCHAR_EP_MASK 0x00000f00 | |
299 | #define QH_EPCHAR_EP_SH 8 | |
300 | #define QH_EPCHAR_I (1 << 7) | |
301 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f | |
302 | #define QH_EPCHAR_DEVADDR_SH 0 | |
303 | ||
304 | /* endpoint capabilities */ | |
305 | uint32_t epcap; | |
306 | #define QH_EPCAP_MULT_MASK 0xc0000000 | |
307 | #define QH_EPCAP_MULT_SH 30 | |
308 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 | |
309 | #define QH_EPCAP_PORTNUM_SH 23 | |
310 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 | |
311 | #define QH_EPCAP_HUBADDR_SH 16 | |
312 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 | |
313 | #define QH_EPCAP_CMASK_SH 8 | |
314 | #define QH_EPCAP_SMASK_MASK 0x000000ff | |
315 | #define QH_EPCAP_SMASK_SH 0 | |
316 | ||
317 | uint32_t current_qtd; // Standard next link pointer | |
318 | uint32_t next_qtd; // Standard next link pointer | |
319 | uint32_t altnext_qtd; | |
320 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e | |
321 | #define QH_ALTNEXT_NAKCNT_SH 1 | |
322 | ||
323 | uint32_t token; // Same as QTD token | |
324 | uint32_t bufptr[5]; // Standard buffer pointer | |
325 | #define BUFPTR_CPROGMASK_MASK 0x000000ff | |
326 | #define BUFPTR_FRAMETAG_MASK 0x0000001f | |
327 | #define BUFPTR_SBYTES_MASK 0x00000fe0 | |
328 | #define BUFPTR_SBYTES_SH 5 | |
329 | } EHCIqh; | |
330 | ||
331 | /* EHCI spec version 1.0 Section 3.7 | |
332 | */ | |
333 | typedef struct EHCIfstn { | |
334 | uint32_t next; // Standard next link pointer | |
335 | uint32_t backptr; // Standard next link pointer | |
336 | } EHCIfstn; | |
337 | ||
0122f472 GH |
338 | typedef struct EHCIQueue EHCIQueue; |
339 | typedef struct EHCIState EHCIState; | |
340 | ||
341 | enum async_state { | |
342 | EHCI_ASYNC_NONE = 0, | |
343 | EHCI_ASYNC_INFLIGHT, | |
344 | EHCI_ASYNC_FINISHED, | |
345 | }; | |
346 | ||
347 | struct EHCIQueue { | |
348 | EHCIState *ehci; | |
8ac6d699 | 349 | QTAILQ_ENTRY(EHCIQueue) next; |
adddecb1 GH |
350 | uint32_t seen; |
351 | uint64_t ts; | |
0122f472 GH |
352 | |
353 | /* cached data from guest - needs to be flushed | |
354 | * when guest removes an entry (doorbell, handshake sequence) | |
355 | */ | |
356 | EHCIqh qh; // copy of current QH (being worked on) | |
357 | uint32_t qhaddr; // address QH read from | |
358 | EHCIqtd qtd; // copy of current QTD (being worked on) | |
359 | uint32_t qtdaddr; // address QTD read from | |
360 | ||
361 | USBPacket packet; | |
0ce668bc | 362 | QEMUSGList sgl; |
0122f472 GH |
363 | int pid; |
364 | uint32_t tbytes; | |
365 | enum async_state async; | |
366 | int usb_status; | |
367 | }; | |
368 | ||
df5d5c5c HG |
369 | typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; |
370 | ||
0122f472 | 371 | struct EHCIState { |
94527ead | 372 | PCIDevice dev; |
0122f472 | 373 | USBBus bus; |
94527ead | 374 | qemu_irq irq; |
e57964f5 | 375 | MemoryRegion mem; |
a0a3167a | 376 | int companion_count; |
16a2dee6 GH |
377 | |
378 | /* properties */ | |
379 | uint32_t freq; | |
380 | uint32_t maxframes; | |
381 | ||
94527ead GH |
382 | /* |
383 | * EHCI spec version 1.0 Section 2.3 | |
384 | * Host Controller Operational Registers | |
385 | */ | |
386 | union { | |
387 | uint8_t mmio[MMIO_SIZE]; | |
388 | struct { | |
389 | uint8_t cap[OPREGBASE]; | |
390 | uint32_t usbcmd; | |
391 | uint32_t usbsts; | |
392 | uint32_t usbintr; | |
393 | uint32_t frindex; | |
394 | uint32_t ctrldssegment; | |
395 | uint32_t periodiclistbase; | |
396 | uint32_t asynclistaddr; | |
397 | uint32_t notused[9]; | |
398 | uint32_t configflag; | |
399 | uint32_t portsc[NB_PORTS]; | |
400 | }; | |
401 | }; | |
0122f472 | 402 | |
94527ead GH |
403 | /* |
404 | * Internal states, shadow registers, etc | |
405 | */ | |
406 | uint32_t sofv; | |
407 | QEMUTimer *frame_timer; | |
408 | int attach_poll_counter; | |
409 | int astate; // Current state in asynchronous schedule | |
410 | int pstate; // Current state in periodic schedule | |
411 | USBPort ports[NB_PORTS]; | |
a0a3167a | 412 | USBPort *companion_ports[NB_PORTS]; |
94527ead | 413 | uint32_t usbsts_pending; |
df5d5c5c HG |
414 | EHCIQueueHead aqueues; |
415 | EHCIQueueHead pqueues; | |
94527ead | 416 | |
0122f472 GH |
417 | uint32_t a_fetch_addr; // which address to look at next |
418 | uint32_t p_fetch_addr; // which address to look at next | |
94527ead | 419 | |
0122f472 | 420 | USBPacket ipacket; |
0ce668bc | 421 | QEMUSGList isgl; |
0122f472 | 422 | |
adddecb1 | 423 | uint64_t last_run_ns; |
0122f472 | 424 | }; |
94527ead GH |
425 | |
426 | #define SET_LAST_RUN_CLOCK(s) \ | |
adddecb1 | 427 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
94527ead GH |
428 | |
429 | /* nifty macros from Arnon's EHCI version */ | |
430 | #define get_field(data, field) \ | |
431 | (((data) & field##_MASK) >> field##_SH) | |
432 | ||
433 | #define set_field(data, newval, field) do { \ | |
434 | uint32_t val = *data; \ | |
435 | val &= ~ field##_MASK; \ | |
436 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
437 | *data = val; \ | |
438 | } while(0) | |
439 | ||
26d53979 | 440 | static const char *ehci_state_names[] = { |
aac882e7 GH |
441 | [EST_INACTIVE] = "INACTIVE", |
442 | [EST_ACTIVE] = "ACTIVE", | |
443 | [EST_EXECUTING] = "EXECUTING", | |
444 | [EST_SLEEPING] = "SLEEPING", | |
445 | [EST_WAITLISTHEAD] = "WAITLISTHEAD", | |
446 | [EST_FETCHENTRY] = "FETCH ENTRY", | |
447 | [EST_FETCHQH] = "FETCH QH", | |
448 | [EST_FETCHITD] = "FETCH ITD", | |
449 | [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", | |
450 | [EST_FETCHQTD] = "FETCH QTD", | |
451 | [EST_EXECUTE] = "EXECUTE", | |
452 | [EST_WRITEBACK] = "WRITEBACK", | |
453 | [EST_HORIZONTALQH] = "HORIZONTALQH", | |
26d53979 GH |
454 | }; |
455 | ||
456 | static const char *ehci_mmio_names[] = { | |
aac882e7 GH |
457 | [CAPLENGTH] = "CAPLENGTH", |
458 | [HCIVERSION] = "HCIVERSION", | |
459 | [HCSPARAMS] = "HCSPARAMS", | |
460 | [HCCPARAMS] = "HCCPARAMS", | |
461 | [USBCMD] = "USBCMD", | |
462 | [USBSTS] = "USBSTS", | |
463 | [USBINTR] = "USBINTR", | |
464 | [FRINDEX] = "FRINDEX", | |
465 | [PERIODICLISTBASE] = "P-LIST BASE", | |
466 | [ASYNCLISTADDR] = "A-LIST ADDR", | |
467 | [PORTSC_BEGIN] = "PORTSC #0", | |
468 | [PORTSC_BEGIN + 4] = "PORTSC #1", | |
469 | [PORTSC_BEGIN + 8] = "PORTSC #2", | |
470 | [PORTSC_BEGIN + 12] = "PORTSC #3", | |
335b8d20 GH |
471 | [PORTSC_BEGIN + 16] = "PORTSC #4", |
472 | [PORTSC_BEGIN + 20] = "PORTSC #5", | |
aac882e7 | 473 | [CONFIGFLAG] = "CONFIGFLAG", |
26d53979 | 474 | }; |
94527ead | 475 | |
26d53979 | 476 | static const char *nr2str(const char **n, size_t len, uint32_t nr) |
94527ead | 477 | { |
26d53979 GH |
478 | if (nr < len && n[nr] != NULL) { |
479 | return n[nr]; | |
94527ead | 480 | } else { |
26d53979 | 481 | return "unknown"; |
94527ead GH |
482 | } |
483 | } | |
94527ead | 484 | |
26d53979 GH |
485 | static const char *state2str(uint32_t state) |
486 | { | |
487 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
488 | } | |
489 | ||
490 | static const char *addr2str(target_phys_addr_t addr) | |
491 | { | |
492 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); | |
493 | } | |
494 | ||
439a97cc GH |
495 | static void ehci_trace_usbsts(uint32_t mask, int state) |
496 | { | |
497 | /* interrupts */ | |
498 | if (mask & USBSTS_INT) { | |
499 | trace_usb_ehci_usbsts("INT", state); | |
500 | } | |
501 | if (mask & USBSTS_ERRINT) { | |
502 | trace_usb_ehci_usbsts("ERRINT", state); | |
503 | } | |
504 | if (mask & USBSTS_PCD) { | |
505 | trace_usb_ehci_usbsts("PCD", state); | |
506 | } | |
507 | if (mask & USBSTS_FLR) { | |
508 | trace_usb_ehci_usbsts("FLR", state); | |
509 | } | |
510 | if (mask & USBSTS_HSE) { | |
511 | trace_usb_ehci_usbsts("HSE", state); | |
512 | } | |
513 | if (mask & USBSTS_IAA) { | |
514 | trace_usb_ehci_usbsts("IAA", state); | |
515 | } | |
516 | ||
517 | /* status */ | |
518 | if (mask & USBSTS_HALT) { | |
519 | trace_usb_ehci_usbsts("HALT", state); | |
520 | } | |
521 | if (mask & USBSTS_REC) { | |
522 | trace_usb_ehci_usbsts("REC", state); | |
523 | } | |
524 | if (mask & USBSTS_PSS) { | |
525 | trace_usb_ehci_usbsts("PSS", state); | |
526 | } | |
527 | if (mask & USBSTS_ASS) { | |
528 | trace_usb_ehci_usbsts("ASS", state); | |
529 | } | |
530 | } | |
531 | ||
532 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
533 | { | |
534 | if ((s->usbsts & mask) == mask) { | |
535 | return; | |
536 | } | |
537 | ehci_trace_usbsts(mask, 1); | |
538 | s->usbsts |= mask; | |
539 | } | |
540 | ||
541 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
542 | { | |
543 | if ((s->usbsts & mask) == 0) { | |
544 | return; | |
545 | } | |
546 | ehci_trace_usbsts(mask, 0); | |
547 | s->usbsts &= ~mask; | |
548 | } | |
94527ead GH |
549 | |
550 | static inline void ehci_set_interrupt(EHCIState *s, int intr) | |
551 | { | |
552 | int level = 0; | |
553 | ||
554 | // TODO honour interrupt threshold requests | |
555 | ||
439a97cc | 556 | ehci_set_usbsts(s, intr); |
94527ead GH |
557 | |
558 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { | |
559 | level = 1; | |
560 | } | |
561 | ||
562 | qemu_set_irq(s->irq, level); | |
563 | } | |
564 | ||
565 | static inline void ehci_record_interrupt(EHCIState *s, int intr) | |
566 | { | |
567 | s->usbsts_pending |= intr; | |
568 | } | |
569 | ||
570 | static inline void ehci_commit_interrupt(EHCIState *s) | |
571 | { | |
572 | if (!s->usbsts_pending) { | |
573 | return; | |
574 | } | |
575 | ehci_set_interrupt(s, s->usbsts_pending); | |
576 | s->usbsts_pending = 0; | |
577 | } | |
578 | ||
26d53979 GH |
579 | static void ehci_set_state(EHCIState *s, int async, int state) |
580 | { | |
581 | if (async) { | |
582 | trace_usb_ehci_state("async", state2str(state)); | |
583 | s->astate = state; | |
584 | } else { | |
585 | trace_usb_ehci_state("periodic", state2str(state)); | |
586 | s->pstate = state; | |
587 | } | |
588 | } | |
589 | ||
590 | static int ehci_get_state(EHCIState *s, int async) | |
591 | { | |
592 | return async ? s->astate : s->pstate; | |
593 | } | |
594 | ||
0122f472 GH |
595 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
596 | { | |
597 | if (async) { | |
598 | s->a_fetch_addr = addr; | |
599 | } else { | |
600 | s->p_fetch_addr = addr; | |
601 | } | |
602 | } | |
603 | ||
604 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
605 | { | |
606 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
607 | } | |
608 | ||
8ac6d699 | 609 | static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) |
26d53979 | 610 | { |
025b168c GH |
611 | /* need three here due to argument count limits */ |
612 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
613 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
614 | trace_usb_ehci_qh_fields(addr, | |
615 | get_field(qh->epchar, QH_EPCHAR_RL), | |
616 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
617 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
618 | get_field(qh->epchar, QH_EPCHAR_EP), | |
619 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
620 | trace_usb_ehci_qh_bits(addr, | |
621 | (bool)(qh->epchar & QH_EPCHAR_C), | |
622 | (bool)(qh->epchar & QH_EPCHAR_H), | |
623 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
624 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
26d53979 GH |
625 | } |
626 | ||
8ac6d699 | 627 | static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) |
26d53979 | 628 | { |
025b168c GH |
629 | /* need three here due to argument count limits */ |
630 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
631 | trace_usb_ehci_qtd_fields(addr, | |
632 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
633 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
634 | get_field(qtd->token, QTD_TOKEN_CERR), | |
635 | get_field(qtd->token, QTD_TOKEN_PID)); | |
636 | trace_usb_ehci_qtd_bits(addr, | |
637 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
638 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
639 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
640 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
641 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
26d53979 GH |
642 | } |
643 | ||
644 | static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) | |
645 | { | |
e654887f GH |
646 | trace_usb_ehci_itd(addr, itd->next, |
647 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
648 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
649 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
650 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
26d53979 GH |
651 | } |
652 | ||
2fe80192 GH |
653 | static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr, |
654 | EHCIsitd *sitd) | |
655 | { | |
656 | trace_usb_ehci_sitd(addr, sitd->next, | |
657 | (bool)(sitd->results & SITD_RESULTS_ACTIVE)); | |
658 | } | |
659 | ||
8ac6d699 GH |
660 | /* queue management */ |
661 | ||
662 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async) | |
663 | { | |
df5d5c5c | 664 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
665 | EHCIQueue *q; |
666 | ||
7267c094 | 667 | q = g_malloc0(sizeof(*q)); |
8ac6d699 | 668 | q->ehci = ehci; |
df5d5c5c | 669 | QTAILQ_INSERT_HEAD(head, q, next); |
8ac6d699 GH |
670 | trace_usb_ehci_queue_action(q, "alloc"); |
671 | return q; | |
672 | } | |
673 | ||
df5d5c5c | 674 | static void ehci_free_queue(EHCIQueue *q, int async) |
8ac6d699 | 675 | { |
df5d5c5c | 676 | EHCIQueueHead *head = async ? &q->ehci->aqueues : &q->ehci->pqueues; |
8ac6d699 GH |
677 | trace_usb_ehci_queue_action(q, "free"); |
678 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
679 | usb_cancel_packet(&q->packet); | |
680 | } | |
df5d5c5c | 681 | QTAILQ_REMOVE(head, q, next); |
7267c094 | 682 | g_free(q); |
8ac6d699 GH |
683 | } |
684 | ||
df5d5c5c HG |
685 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr, |
686 | int async) | |
8ac6d699 | 687 | { |
df5d5c5c | 688 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
689 | EHCIQueue *q; |
690 | ||
df5d5c5c | 691 | QTAILQ_FOREACH(q, head, next) { |
8ac6d699 GH |
692 | if (addr == q->qhaddr) { |
693 | return q; | |
694 | } | |
695 | } | |
696 | return NULL; | |
697 | } | |
698 | ||
4be23939 | 699 | static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush) |
8ac6d699 | 700 | { |
df5d5c5c | 701 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
702 | EHCIQueue *q, *tmp; |
703 | ||
df5d5c5c | 704 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
8ac6d699 GH |
705 | if (q->seen) { |
706 | q->seen = 0; | |
adddecb1 | 707 | q->ts = ehci->last_run_ns; |
8ac6d699 GH |
708 | continue; |
709 | } | |
4be23939 | 710 | if (!flush && ehci->last_run_ns < q->ts + 250000000) { |
8ac6d699 GH |
711 | /* allow 0.25 sec idle */ |
712 | continue; | |
713 | } | |
df5d5c5c | 714 | ehci_free_queue(q, async); |
8ac6d699 GH |
715 | } |
716 | } | |
717 | ||
df5d5c5c | 718 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) |
07771f6f | 719 | { |
df5d5c5c | 720 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
07771f6f GH |
721 | EHCIQueue *q, *tmp; |
722 | ||
df5d5c5c | 723 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
f53c398a GH |
724 | if (!usb_packet_is_inflight(&q->packet) || |
725 | q->packet.ep->dev != dev) { | |
07771f6f GH |
726 | continue; |
727 | } | |
df5d5c5c | 728 | ehci_free_queue(q, async); |
07771f6f GH |
729 | } |
730 | } | |
731 | ||
df5d5c5c | 732 | static void ehci_queues_rip_all(EHCIState *ehci, int async) |
8ac6d699 | 733 | { |
df5d5c5c | 734 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
735 | EHCIQueue *q, *tmp; |
736 | ||
df5d5c5c HG |
737 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
738 | ehci_free_queue(q, async); | |
8ac6d699 GH |
739 | } |
740 | } | |
741 | ||
94527ead GH |
742 | /* Attach or detach a device on root hub */ |
743 | ||
744 | static void ehci_attach(USBPort *port) | |
745 | { | |
746 | EHCIState *s = port->opaque; | |
747 | uint32_t *portsc = &s->portsc[port->index]; | |
748 | ||
dcbd0b5c | 749 | trace_usb_ehci_port_attach(port->index, port->dev->product_desc); |
94527ead | 750 | |
a0a3167a HG |
751 | if (*portsc & PORTSC_POWNER) { |
752 | USBPort *companion = s->companion_ports[port->index]; | |
753 | companion->dev = port->dev; | |
754 | companion->ops->attach(companion); | |
755 | return; | |
756 | } | |
757 | ||
94527ead GH |
758 | *portsc |= PORTSC_CONNECT; |
759 | *portsc |= PORTSC_CSC; | |
760 | ||
a0a3167a | 761 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
762 | } |
763 | ||
764 | static void ehci_detach(USBPort *port) | |
765 | { | |
766 | EHCIState *s = port->opaque; | |
767 | uint32_t *portsc = &s->portsc[port->index]; | |
768 | ||
dcbd0b5c | 769 | trace_usb_ehci_port_detach(port->index); |
94527ead | 770 | |
a0a3167a HG |
771 | if (*portsc & PORTSC_POWNER) { |
772 | USBPort *companion = s->companion_ports[port->index]; | |
773 | companion->ops->detach(companion); | |
774 | companion->dev = NULL; | |
f76e1d81 HG |
775 | /* |
776 | * EHCI spec 4.2.2: "When a disconnect occurs... On the event, | |
777 | * the port ownership is returned immediately to the EHCI controller." | |
778 | */ | |
779 | *portsc &= ~PORTSC_POWNER; | |
a0a3167a HG |
780 | return; |
781 | } | |
782 | ||
df5d5c5c HG |
783 | ehci_queues_rip_device(s, port->dev, 0); |
784 | ehci_queues_rip_device(s, port->dev, 1); | |
4706ab6c | 785 | |
fbd97532 | 786 | *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
94527ead GH |
787 | *portsc |= PORTSC_CSC; |
788 | ||
a0a3167a | 789 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
790 | } |
791 | ||
4706ab6c HG |
792 | static void ehci_child_detach(USBPort *port, USBDevice *child) |
793 | { | |
794 | EHCIState *s = port->opaque; | |
a0a3167a HG |
795 | uint32_t portsc = s->portsc[port->index]; |
796 | ||
797 | if (portsc & PORTSC_POWNER) { | |
798 | USBPort *companion = s->companion_ports[port->index]; | |
799 | companion->ops->child_detach(companion, child); | |
a0a3167a HG |
800 | return; |
801 | } | |
4706ab6c | 802 | |
df5d5c5c HG |
803 | ehci_queues_rip_device(s, child, 0); |
804 | ehci_queues_rip_device(s, child, 1); | |
4706ab6c HG |
805 | } |
806 | ||
a0a3167a HG |
807 | static void ehci_wakeup(USBPort *port) |
808 | { | |
809 | EHCIState *s = port->opaque; | |
810 | uint32_t portsc = s->portsc[port->index]; | |
811 | ||
812 | if (portsc & PORTSC_POWNER) { | |
813 | USBPort *companion = s->companion_ports[port->index]; | |
814 | if (companion->ops->wakeup) { | |
815 | companion->ops->wakeup(companion); | |
816 | } | |
817 | } | |
818 | } | |
819 | ||
820 | static int ehci_register_companion(USBBus *bus, USBPort *ports[], | |
821 | uint32_t portcount, uint32_t firstport) | |
822 | { | |
823 | EHCIState *s = container_of(bus, EHCIState, bus); | |
824 | uint32_t i; | |
825 | ||
826 | if (firstport + portcount > NB_PORTS) { | |
827 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", | |
828 | "firstport on masterbus"); | |
829 | error_printf_unless_qmp( | |
830 | "firstport value of %u makes companion take ports %u - %u, which " | |
831 | "is outside of the valid range of 0 - %u\n", firstport, firstport, | |
832 | firstport + portcount - 1, NB_PORTS - 1); | |
833 | return -1; | |
834 | } | |
835 | ||
836 | for (i = 0; i < portcount; i++) { | |
837 | if (s->companion_ports[firstport + i]) { | |
838 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", | |
839 | "an USB masterbus"); | |
840 | error_printf_unless_qmp( | |
841 | "port %u on masterbus %s already has a companion assigned\n", | |
842 | firstport + i, bus->qbus.name); | |
843 | return -1; | |
844 | } | |
845 | } | |
846 | ||
847 | for (i = 0; i < portcount; i++) { | |
848 | s->companion_ports[firstport + i] = ports[i]; | |
849 | s->ports[firstport + i].speedmask |= | |
850 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; | |
851 | /* Ensure devs attached before the initial reset go to the companion */ | |
852 | s->portsc[firstport + i] = PORTSC_POWNER; | |
853 | } | |
854 | ||
855 | s->companion_count++; | |
856 | s->mmio[0x05] = (s->companion_count << 4) | portcount; | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
828143c6 GH |
861 | static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr) |
862 | { | |
863 | USBDevice *dev; | |
864 | USBPort *port; | |
865 | int i; | |
866 | ||
867 | for (i = 0; i < NB_PORTS; i++) { | |
868 | port = &ehci->ports[i]; | |
869 | if (!(ehci->portsc[i] & PORTSC_PED)) { | |
870 | DPRINTF("Port %d not enabled\n", i); | |
871 | continue; | |
872 | } | |
873 | dev = usb_find_device(port, addr); | |
874 | if (dev != NULL) { | |
875 | return dev; | |
876 | } | |
877 | } | |
878 | return NULL; | |
879 | } | |
880 | ||
94527ead GH |
881 | /* 4.1 host controller initialization */ |
882 | static void ehci_reset(void *opaque) | |
883 | { | |
884 | EHCIState *s = opaque; | |
94527ead | 885 | int i; |
a0a3167a | 886 | USBDevice *devs[NB_PORTS]; |
94527ead | 887 | |
439a97cc | 888 | trace_usb_ehci_reset(); |
94527ead | 889 | |
a0a3167a HG |
890 | /* |
891 | * Do the detach before touching portsc, so that it correctly gets send to | |
892 | * us or to our companion based on PORTSC_POWNER before the reset. | |
893 | */ | |
894 | for(i = 0; i < NB_PORTS; i++) { | |
895 | devs[i] = s->ports[i].dev; | |
891fb2cd GH |
896 | if (devs[i] && devs[i]->attached) { |
897 | usb_detach(&s->ports[i]); | |
a0a3167a HG |
898 | } |
899 | } | |
900 | ||
94527ead GH |
901 | memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); |
902 | ||
903 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
904 | s->usbsts = USBSTS_HALT; | |
905 | ||
906 | s->astate = EST_INACTIVE; | |
907 | s->pstate = EST_INACTIVE; | |
94527ead GH |
908 | s->attach_poll_counter = 0; |
909 | ||
910 | for(i = 0; i < NB_PORTS; i++) { | |
a0a3167a HG |
911 | if (s->companion_ports[i]) { |
912 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
913 | } else { | |
914 | s->portsc[i] = PORTSC_PPOWER; | |
915 | } | |
891fb2cd GH |
916 | if (devs[i] && devs[i]->attached) { |
917 | usb_attach(&s->ports[i]); | |
d28f4e2d | 918 | usb_device_reset(devs[i]); |
94527ead GH |
919 | } |
920 | } | |
df5d5c5c HG |
921 | ehci_queues_rip_all(s, 0); |
922 | ehci_queues_rip_all(s, 1); | |
81d37739 | 923 | qemu_del_timer(s->frame_timer); |
94527ead GH |
924 | } |
925 | ||
926 | static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) | |
927 | { | |
928 | EHCIState *s = ptr; | |
929 | uint32_t val; | |
930 | ||
931 | val = s->mmio[addr]; | |
932 | ||
933 | return val; | |
934 | } | |
935 | ||
936 | static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) | |
937 | { | |
938 | EHCIState *s = ptr; | |
939 | uint32_t val; | |
940 | ||
941 | val = s->mmio[addr] | (s->mmio[addr+1] << 8); | |
942 | ||
943 | return val; | |
944 | } | |
945 | ||
946 | static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) | |
947 | { | |
948 | EHCIState *s = ptr; | |
949 | uint32_t val; | |
950 | ||
951 | val = s->mmio[addr] | (s->mmio[addr+1] << 8) | | |
952 | (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); | |
953 | ||
439a97cc | 954 | trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); |
94527ead GH |
955 | return val; |
956 | } | |
957 | ||
958 | static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) | |
959 | { | |
960 | fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); | |
961 | exit(1); | |
962 | } | |
963 | ||
964 | static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) | |
965 | { | |
966 | fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); | |
967 | exit(1); | |
968 | } | |
969 | ||
a0a3167a HG |
970 | static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
971 | { | |
972 | USBDevice *dev = s->ports[port].dev; | |
973 | uint32_t *portsc = &s->portsc[port]; | |
974 | uint32_t orig; | |
975 | ||
976 | if (s->companion_ports[port] == NULL) | |
977 | return; | |
978 | ||
979 | owner = owner & PORTSC_POWNER; | |
980 | orig = *portsc & PORTSC_POWNER; | |
981 | ||
982 | if (!(owner ^ orig)) { | |
983 | return; | |
984 | } | |
985 | ||
891fb2cd GH |
986 | if (dev && dev->attached) { |
987 | usb_detach(&s->ports[port]); | |
a0a3167a HG |
988 | } |
989 | ||
990 | *portsc &= ~PORTSC_POWNER; | |
991 | *portsc |= owner; | |
992 | ||
891fb2cd GH |
993 | if (dev && dev->attached) { |
994 | usb_attach(&s->ports[port]); | |
a0a3167a HG |
995 | } |
996 | } | |
997 | ||
94527ead GH |
998 | static void handle_port_status_write(EHCIState *s, int port, uint32_t val) |
999 | { | |
1000 | uint32_t *portsc = &s->portsc[port]; | |
94527ead GH |
1001 | USBDevice *dev = s->ports[port].dev; |
1002 | ||
fbd97532 HG |
1003 | /* Clear rwc bits */ |
1004 | *portsc &= ~(val & PORTSC_RWC_MASK); | |
1005 | /* The guest may clear, but not set the PED bit */ | |
1006 | *portsc &= val | ~PORTSC_PED; | |
a0a3167a HG |
1007 | /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ |
1008 | handle_port_owner_write(s, port, val); | |
1009 | /* And finally apply RO_MASK */ | |
94527ead GH |
1010 | val &= PORTSC_RO_MASK; |
1011 | ||
94527ead | 1012 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { |
dcbd0b5c | 1013 | trace_usb_ehci_port_reset(port, 1); |
94527ead GH |
1014 | } |
1015 | ||
1016 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 1017 | trace_usb_ehci_port_reset(port, 0); |
891fb2cd | 1018 | if (dev && dev->attached) { |
d28f4e2d | 1019 | usb_port_reset(&s->ports[port]); |
94527ead GH |
1020 | *portsc &= ~PORTSC_CSC; |
1021 | } | |
1022 | ||
fbd97532 HG |
1023 | /* |
1024 | * Table 2.16 Set the enable bit(and enable bit change) to indicate | |
94527ead | 1025 | * to SW that this port has a high speed device attached |
94527ead | 1026 | */ |
891fb2cd | 1027 | if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { |
fbd97532 HG |
1028 | val |= PORTSC_PED; |
1029 | } | |
94527ead GH |
1030 | } |
1031 | ||
1032 | *portsc &= ~PORTSC_RO_MASK; | |
1033 | *portsc |= val; | |
94527ead GH |
1034 | } |
1035 | ||
1036 | static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) | |
1037 | { | |
1038 | EHCIState *s = ptr; | |
c4f8e211 GH |
1039 | uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); |
1040 | uint32_t old = *mmio; | |
94527ead | 1041 | int i; |
439a97cc | 1042 | |
c4f8e211 | 1043 | trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); |
94527ead GH |
1044 | |
1045 | /* Only aligned reads are allowed on OHCI */ | |
1046 | if (addr & 3) { | |
1047 | fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" | |
1048 | TARGET_FMT_plx "\n", addr); | |
1049 | return; | |
1050 | } | |
1051 | ||
1052 | if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { | |
1053 | handle_port_status_write(s, (addr-PORTSC)/4, val); | |
c4f8e211 | 1054 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); |
94527ead GH |
1055 | return; |
1056 | } | |
1057 | ||
1058 | if (addr < OPREGBASE) { | |
1059 | fprintf(stderr, "usb-ehci: write attempt to read-only register" | |
1060 | TARGET_FMT_plx "\n", addr); | |
1061 | return; | |
1062 | } | |
1063 | ||
1064 | ||
1065 | /* Do any register specific pre-write processing here. */ | |
94527ead GH |
1066 | switch(addr) { |
1067 | case USBCMD: | |
94527ead | 1068 | if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) { |
94527ead GH |
1069 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
1070 | SET_LAST_RUN_CLOCK(s); | |
439a97cc | 1071 | ehci_clear_usbsts(s, USBSTS_HALT); |
94527ead GH |
1072 | } |
1073 | ||
1074 | if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
94527ead | 1075 | qemu_del_timer(s->frame_timer); |
e850c2b4 HG |
1076 | ehci_queues_rip_all(s, 0); |
1077 | ehci_queues_rip_all(s, 1); | |
439a97cc | 1078 | ehci_set_usbsts(s, USBSTS_HALT); |
94527ead GH |
1079 | } |
1080 | ||
1081 | if (val & USBCMD_HCRESET) { | |
94527ead | 1082 | ehci_reset(s); |
81d37739 | 1083 | val = s->usbcmd; |
94527ead GH |
1084 | } |
1085 | ||
1086 | /* not supporting dynamic frame list size at the moment */ | |
1087 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
1088 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
1089 | val & USBCMD_FLS); | |
1090 | val &= ~USBCMD_FLS; | |
1091 | } | |
94527ead GH |
1092 | break; |
1093 | ||
94527ead GH |
1094 | case USBSTS: |
1095 | val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO | |
439a97cc GH |
1096 | ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC |
1097 | val = s->usbsts; | |
94527ead GH |
1098 | ehci_set_interrupt(s, 0); |
1099 | break; | |
1100 | ||
94527ead GH |
1101 | case USBINTR: |
1102 | val &= USBINTR_MASK; | |
94527ead GH |
1103 | break; |
1104 | ||
1105 | case FRINDEX: | |
1106 | s->sofv = val >> 3; | |
94527ead GH |
1107 | break; |
1108 | ||
1109 | case CONFIGFLAG: | |
94527ead GH |
1110 | val &= 0x1; |
1111 | if (val) { | |
1112 | for(i = 0; i < NB_PORTS; i++) | |
a0a3167a | 1113 | handle_port_owner_write(s, i, 0); |
94527ead GH |
1114 | } |
1115 | break; | |
1116 | ||
1117 | case PERIODICLISTBASE: | |
1118 | if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1119 | fprintf(stderr, | |
1120 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
1121 | " is enabled and HC is enabled\n"); | |
1122 | } | |
94527ead GH |
1123 | break; |
1124 | ||
1125 | case ASYNCLISTADDR: | |
1126 | if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1127 | fprintf(stderr, | |
1128 | "ehci: ASYNC list address register set while async schedule\n" | |
1129 | " is enabled and HC is enabled\n"); | |
1130 | } | |
94527ead GH |
1131 | break; |
1132 | } | |
1133 | ||
c4f8e211 GH |
1134 | *mmio = val; |
1135 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); | |
94527ead GH |
1136 | } |
1137 | ||
1138 | ||
1139 | // TODO : Put in common header file, duplication from usb-ohci.c | |
1140 | ||
1141 | /* Get an array of dwords from main memory */ | |
68d55358 DG |
1142 | static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1143 | uint32_t *buf, int num) | |
94527ead GH |
1144 | { |
1145 | int i; | |
1146 | ||
1147 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
4bf80119 | 1148 | pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf)); |
94527ead GH |
1149 | *buf = le32_to_cpu(*buf); |
1150 | } | |
1151 | ||
1152 | return 1; | |
1153 | } | |
1154 | ||
1155 | /* Put an array of dwords in to main memory */ | |
68d55358 DG |
1156 | static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1157 | uint32_t *buf, int num) | |
94527ead GH |
1158 | { |
1159 | int i; | |
1160 | ||
1161 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1162 | uint32_t tmp = cpu_to_le32(*buf); | |
4bf80119 | 1163 | pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp)); |
94527ead GH |
1164 | } |
1165 | ||
1166 | return 1; | |
1167 | } | |
1168 | ||
1169 | // 4.10.2 | |
1170 | ||
0122f472 | 1171 | static int ehci_qh_do_overlay(EHCIQueue *q) |
94527ead GH |
1172 | { |
1173 | int i; | |
1174 | int dtoggle; | |
1175 | int ping; | |
1176 | int eps; | |
1177 | int reload; | |
1178 | ||
1179 | // remember values in fields to preserve in qh after overlay | |
1180 | ||
0122f472 GH |
1181 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1182 | ping = q->qh.token & QTD_TOKEN_PING; | |
94527ead | 1183 | |
0122f472 GH |
1184 | q->qh.current_qtd = q->qtdaddr; |
1185 | q->qh.next_qtd = q->qtd.next; | |
1186 | q->qh.altnext_qtd = q->qtd.altnext; | |
1187 | q->qh.token = q->qtd.token; | |
94527ead GH |
1188 | |
1189 | ||
0122f472 | 1190 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
94527ead | 1191 | if (eps == EHCI_QH_EPS_HIGH) { |
0122f472 GH |
1192 | q->qh.token &= ~QTD_TOKEN_PING; |
1193 | q->qh.token |= ping; | |
94527ead GH |
1194 | } |
1195 | ||
0122f472 GH |
1196 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1197 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
94527ead GH |
1198 | |
1199 | for (i = 0; i < 5; i++) { | |
0122f472 | 1200 | q->qh.bufptr[i] = q->qtd.bufptr[i]; |
94527ead GH |
1201 | } |
1202 | ||
0122f472 | 1203 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { |
94527ead | 1204 | // preserve QH DT bit |
0122f472 GH |
1205 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1206 | q->qh.token |= dtoggle; | |
94527ead GH |
1207 | } |
1208 | ||
0122f472 GH |
1209 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; |
1210 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
94527ead | 1211 | |
68d55358 DG |
1212 | put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, |
1213 | sizeof(EHCIqh) >> 2); | |
94527ead GH |
1214 | |
1215 | return 0; | |
1216 | } | |
1217 | ||
0ce668bc | 1218 | static int ehci_init_transfer(EHCIQueue *q) |
94527ead | 1219 | { |
0ce668bc | 1220 | uint32_t cpage, offset, bytes, plen; |
68d55358 | 1221 | dma_addr_t page; |
94527ead | 1222 | |
0ce668bc GH |
1223 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); |
1224 | bytes = get_field(q->qh.token, QTD_TOKEN_TBYTES); | |
0122f472 | 1225 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; |
68d55358 | 1226 | pci_dma_sglist_init(&q->sgl, &q->ehci->dev, 5); |
94527ead | 1227 | |
0ce668bc GH |
1228 | while (bytes > 0) { |
1229 | if (cpage > 4) { | |
1230 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
1231 | return USB_RET_PROCERR; | |
1232 | } | |
94527ead | 1233 | |
0ce668bc GH |
1234 | page = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK; |
1235 | page += offset; | |
1236 | plen = bytes; | |
1237 | if (plen > 4096 - offset) { | |
1238 | plen = 4096 - offset; | |
1239 | offset = 0; | |
1240 | cpage++; | |
94527ead GH |
1241 | } |
1242 | ||
0ce668bc GH |
1243 | qemu_sglist_add(&q->sgl, page, plen); |
1244 | bytes -= plen; | |
1245 | } | |
1246 | return 0; | |
1247 | } | |
94527ead | 1248 | |
0ce668bc GH |
1249 | static void ehci_finish_transfer(EHCIQueue *q, int status) |
1250 | { | |
1251 | uint32_t cpage, offset; | |
94527ead | 1252 | |
0ce668bc | 1253 | qemu_sglist_destroy(&q->sgl); |
94527ead | 1254 | |
0ce668bc GH |
1255 | if (status > 0) { |
1256 | /* update cpage & offset */ | |
1257 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); | |
1258 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; | |
94527ead | 1259 | |
0ce668bc GH |
1260 | offset += status; |
1261 | cpage += offset >> QTD_BUFPTR_SH; | |
1262 | offset &= ~QTD_BUFPTR_MASK; | |
94527ead | 1263 | |
0ce668bc GH |
1264 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1265 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; | |
1266 | q->qh.bufptr[0] |= offset; | |
1267 | } | |
94527ead GH |
1268 | } |
1269 | ||
d47e59b8 | 1270 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
94527ead | 1271 | { |
a0a3167a HG |
1272 | EHCIQueue *q; |
1273 | EHCIState *s = port->opaque; | |
1274 | uint32_t portsc = s->portsc[port->index]; | |
1275 | ||
1276 | if (portsc & PORTSC_POWNER) { | |
1277 | USBPort *companion = s->companion_ports[port->index]; | |
1278 | companion->ops->complete(companion, packet); | |
1279 | return; | |
1280 | } | |
94527ead | 1281 | |
a0a3167a | 1282 | q = container_of(packet, EHCIQueue, packet); |
8ac6d699 GH |
1283 | trace_usb_ehci_queue_action(q, "wakeup"); |
1284 | assert(q->async == EHCI_ASYNC_INFLIGHT); | |
0122f472 | 1285 | q->async = EHCI_ASYNC_FINISHED; |
4f4321c1 | 1286 | q->usb_status = packet->result; |
94527ead GH |
1287 | } |
1288 | ||
0122f472 | 1289 | static void ehci_execute_complete(EHCIQueue *q) |
94527ead | 1290 | { |
8ac6d699 | 1291 | assert(q->async != EHCI_ASYNC_INFLIGHT); |
0122f472 | 1292 | q->async = EHCI_ASYNC_NONE; |
94527ead GH |
1293 | |
1294 | DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", | |
0122f472 | 1295 | q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
94527ead | 1296 | |
0122f472 | 1297 | if (q->usb_status < 0) { |
0122f472 | 1298 | switch(q->usb_status) { |
d61000a8 | 1299 | case USB_RET_IOERROR: |
94527ead | 1300 | case USB_RET_NODEV: |
d2bd525f | 1301 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
dd54cfe0 | 1302 | set_field(&q->qh.token, 0, QTD_TOKEN_CERR); |
d2bd525f | 1303 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1304 | break; |
1305 | case USB_RET_STALL: | |
0122f472 GH |
1306 | q->qh.token |= QTD_TOKEN_HALT; |
1307 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1308 | break; |
1309 | case USB_RET_NAK: | |
553a6a59 HG |
1310 | set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT); |
1311 | return; /* We're not done yet with this transaction */ | |
94527ead | 1312 | case USB_RET_BABBLE: |
d2bd525f | 1313 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
0122f472 | 1314 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1315 | break; |
1316 | default: | |
0122f472 GH |
1317 | /* should not be triggerable */ |
1318 | fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status); | |
1319 | assert(0); | |
94527ead GH |
1320 | break; |
1321 | } | |
dd54cfe0 HG |
1322 | } else if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) { |
1323 | q->usb_status = USB_RET_BABBLE; | |
1324 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); | |
1325 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead | 1326 | } else { |
94527ead GH |
1327 | // TODO check 4.12 for splits |
1328 | ||
0122f472 | 1329 | if (q->tbytes && q->pid == USB_TOKEN_IN) { |
0122f472 | 1330 | q->tbytes -= q->usb_status; |
94527ead | 1331 | } else { |
0122f472 | 1332 | q->tbytes = 0; |
94527ead GH |
1333 | } |
1334 | ||
0122f472 GH |
1335 | DPRINTF("updating tbytes to %d\n", q->tbytes); |
1336 | set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES); | |
94527ead | 1337 | } |
0ce668bc GH |
1338 | ehci_finish_transfer(q, q->usb_status); |
1339 | usb_packet_unmap(&q->packet); | |
94527ead | 1340 | |
0122f472 GH |
1341 | q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1342 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
94527ead | 1343 | |
553a6a59 | 1344 | if (q->qh.token & QTD_TOKEN_IOC) { |
0122f472 | 1345 | ehci_record_interrupt(q->ehci, USBSTS_INT); |
94527ead | 1346 | } |
94527ead GH |
1347 | } |
1348 | ||
1349 | // 4.10.3 | |
1350 | ||
0122f472 | 1351 | static int ehci_execute(EHCIQueue *q) |
94527ead | 1352 | { |
94527ead | 1353 | USBDevice *dev; |
079d0b7f | 1354 | USBEndpoint *ep; |
94527ead | 1355 | int ret; |
94527ead GH |
1356 | int endp; |
1357 | int devadr; | |
1358 | ||
0122f472 | 1359 | if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) { |
94527ead GH |
1360 | fprintf(stderr, "Attempting to execute inactive QH\n"); |
1361 | return USB_RET_PROCERR; | |
1362 | } | |
1363 | ||
0122f472 GH |
1364 | q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; |
1365 | if (q->tbytes > BUFF_SIZE) { | |
94527ead GH |
1366 | fprintf(stderr, "Request for more bytes than allowed\n"); |
1367 | return USB_RET_PROCERR; | |
1368 | } | |
1369 | ||
0122f472 GH |
1370 | q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
1371 | switch(q->pid) { | |
1372 | case 0: q->pid = USB_TOKEN_OUT; break; | |
1373 | case 1: q->pid = USB_TOKEN_IN; break; | |
1374 | case 2: q->pid = USB_TOKEN_SETUP; break; | |
94527ead GH |
1375 | default: fprintf(stderr, "bad token\n"); break; |
1376 | } | |
1377 | ||
0ce668bc | 1378 | if (ehci_init_transfer(q) != 0) { |
94527ead GH |
1379 | return USB_RET_PROCERR; |
1380 | } | |
1381 | ||
0122f472 GH |
1382 | endp = get_field(q->qh.epchar, QH_EPCHAR_EP); |
1383 | devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); | |
94527ead | 1384 | |
079d0b7f GH |
1385 | /* TODO: associating device with ehci port */ |
1386 | dev = ehci_find_device(q->ehci, devadr); | |
1387 | ep = usb_ep_get(dev, q->pid, endp); | |
94527ead | 1388 | |
079d0b7f | 1389 | usb_packet_setup(&q->packet, q->pid, ep); |
0ce668bc GH |
1390 | usb_packet_map(&q->packet, &q->sgl); |
1391 | ||
828143c6 GH |
1392 | ret = usb_handle_packet(dev, &q->packet); |
1393 | DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd " | |
1394 | "(total %d) endp %x ret %d\n", | |
1395 | q->qhaddr, q->qh.next, q->qtdaddr, q->pid, | |
1396 | q->packet.iov.size, q->tbytes, endp, ret); | |
94527ead GH |
1397 | |
1398 | if (ret > BUFF_SIZE) { | |
1399 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); | |
1400 | return USB_RET_PROCERR; | |
1401 | } | |
1402 | ||
94527ead GH |
1403 | return ret; |
1404 | } | |
1405 | ||
1406 | /* 4.7.2 | |
1407 | */ | |
1408 | ||
1409 | static int ehci_process_itd(EHCIState *ehci, | |
1410 | EHCIitd *itd) | |
1411 | { | |
94527ead | 1412 | USBDevice *dev; |
079d0b7f | 1413 | USBEndpoint *ep; |
94527ead | 1414 | int ret; |
828143c6 | 1415 | uint32_t i, len, pid, dir, devaddr, endp; |
e654887f | 1416 | uint32_t pg, off, ptr1, ptr2, max, mult; |
94527ead GH |
1417 | |
1418 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); | |
e654887f | 1419 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); |
94527ead | 1420 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); |
e654887f GH |
1421 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); |
1422 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
94527ead GH |
1423 | |
1424 | for(i = 0; i < 8; i++) { | |
1425 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
e654887f GH |
1426 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1427 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1428 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1429 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1430 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1431 | ||
1432 | if (len > max * mult) { | |
1433 | len = max * mult; | |
1434 | } | |
94527ead GH |
1435 | |
1436 | if (len > BUFF_SIZE) { | |
1437 | return USB_RET_PROCERR; | |
1438 | } | |
1439 | ||
68d55358 | 1440 | pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); |
e654887f GH |
1441 | if (off + len > 4096) { |
1442 | /* transfer crosses page border */ | |
0ce668bc GH |
1443 | uint32_t len2 = off + len - 4096; |
1444 | uint32_t len1 = len - len2; | |
1445 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); | |
1446 | qemu_sglist_add(&ehci->isgl, ptr2, len2); | |
e654887f | 1447 | } else { |
0ce668bc | 1448 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
e654887f | 1449 | } |
94527ead | 1450 | |
0ce668bc | 1451 | pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
94527ead | 1452 | |
079d0b7f GH |
1453 | dev = ehci_find_device(ehci, devaddr); |
1454 | ep = usb_ep_get(dev, pid, endp); | |
aa0568ff GH |
1455 | if (ep->type == USB_ENDPOINT_XFER_ISOC) { |
1456 | usb_packet_setup(&ehci->ipacket, pid, ep); | |
1457 | usb_packet_map(&ehci->ipacket, &ehci->isgl); | |
1458 | ret = usb_handle_packet(dev, &ehci->ipacket); | |
1459 | assert(ret != USB_RET_ASYNC); | |
1460 | usb_packet_unmap(&ehci->ipacket); | |
1461 | } else { | |
1462 | DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); | |
1463 | ret = USB_RET_NAK; | |
1464 | } | |
0ce668bc GH |
1465 | qemu_sglist_destroy(&ehci->isgl); |
1466 | ||
5eafd438 | 1467 | if (ret < 0) { |
df787185 HG |
1468 | switch (ret) { |
1469 | default: | |
1470 | fprintf(stderr, "Unexpected iso usb result: %d\n", ret); | |
1471 | /* Fall through */ | |
d61000a8 | 1472 | case USB_RET_IOERROR: |
df787185 HG |
1473 | case USB_RET_NODEV: |
1474 | /* 3.3.2: XACTERR is only allowed on IN transactions */ | |
1475 | if (dir) { | |
1476 | itd->transact[i] |= ITD_XACT_XACTERR; | |
1477 | ehci_record_interrupt(ehci, USBSTS_ERRINT); | |
1478 | } | |
1479 | break; | |
1480 | case USB_RET_BABBLE: | |
1481 | itd->transact[i] |= ITD_XACT_BABBLE; | |
1482 | ehci_record_interrupt(ehci, USBSTS_ERRINT); | |
1483 | break; | |
5eafd438 HG |
1484 | case USB_RET_NAK: |
1485 | /* no data for us, so do a zero-length transfer */ | |
1486 | ret = 0; | |
1487 | break; | |
1488 | } | |
1489 | } | |
1490 | if (ret >= 0) { | |
1491 | if (!dir) { | |
1492 | /* OUT */ | |
1493 | set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); | |
1494 | } else { | |
1495 | /* IN */ | |
1496 | set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); | |
94527ead GH |
1497 | } |
1498 | } | |
df787185 HG |
1499 | if (itd->transact[i] & ITD_XACT_IOC) { |
1500 | ehci_record_interrupt(ehci, USBSTS_INT); | |
1501 | } | |
e654887f | 1502 | itd->transact[i] &= ~ITD_XACT_ACTIVE; |
94527ead GH |
1503 | } |
1504 | } | |
1505 | return 0; | |
1506 | } | |
1507 | ||
1508 | /* This state is the entry point for asynchronous schedule | |
1509 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1510 | */ | |
26d53979 | 1511 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
94527ead | 1512 | { |
0122f472 | 1513 | EHCIqh qh; |
94527ead GH |
1514 | int i = 0; |
1515 | int again = 0; | |
1516 | uint32_t entry = ehci->asynclistaddr; | |
1517 | ||
1518 | /* set reclamation flag at start event (4.8.6) */ | |
1519 | if (async) { | |
439a97cc | 1520 | ehci_set_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1521 | } |
1522 | ||
4be23939 | 1523 | ehci_queues_rip_unused(ehci, async, 0); |
8ac6d699 | 1524 | |
94527ead GH |
1525 | /* Find the head of the list (4.9.1.1) */ |
1526 | for(i = 0; i < MAX_QH; i++) { | |
68d55358 DG |
1527 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1528 | sizeof(EHCIqh) >> 2); | |
8ac6d699 | 1529 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); |
94527ead | 1530 | |
0122f472 | 1531 | if (qh.epchar & QH_EPCHAR_H) { |
94527ead GH |
1532 | if (async) { |
1533 | entry |= (NLPTR_TYPE_QH << 1); | |
1534 | } | |
1535 | ||
0122f472 | 1536 | ehci_set_fetch_addr(ehci, async, entry); |
26d53979 | 1537 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1538 | again = 1; |
1539 | goto out; | |
1540 | } | |
1541 | ||
0122f472 | 1542 | entry = qh.next; |
94527ead | 1543 | if (entry == ehci->asynclistaddr) { |
94527ead GH |
1544 | break; |
1545 | } | |
1546 | } | |
1547 | ||
1548 | /* no head found for list. */ | |
1549 | ||
26d53979 | 1550 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1551 | |
1552 | out: | |
1553 | return again; | |
1554 | } | |
1555 | ||
1556 | ||
1557 | /* This state is the entry point for periodic schedule processing as | |
1558 | * well as being a continuation state for async processing. | |
1559 | */ | |
26d53979 | 1560 | static int ehci_state_fetchentry(EHCIState *ehci, int async) |
94527ead GH |
1561 | { |
1562 | int again = 0; | |
0122f472 | 1563 | uint32_t entry = ehci_get_fetch_addr(ehci, async); |
94527ead | 1564 | |
2a5ff735 | 1565 | if (NLPTR_TBIT(entry)) { |
26d53979 | 1566 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1567 | goto out; |
1568 | } | |
1569 | ||
1570 | /* section 4.8, only QH in async schedule */ | |
1571 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1572 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1573 | return -1; | |
1574 | } | |
1575 | ||
1576 | switch (NLPTR_TYPE_GET(entry)) { | |
1577 | case NLPTR_TYPE_QH: | |
26d53979 | 1578 | ehci_set_state(ehci, async, EST_FETCHQH); |
94527ead GH |
1579 | again = 1; |
1580 | break; | |
1581 | ||
1582 | case NLPTR_TYPE_ITD: | |
26d53979 | 1583 | ehci_set_state(ehci, async, EST_FETCHITD); |
94527ead GH |
1584 | again = 1; |
1585 | break; | |
1586 | ||
2fe80192 GH |
1587 | case NLPTR_TYPE_STITD: |
1588 | ehci_set_state(ehci, async, EST_FETCHSITD); | |
1589 | again = 1; | |
1590 | break; | |
1591 | ||
94527ead | 1592 | default: |
2fe80192 | 1593 | /* TODO: handle FSTN type */ |
94527ead GH |
1594 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " |
1595 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1596 | return -1; | |
1597 | } | |
1598 | ||
1599 | out: | |
1600 | return again; | |
1601 | } | |
1602 | ||
0122f472 | 1603 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
94527ead | 1604 | { |
0122f472 GH |
1605 | uint32_t entry; |
1606 | EHCIQueue *q; | |
94527ead | 1607 | |
0122f472 | 1608 | entry = ehci_get_fetch_addr(ehci, async); |
df5d5c5c | 1609 | q = ehci_find_queue_by_qh(ehci, entry, async); |
8ac6d699 GH |
1610 | if (NULL == q) { |
1611 | q = ehci_alloc_queue(ehci, async); | |
1612 | } | |
0122f472 | 1613 | q->qhaddr = entry; |
8ac6d699 GH |
1614 | q->seen++; |
1615 | ||
1616 | if (q->seen > 1) { | |
1617 | /* we are going in circles -- stop processing */ | |
1618 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1619 | q = NULL; | |
1620 | goto out; | |
1621 | } | |
94527ead | 1622 | |
68d55358 DG |
1623 | get_dwords(ehci, NLPTR_GET(q->qhaddr), |
1624 | (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); | |
8ac6d699 GH |
1625 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); |
1626 | ||
1627 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
1628 | /* I/O still in progress -- skip queue */ | |
1629 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1630 | goto out; | |
1631 | } | |
1632 | if (q->async == EHCI_ASYNC_FINISHED) { | |
1633 | /* I/O finished -- continue processing queue */ | |
1634 | trace_usb_ehci_queue_action(q, "resume"); | |
1635 | ehci_set_state(ehci, async, EST_EXECUTING); | |
1636 | goto out; | |
1637 | } | |
0122f472 GH |
1638 | |
1639 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
94527ead GH |
1640 | |
1641 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1642 | if (ehci->usbsts & USBSTS_REC) { | |
439a97cc | 1643 | ehci_clear_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1644 | } else { |
1645 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
0122f472 | 1646 | " - done processing\n", q->qhaddr); |
26d53979 | 1647 | ehci_set_state(ehci, async, EST_ACTIVE); |
0122f472 | 1648 | q = NULL; |
94527ead GH |
1649 | goto out; |
1650 | } | |
1651 | } | |
1652 | ||
1653 | #if EHCI_DEBUG | |
0122f472 | 1654 | if (q->qhaddr != q->qh.next) { |
94527ead | 1655 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", |
0122f472 GH |
1656 | q->qhaddr, |
1657 | q->qh.epchar & QH_EPCHAR_H, | |
1658 | q->qh.token & QTD_TOKEN_HALT, | |
1659 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1660 | q->qh.next); | |
94527ead GH |
1661 | } |
1662 | #endif | |
1663 | ||
0122f472 | 1664 | if (q->qh.token & QTD_TOKEN_HALT) { |
26d53979 | 1665 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead | 1666 | |
2a5ff735 HG |
1667 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && |
1668 | (NLPTR_TBIT(q->qh.current_qtd) == 0)) { | |
0122f472 | 1669 | q->qtdaddr = q->qh.current_qtd; |
26d53979 | 1670 | ehci_set_state(ehci, async, EST_FETCHQTD); |
94527ead GH |
1671 | |
1672 | } else { | |
1673 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
26d53979 | 1674 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
94527ead GH |
1675 | } |
1676 | ||
1677 | out: | |
0122f472 | 1678 | return q; |
94527ead GH |
1679 | } |
1680 | ||
26d53979 | 1681 | static int ehci_state_fetchitd(EHCIState *ehci, int async) |
94527ead | 1682 | { |
0122f472 | 1683 | uint32_t entry; |
94527ead GH |
1684 | EHCIitd itd; |
1685 | ||
0122f472 GH |
1686 | assert(!async); |
1687 | entry = ehci_get_fetch_addr(ehci, async); | |
1688 | ||
68d55358 | 1689 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
94527ead | 1690 | sizeof(EHCIitd) >> 2); |
0122f472 | 1691 | ehci_trace_itd(ehci, entry, &itd); |
94527ead GH |
1692 | |
1693 | if (ehci_process_itd(ehci, &itd) != 0) { | |
1694 | return -1; | |
1695 | } | |
1696 | ||
68d55358 DG |
1697 | put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1698 | sizeof(EHCIitd) >> 2); | |
0122f472 | 1699 | ehci_set_fetch_addr(ehci, async, itd.next); |
26d53979 | 1700 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1701 | |
1702 | return 1; | |
1703 | } | |
1704 | ||
2fe80192 GH |
1705 | static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1706 | { | |
1707 | uint32_t entry; | |
1708 | EHCIsitd sitd; | |
1709 | ||
1710 | assert(!async); | |
1711 | entry = ehci_get_fetch_addr(ehci, async); | |
1712 | ||
68d55358 | 1713 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
2fe80192 GH |
1714 | sizeof(EHCIsitd) >> 2); |
1715 | ehci_trace_sitd(ehci, entry, &sitd); | |
1716 | ||
1717 | if (!(sitd.results & SITD_RESULTS_ACTIVE)) { | |
1718 | /* siTD is not active, nothing to do */; | |
1719 | } else { | |
1720 | /* TODO: split transfers are not implemented */ | |
1721 | fprintf(stderr, "WARNING: Skipping active siTD\n"); | |
1722 | } | |
1723 | ||
1724 | ehci_set_fetch_addr(ehci, async, sitd.next); | |
1725 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
1726 | return 1; | |
1727 | } | |
1728 | ||
94527ead | 1729 | /* Section 4.10.2 - paragraph 3 */ |
0122f472 | 1730 | static int ehci_state_advqueue(EHCIQueue *q, int async) |
94527ead GH |
1731 | { |
1732 | #if 0 | |
1733 | /* TO-DO: 4.10.2 - paragraph 2 | |
1734 | * if I-bit is set to 1 and QH is not active | |
1735 | * go to horizontal QH | |
1736 | */ | |
1737 | if (I-bit set) { | |
26d53979 | 1738 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1739 | goto out; |
1740 | } | |
1741 | #endif | |
1742 | ||
1743 | /* | |
1744 | * want data and alt-next qTD is valid | |
1745 | */ | |
0122f472 | 1746 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
0122f472 GH |
1747 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { |
1748 | q->qtdaddr = q->qh.altnext_qtd; | |
1749 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1750 | |
1751 | /* | |
1752 | * next qTD is valid | |
1753 | */ | |
2a5ff735 | 1754 | } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { |
0122f472 GH |
1755 | q->qtdaddr = q->qh.next_qtd; |
1756 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1757 | |
1758 | /* | |
1759 | * no valid qTD, try next QH | |
1760 | */ | |
1761 | } else { | |
0122f472 | 1762 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1763 | } |
1764 | ||
1765 | return 1; | |
1766 | } | |
1767 | ||
1768 | /* Section 4.10.2 - paragraph 4 */ | |
0122f472 | 1769 | static int ehci_state_fetchqtd(EHCIQueue *q, int async) |
94527ead | 1770 | { |
94527ead GH |
1771 | int again = 0; |
1772 | ||
68d55358 DG |
1773 | get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qtd, |
1774 | sizeof(EHCIqtd) >> 2); | |
8ac6d699 | 1775 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd); |
94527ead | 1776 | |
0122f472 GH |
1777 | if (q->qtd.token & QTD_TOKEN_ACTIVE) { |
1778 | ehci_set_state(q->ehci, async, EST_EXECUTE); | |
94527ead GH |
1779 | again = 1; |
1780 | } else { | |
0122f472 | 1781 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1782 | again = 1; |
1783 | } | |
1784 | ||
1785 | return again; | |
1786 | } | |
1787 | ||
0122f472 | 1788 | static int ehci_state_horizqh(EHCIQueue *q, int async) |
94527ead GH |
1789 | { |
1790 | int again = 0; | |
1791 | ||
0122f472 GH |
1792 | if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) { |
1793 | ehci_set_fetch_addr(q->ehci, async, q->qh.next); | |
1794 | ehci_set_state(q->ehci, async, EST_FETCHENTRY); | |
94527ead GH |
1795 | again = 1; |
1796 | } else { | |
0122f472 | 1797 | ehci_set_state(q->ehci, async, EST_ACTIVE); |
94527ead GH |
1798 | } |
1799 | ||
1800 | return again; | |
1801 | } | |
1802 | ||
8ac6d699 GH |
1803 | /* |
1804 | * Write the qh back to guest physical memory. This step isn't | |
1805 | * in the EHCI spec but we need to do it since we don't share | |
1806 | * physical memory with our guest VM. | |
1807 | * | |
1808 | * The first three dwords are read-only for the EHCI, so skip them | |
1809 | * when writing back the qh. | |
1810 | */ | |
1811 | static void ehci_flush_qh(EHCIQueue *q) | |
1812 | { | |
1813 | uint32_t *qh = (uint32_t *) &q->qh; | |
1814 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1815 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1816 | ||
68d55358 | 1817 | put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); |
8ac6d699 GH |
1818 | } |
1819 | ||
0122f472 | 1820 | static int ehci_state_execute(EHCIQueue *q, int async) |
94527ead | 1821 | { |
94527ead | 1822 | int again = 0; |
94527ead | 1823 | |
0122f472 | 1824 | if (ehci_qh_do_overlay(q) != 0) { |
94527ead GH |
1825 | return -1; |
1826 | } | |
1827 | ||
94527ead GH |
1828 | // TODO verify enough time remains in the uframe as in 4.4.1.1 |
1829 | // TODO write back ptr to async list when done or out of time | |
1830 | // TODO Windows does not seem to ever set the MULT field | |
1831 | ||
1832 | if (!async) { | |
0122f472 | 1833 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1834 | if (!transactCtr) { |
0122f472 | 1835 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1836 | again = 1; |
1837 | goto out; | |
1838 | } | |
1839 | } | |
1840 | ||
1841 | if (async) { | |
0122f472 | 1842 | ehci_set_usbsts(q->ehci, USBSTS_REC); |
94527ead GH |
1843 | } |
1844 | ||
0122f472 GH |
1845 | q->usb_status = ehci_execute(q); |
1846 | if (q->usb_status == USB_RET_PROCERR) { | |
94527ead GH |
1847 | again = -1; |
1848 | goto out; | |
1849 | } | |
8ac6d699 GH |
1850 | if (q->usb_status == USB_RET_ASYNC) { |
1851 | ehci_flush_qh(q); | |
1852 | trace_usb_ehci_queue_action(q, "suspend"); | |
1853 | q->async = EHCI_ASYNC_INFLIGHT; | |
1854 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
94527ead | 1855 | again = 1; |
8ac6d699 | 1856 | goto out; |
94527ead GH |
1857 | } |
1858 | ||
8ac6d699 GH |
1859 | ehci_set_state(q->ehci, async, EST_EXECUTING); |
1860 | again = 1; | |
1861 | ||
94527ead GH |
1862 | out: |
1863 | return again; | |
1864 | } | |
1865 | ||
0122f472 | 1866 | static int ehci_state_executing(EHCIQueue *q, int async) |
94527ead | 1867 | { |
94527ead | 1868 | int again = 0; |
94527ead | 1869 | |
0122f472 GH |
1870 | ehci_execute_complete(q); |
1871 | if (q->usb_status == USB_RET_ASYNC) { | |
94527ead GH |
1872 | goto out; |
1873 | } | |
0122f472 | 1874 | if (q->usb_status == USB_RET_PROCERR) { |
94527ead GH |
1875 | again = -1; |
1876 | goto out; | |
1877 | } | |
1878 | ||
1879 | // 4.10.3 | |
1880 | if (!async) { | |
0122f472 | 1881 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1882 | transactCtr--; |
0122f472 | 1883 | set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); |
94527ead GH |
1884 | // 4.10.3, bottom of page 82, should exit this state when transaction |
1885 | // counter decrements to 0 | |
1886 | } | |
1887 | ||
94527ead | 1888 | /* 4.10.5 */ |
553a6a59 | 1889 | if (q->usb_status == USB_RET_NAK) { |
0122f472 | 1890 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead | 1891 | } else { |
0122f472 | 1892 | ehci_set_state(q->ehci, async, EST_WRITEBACK); |
94527ead GH |
1893 | } |
1894 | ||
1895 | again = 1; | |
1896 | ||
1897 | out: | |
8ac6d699 | 1898 | ehci_flush_qh(q); |
94527ead GH |
1899 | return again; |
1900 | } | |
1901 | ||
1902 | ||
0122f472 | 1903 | static int ehci_state_writeback(EHCIQueue *q, int async) |
94527ead | 1904 | { |
94527ead GH |
1905 | int again = 0; |
1906 | ||
1907 | /* Write back the QTD from the QH area */ | |
8ac6d699 | 1908 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd); |
68d55358 DG |
1909 | put_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qh.next_qtd, |
1910 | sizeof(EHCIqtd) >> 2); | |
94527ead | 1911 | |
d2bd525f GH |
1912 | /* |
1913 | * EHCI specs say go horizontal here. | |
1914 | * | |
1915 | * We can also advance the queue here for performance reasons. We | |
1916 | * need to take care to only take that shortcut in case we've | |
1917 | * processed the qtd just written back without errors, i.e. halt | |
1918 | * bit is clear. | |
94527ead | 1919 | */ |
d2bd525f GH |
1920 | if (q->qh.token & QTD_TOKEN_HALT) { |
1921 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1922 | again = 1; | |
1923 | } else { | |
0122f472 | 1924 | ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE); |
94527ead | 1925 | again = 1; |
d2bd525f | 1926 | } |
94527ead GH |
1927 | return again; |
1928 | } | |
1929 | ||
1930 | /* | |
1931 | * This is the state machine that is common to both async and periodic | |
1932 | */ | |
1933 | ||
26d53979 GH |
1934 | static void ehci_advance_state(EHCIState *ehci, |
1935 | int async) | |
94527ead | 1936 | { |
0122f472 | 1937 | EHCIQueue *q = NULL; |
94527ead GH |
1938 | int again; |
1939 | int iter = 0; | |
1940 | ||
1941 | do { | |
26d53979 | 1942 | if (ehci_get_state(ehci, async) == EST_FETCHQH) { |
94527ead GH |
1943 | iter++; |
1944 | /* if we are roaming a lot of QH without executing a qTD | |
1945 | * something is wrong with the linked list. TO-DO: why is | |
1946 | * this hack needed? | |
1947 | */ | |
8ac6d699 GH |
1948 | assert(iter < MAX_ITERATIONS); |
1949 | #if 0 | |
94527ead GH |
1950 | if (iter > MAX_ITERATIONS) { |
1951 | DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n"); | |
26d53979 | 1952 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1953 | break; |
1954 | } | |
8ac6d699 | 1955 | #endif |
94527ead | 1956 | } |
26d53979 | 1957 | switch(ehci_get_state(ehci, async)) { |
94527ead | 1958 | case EST_WAITLISTHEAD: |
26d53979 | 1959 | again = ehci_state_waitlisthead(ehci, async); |
94527ead GH |
1960 | break; |
1961 | ||
1962 | case EST_FETCHENTRY: | |
26d53979 | 1963 | again = ehci_state_fetchentry(ehci, async); |
94527ead GH |
1964 | break; |
1965 | ||
1966 | case EST_FETCHQH: | |
0122f472 GH |
1967 | q = ehci_state_fetchqh(ehci, async); |
1968 | again = q ? 1 : 0; | |
94527ead GH |
1969 | break; |
1970 | ||
1971 | case EST_FETCHITD: | |
26d53979 | 1972 | again = ehci_state_fetchitd(ehci, async); |
94527ead GH |
1973 | break; |
1974 | ||
2fe80192 GH |
1975 | case EST_FETCHSITD: |
1976 | again = ehci_state_fetchsitd(ehci, async); | |
1977 | break; | |
1978 | ||
94527ead | 1979 | case EST_ADVANCEQUEUE: |
0122f472 | 1980 | again = ehci_state_advqueue(q, async); |
94527ead GH |
1981 | break; |
1982 | ||
1983 | case EST_FETCHQTD: | |
0122f472 | 1984 | again = ehci_state_fetchqtd(q, async); |
94527ead GH |
1985 | break; |
1986 | ||
1987 | case EST_HORIZONTALQH: | |
0122f472 | 1988 | again = ehci_state_horizqh(q, async); |
94527ead GH |
1989 | break; |
1990 | ||
1991 | case EST_EXECUTE: | |
1992 | iter = 0; | |
0122f472 | 1993 | again = ehci_state_execute(q, async); |
94527ead GH |
1994 | break; |
1995 | ||
1996 | case EST_EXECUTING: | |
8ac6d699 | 1997 | assert(q != NULL); |
0122f472 | 1998 | again = ehci_state_executing(q, async); |
94527ead GH |
1999 | break; |
2000 | ||
2001 | case EST_WRITEBACK: | |
b2467216 | 2002 | assert(q != NULL); |
0122f472 | 2003 | again = ehci_state_writeback(q, async); |
94527ead GH |
2004 | break; |
2005 | ||
2006 | default: | |
2007 | fprintf(stderr, "Bad state!\n"); | |
2008 | again = -1; | |
8ac6d699 | 2009 | assert(0); |
94527ead GH |
2010 | break; |
2011 | } | |
2012 | ||
2013 | if (again < 0) { | |
2014 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
2015 | ehci_reset(ehci); | |
2016 | again = 0; | |
8ac6d699 | 2017 | assert(0); |
94527ead GH |
2018 | } |
2019 | } | |
2020 | while (again); | |
2021 | ||
2022 | ehci_commit_interrupt(ehci); | |
94527ead GH |
2023 | } |
2024 | ||
2025 | static void ehci_advance_async_state(EHCIState *ehci) | |
2026 | { | |
df5d5c5c | 2027 | const int async = 1; |
94527ead | 2028 | |
26d53979 | 2029 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2030 | case EST_INACTIVE: |
2031 | if (!(ehci->usbcmd & USBCMD_ASE)) { | |
2032 | break; | |
2033 | } | |
439a97cc | 2034 | ehci_set_usbsts(ehci, USBSTS_ASS); |
26d53979 | 2035 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2036 | // No break, fall through to ACTIVE |
2037 | ||
2038 | case EST_ACTIVE: | |
2039 | if ( !(ehci->usbcmd & USBCMD_ASE)) { | |
e850c2b4 | 2040 | ehci_queues_rip_all(ehci, async); |
439a97cc | 2041 | ehci_clear_usbsts(ehci, USBSTS_ASS); |
26d53979 | 2042 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2043 | break; |
2044 | } | |
2045 | ||
4be23939 | 2046 | /* make sure guest has acknowledged the doorbell interrupt */ |
94527ead GH |
2047 | /* TO-DO: is this really needed? */ |
2048 | if (ehci->usbsts & USBSTS_IAA) { | |
2049 | DPRINTF("IAA status bit still set.\n"); | |
2050 | break; | |
2051 | } | |
2052 | ||
94527ead GH |
2053 | /* check that address register has been set */ |
2054 | if (ehci->asynclistaddr == 0) { | |
2055 | break; | |
2056 | } | |
2057 | ||
26d53979 | 2058 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
26d53979 | 2059 | ehci_advance_state(ehci, async); |
4be23939 HG |
2060 | |
2061 | /* If the doorbell is set, the guest wants to make a change to the | |
2062 | * schedule. The host controller needs to release cached data. | |
2063 | * (section 4.8.2) | |
2064 | */ | |
2065 | if (ehci->usbcmd & USBCMD_IAAD) { | |
2066 | /* Remove all unseen qhs from the async qhs queue */ | |
2067 | ehci_queues_rip_unused(ehci, async, 1); | |
2068 | DPRINTF("ASYNC: doorbell request acknowledged\n"); | |
2069 | ehci->usbcmd &= ~USBCMD_IAAD; | |
2070 | ehci_set_interrupt(ehci, USBSTS_IAA); | |
2071 | } | |
94527ead GH |
2072 | break; |
2073 | ||
2074 | default: | |
2075 | /* this should only be due to a developer mistake */ | |
2076 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
2077 | "Resetting to active\n", ehci->astate); | |
0122f472 | 2078 | assert(0); |
94527ead GH |
2079 | } |
2080 | } | |
2081 | ||
2082 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
2083 | { | |
2084 | uint32_t entry; | |
2085 | uint32_t list; | |
df5d5c5c | 2086 | const int async = 0; |
94527ead GH |
2087 | |
2088 | // 4.6 | |
2089 | ||
26d53979 | 2090 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2091 | case EST_INACTIVE: |
2092 | if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2093 | ehci_set_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2094 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2095 | // No break, fall through to ACTIVE |
2096 | } else | |
2097 | break; | |
2098 | ||
2099 | case EST_ACTIVE: | |
2100 | if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) { | |
e850c2b4 | 2101 | ehci_queues_rip_all(ehci, async); |
439a97cc | 2102 | ehci_clear_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2103 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2104 | break; |
2105 | } | |
2106 | ||
2107 | list = ehci->periodiclistbase & 0xfffff000; | |
2108 | /* check that register has been set */ | |
2109 | if (list == 0) { | |
2110 | break; | |
2111 | } | |
2112 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2113 | ||
4bf80119 | 2114 | pci_dma_read(&ehci->dev, list, &entry, sizeof entry); |
94527ead GH |
2115 | entry = le32_to_cpu(entry); |
2116 | ||
2117 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2118 | ehci->frindex / 8, list, entry); | |
0122f472 | 2119 | ehci_set_fetch_addr(ehci, async,entry); |
26d53979 GH |
2120 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
2121 | ehci_advance_state(ehci, async); | |
4be23939 | 2122 | ehci_queues_rip_unused(ehci, async, 0); |
94527ead GH |
2123 | break; |
2124 | ||
94527ead GH |
2125 | default: |
2126 | /* this should only be due to a developer mistake */ | |
2127 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2128 | "Resetting to active\n", ehci->pstate); | |
0122f472 | 2129 | assert(0); |
94527ead GH |
2130 | } |
2131 | } | |
2132 | ||
2133 | static void ehci_frame_timer(void *opaque) | |
2134 | { | |
2135 | EHCIState *ehci = opaque; | |
2136 | int64_t expire_time, t_now; | |
adddecb1 | 2137 | uint64_t ns_elapsed; |
94527ead | 2138 | int frames; |
94527ead GH |
2139 | int i; |
2140 | int skipped_frames = 0; | |
2141 | ||
94527ead | 2142 | t_now = qemu_get_clock_ns(vm_clock); |
16a2dee6 | 2143 | expire_time = t_now + (get_ticks_per_sec() / ehci->freq); |
94527ead | 2144 | |
adddecb1 GH |
2145 | ns_elapsed = t_now - ehci->last_run_ns; |
2146 | frames = ns_elapsed / FRAME_TIMER_NS; | |
94527ead GH |
2147 | |
2148 | for (i = 0; i < frames; i++) { | |
2149 | if ( !(ehci->usbsts & USBSTS_HALT)) { | |
fcb70eca | 2150 | ehci->frindex += 8; |
94527ead | 2151 | |
58ea88d8 | 2152 | if (ehci->frindex == 0x00002000) { |
94527ead GH |
2153 | ehci_set_interrupt(ehci, USBSTS_FLR); |
2154 | } | |
2155 | ||
58ea88d8 HG |
2156 | if (ehci->frindex == 0x00004000) { |
2157 | ehci_set_interrupt(ehci, USBSTS_FLR); | |
2158 | ehci->frindex = 0; | |
2159 | } | |
2160 | ||
94527ead GH |
2161 | ehci->sofv = (ehci->frindex - 1) >> 3; |
2162 | ehci->sofv &= 0x000003ff; | |
2163 | } | |
2164 | ||
16a2dee6 | 2165 | if (frames - i > ehci->maxframes) { |
94527ead GH |
2166 | skipped_frames++; |
2167 | } else { | |
d0539307 | 2168 | ehci_advance_periodic_state(ehci); |
94527ead GH |
2169 | } |
2170 | ||
adddecb1 | 2171 | ehci->last_run_ns += FRAME_TIMER_NS; |
94527ead GH |
2172 | } |
2173 | ||
2174 | #if 0 | |
2175 | if (skipped_frames) { | |
2176 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2177 | } | |
2178 | #endif | |
2179 | ||
2180 | /* Async is not inside loop since it executes everything it can once | |
2181 | * called | |
2182 | */ | |
d0539307 | 2183 | ehci_advance_async_state(ehci); |
94527ead GH |
2184 | |
2185 | qemu_mod_timer(ehci->frame_timer, expire_time); | |
2186 | } | |
2187 | ||
94527ead | 2188 | |
e57964f5 AK |
2189 | static const MemoryRegionOps ehci_mem_ops = { |
2190 | .old_mmio = { | |
2191 | .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl }, | |
2192 | .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel }, | |
2193 | }, | |
2194 | .endianness = DEVICE_LITTLE_ENDIAN, | |
94527ead GH |
2195 | }; |
2196 | ||
94527ead GH |
2197 | static int usb_ehci_initfn(PCIDevice *dev); |
2198 | ||
2199 | static USBPortOps ehci_port_ops = { | |
2200 | .attach = ehci_attach, | |
2201 | .detach = ehci_detach, | |
4706ab6c | 2202 | .child_detach = ehci_child_detach, |
a0a3167a | 2203 | .wakeup = ehci_wakeup, |
94527ead GH |
2204 | .complete = ehci_async_complete_packet, |
2205 | }; | |
2206 | ||
07771f6f | 2207 | static USBBusOps ehci_bus_ops = { |
a0a3167a | 2208 | .register_companion = ehci_register_companion, |
07771f6f GH |
2209 | }; |
2210 | ||
9490fb06 GH |
2211 | static const VMStateDescription vmstate_ehci = { |
2212 | .name = "ehci", | |
2213 | .unmigratable = 1, | |
2214 | }; | |
2215 | ||
3028376e GH |
2216 | static Property ehci_properties[] = { |
2217 | DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ), | |
2218 | DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), | |
2219 | DEFINE_PROP_END_OF_LIST(), | |
2220 | }; | |
2221 | ||
40021f08 AL |
2222 | static void ehci_class_init(ObjectClass *klass, void *data) |
2223 | { | |
39bffca2 | 2224 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2225 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2226 | ||
2227 | k->init = usb_ehci_initfn; | |
2228 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2229 | k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ | |
2230 | k->revision = 0x10; | |
2231 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2232 | dc->vmsd = &vmstate_ehci; |
2233 | dc->props = ehci_properties; | |
40021f08 AL |
2234 | } |
2235 | ||
39bffca2 AL |
2236 | static TypeInfo ehci_info = { |
2237 | .name = "usb-ehci", | |
2238 | .parent = TYPE_PCI_DEVICE, | |
2239 | .instance_size = sizeof(EHCIState), | |
2240 | .class_init = ehci_class_init, | |
e855761c AL |
2241 | }; |
2242 | ||
40021f08 AL |
2243 | static void ich9_ehci_class_init(ObjectClass *klass, void *data) |
2244 | { | |
39bffca2 | 2245 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2246 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2247 | ||
2248 | k->init = usb_ehci_initfn; | |
2249 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2250 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; | |
2251 | k->revision = 0x03; | |
2252 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2253 | dc->vmsd = &vmstate_ehci; |
2254 | dc->props = ehci_properties; | |
40021f08 AL |
2255 | } |
2256 | ||
39bffca2 AL |
2257 | static TypeInfo ich9_ehci_info = { |
2258 | .name = "ich9-usb-ehci1", | |
2259 | .parent = TYPE_PCI_DEVICE, | |
2260 | .instance_size = sizeof(EHCIState), | |
2261 | .class_init = ich9_ehci_class_init, | |
94527ead GH |
2262 | }; |
2263 | ||
2264 | static int usb_ehci_initfn(PCIDevice *dev) | |
2265 | { | |
2266 | EHCIState *s = DO_UPCAST(EHCIState, dev, dev); | |
2267 | uint8_t *pci_conf = s->dev.config; | |
2268 | int i; | |
2269 | ||
94527ead | 2270 | pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); |
94527ead GH |
2271 | |
2272 | /* capabilities pointer */ | |
2273 | pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); | |
2274 | //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); | |
2275 | ||
817e0b6f | 2276 | pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ |
94527ead GH |
2277 | pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); |
2278 | pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); | |
2279 | ||
2280 | // pci_conf[0x50] = 0x01; // power management caps | |
2281 | ||
4001f22f | 2282 | pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) |
94527ead GH |
2283 | pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) |
2284 | pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) | |
2285 | ||
2286 | pci_conf[0x64] = 0x00; | |
2287 | pci_conf[0x65] = 0x00; | |
2288 | pci_conf[0x66] = 0x00; | |
2289 | pci_conf[0x67] = 0x00; | |
2290 | pci_conf[0x68] = 0x01; | |
2291 | pci_conf[0x69] = 0x00; | |
2292 | pci_conf[0x6a] = 0x00; | |
2293 | pci_conf[0x6b] = 0x00; // USBLEGSUP | |
2294 | pci_conf[0x6c] = 0x00; | |
2295 | pci_conf[0x6d] = 0x00; | |
2296 | pci_conf[0x6e] = 0x00; | |
2297 | pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS | |
2298 | ||
2299 | // 2.2 host controller interface version | |
2300 | s->mmio[0x00] = (uint8_t) OPREGBASE; | |
2301 | s->mmio[0x01] = 0x00; | |
2302 | s->mmio[0x02] = 0x00; | |
2303 | s->mmio[0x03] = 0x01; // HC version | |
2304 | s->mmio[0x04] = NB_PORTS; // Number of downstream ports | |
2305 | s->mmio[0x05] = 0x00; // No companion ports at present | |
2306 | s->mmio[0x06] = 0x00; | |
2307 | s->mmio[0x07] = 0x00; | |
2308 | s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable | |
2309 | s->mmio[0x09] = 0x68; // EECP | |
2310 | s->mmio[0x0a] = 0x00; | |
2311 | s->mmio[0x0b] = 0x00; | |
2312 | ||
2313 | s->irq = s->dev.irq[3]; | |
2314 | ||
07771f6f | 2315 | usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); |
94527ead GH |
2316 | for(i = 0; i < NB_PORTS; i++) { |
2317 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2318 | USB_SPEED_MASK_HIGH); | |
94527ead GH |
2319 | s->ports[i].dev = 0; |
2320 | } | |
2321 | ||
2322 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
df5d5c5c HG |
2323 | QTAILQ_INIT(&s->aqueues); |
2324 | QTAILQ_INIT(&s->pqueues); | |
94527ead GH |
2325 | |
2326 | qemu_register_reset(ehci_reset, s); | |
2327 | ||
e57964f5 | 2328 | memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE); |
e824b2cc | 2329 | pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); |
94527ead | 2330 | |
94527ead GH |
2331 | return 0; |
2332 | } | |
2333 | ||
83f7d43a | 2334 | static void ehci_register_types(void) |
94527ead | 2335 | { |
39bffca2 AL |
2336 | type_register_static(&ehci_info); |
2337 | type_register_static(&ich9_ehci_info); | |
94527ead | 2338 | } |
83f7d43a AF |
2339 | |
2340 | type_init(ehci_register_types) | |
94527ead GH |
2341 | |
2342 | /* | |
2343 | * vim: expandtab ts=4 | |
2344 | */ |