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94527ead GH |
1 | /* |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
5 | * | |
6 | * EHCI project was started by Mark Burkley, with contributions by | |
7 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
8 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
9 | * | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or(at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
94527ead GH |
23 | */ |
24 | ||
f1ae32a1 | 25 | #include "hw/hw.h" |
94527ead | 26 | #include "qemu-timer.h" |
f1ae32a1 GH |
27 | #include "hw/usb.h" |
28 | #include "hw/pci.h" | |
94527ead | 29 | #include "monitor.h" |
439a97cc | 30 | #include "trace.h" |
0ce668bc | 31 | #include "dma.h" |
94527ead GH |
32 | |
33 | #define EHCI_DEBUG 0 | |
94527ead | 34 | |
26d53979 | 35 | #if EHCI_DEBUG |
94527ead GH |
36 | #define DPRINTF printf |
37 | #else | |
38 | #define DPRINTF(...) | |
39 | #endif | |
40 | ||
94527ead GH |
41 | /* internal processing - reset HC to try and recover */ |
42 | #define USB_RET_PROCERR (-99) | |
43 | ||
44 | #define MMIO_SIZE 0x1000 | |
45 | ||
46 | /* Capability Registers Base Address - section 2.2 */ | |
47 | #define CAPREGBASE 0x0000 | |
48 | #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved | |
49 | #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # | |
50 | #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params | |
51 | #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params | |
52 | #define EECP HCCPARAMS + 1 | |
53 | #define HCSPPORTROUTE1 CAPREGBASE + 0x000c | |
54 | #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 | |
55 | ||
56 | #define OPREGBASE 0x0020 // Operational Registers Base Address | |
57 | ||
58 | #define USBCMD OPREGBASE + 0x0000 | |
59 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop | |
60 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
61 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
62 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
63 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
64 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
65 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
66 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
67 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
68 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
69 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
70 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
71 | ||
72 | #define USBSTS OPREGBASE + 0x0004 | |
73 | #define USBSTS_RO_MASK 0x0000003f | |
74 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
75 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
76 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
77 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
78 | #define USBSTS_HSE (1 << 4) // Host System Error | |
79 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
80 | #define USBSTS_HALT (1 << 12) // HC Halted | |
81 | #define USBSTS_REC (1 << 13) // Reclamation | |
82 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
83 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
84 | ||
85 | /* | |
86 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
87 | * so no need to redefine here. | |
88 | */ | |
89 | #define USBINTR OPREGBASE + 0x0008 | |
90 | #define USBINTR_MASK 0x0000003f | |
91 | ||
92 | #define FRINDEX OPREGBASE + 0x000c | |
93 | #define CTRLDSSEGMENT OPREGBASE + 0x0010 | |
94 | #define PERIODICLISTBASE OPREGBASE + 0x0014 | |
95 | #define ASYNCLISTADDR OPREGBASE + 0x0018 | |
96 | #define ASYNCLISTADDR_MASK 0xffffffe0 | |
97 | ||
98 | #define CONFIGFLAG OPREGBASE + 0x0040 | |
99 | ||
100 | #define PORTSC (OPREGBASE + 0x0044) | |
101 | #define PORTSC_BEGIN PORTSC | |
102 | #define PORTSC_END (PORTSC + 4 * NB_PORTS) | |
103 | /* | |
c44fd61c | 104 | * Bits that are reserved or are read-only are masked out of values |
94527ead GH |
105 | * written to us by software |
106 | */ | |
a0a3167a | 107 | #define PORTSC_RO_MASK 0x007001c0 |
94527ead GH |
108 | #define PORTSC_RWC_MASK 0x0000002a |
109 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
110 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
111 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
112 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
113 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
114 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
115 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
116 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
117 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
118 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
119 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
120 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
121 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
122 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
123 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
124 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
125 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
126 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
127 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
128 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
129 | ||
130 | #define FRAME_TIMER_FREQ 1000 | |
adddecb1 | 131 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
94527ead GH |
132 | |
133 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
5cc194ca | 134 | #define NB_PORTS 6 // Number of downstream ports |
94527ead | 135 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction |
94527ead GH |
136 | #define MAX_QH 100 // Max allowable queue heads in a chain |
137 | ||
138 | /* Internal periodic / asynchronous schedule state machine states | |
139 | */ | |
140 | typedef enum { | |
141 | EST_INACTIVE = 1000, | |
142 | EST_ACTIVE, | |
143 | EST_EXECUTING, | |
144 | EST_SLEEPING, | |
145 | /* The following states are internal to the state machine function | |
146 | */ | |
147 | EST_WAITLISTHEAD, | |
148 | EST_FETCHENTRY, | |
149 | EST_FETCHQH, | |
150 | EST_FETCHITD, | |
2fe80192 | 151 | EST_FETCHSITD, |
94527ead GH |
152 | EST_ADVANCEQUEUE, |
153 | EST_FETCHQTD, | |
154 | EST_EXECUTE, | |
155 | EST_WRITEBACK, | |
156 | EST_HORIZONTALQH | |
157 | } EHCI_STATES; | |
158 | ||
159 | /* macros for accessing fields within next link pointer entry */ | |
160 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
161 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
162 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
163 | ||
164 | /* link pointer types */ | |
165 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
166 | #define NLPTR_TYPE_QH 1 // queue head | |
167 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
168 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
169 | ||
170 | ||
171 | /* EHCI spec version 1.0 Section 3.3 | |
172 | */ | |
173 | typedef struct EHCIitd { | |
174 | uint32_t next; | |
175 | ||
176 | uint32_t transact[8]; | |
177 | #define ITD_XACT_ACTIVE (1 << 31) | |
178 | #define ITD_XACT_DBERROR (1 << 30) | |
179 | #define ITD_XACT_BABBLE (1 << 29) | |
180 | #define ITD_XACT_XACTERR (1 << 28) | |
181 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 | |
182 | #define ITD_XACT_LENGTH_SH 16 | |
183 | #define ITD_XACT_IOC (1 << 15) | |
184 | #define ITD_XACT_PGSEL_MASK 0x00007000 | |
185 | #define ITD_XACT_PGSEL_SH 12 | |
186 | #define ITD_XACT_OFFSET_MASK 0x00000fff | |
187 | ||
188 | uint32_t bufptr[7]; | |
189 | #define ITD_BUFPTR_MASK 0xfffff000 | |
190 | #define ITD_BUFPTR_SH 12 | |
191 | #define ITD_BUFPTR_EP_MASK 0x00000f00 | |
192 | #define ITD_BUFPTR_EP_SH 8 | |
193 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f | |
194 | #define ITD_BUFPTR_DEVADDR_SH 0 | |
195 | #define ITD_BUFPTR_DIRECTION (1 << 11) | |
196 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff | |
197 | #define ITD_BUFPTR_MAXPKT_SH 0 | |
198 | #define ITD_BUFPTR_MULT_MASK 0x00000003 | |
e654887f | 199 | #define ITD_BUFPTR_MULT_SH 0 |
94527ead GH |
200 | } EHCIitd; |
201 | ||
202 | /* EHCI spec version 1.0 Section 3.4 | |
203 | */ | |
204 | typedef struct EHCIsitd { | |
205 | uint32_t next; // Standard next link pointer | |
206 | uint32_t epchar; | |
207 | #define SITD_EPCHAR_IO (1 << 31) | |
208 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 | |
209 | #define SITD_EPCHAR_PORTNUM_SH 24 | |
210 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 | |
211 | #define SITD_EPCHAR_HUBADDR_SH 16 | |
212 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 | |
213 | #define SITD_EPCHAR_EPNUM_SH 8 | |
214 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f | |
215 | ||
216 | uint32_t uframe; | |
217 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 | |
218 | #define SITD_UFRAME_CMASK_SH 8 | |
219 | #define SITD_UFRAME_SMASK_MASK 0x000000ff | |
220 | ||
221 | uint32_t results; | |
222 | #define SITD_RESULTS_IOC (1 << 31) | |
223 | #define SITD_RESULTS_PGSEL (1 << 30) | |
224 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 | |
225 | #define SITD_RESULTS_TYBYTES_SH 16 | |
226 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 | |
227 | #define SITD_RESULTS_CPROGMASK_SH 8 | |
228 | #define SITD_RESULTS_ACTIVE (1 << 7) | |
229 | #define SITD_RESULTS_ERR (1 << 6) | |
230 | #define SITD_RESULTS_DBERR (1 << 5) | |
231 | #define SITD_RESULTS_BABBLE (1 << 4) | |
232 | #define SITD_RESULTS_XACTERR (1 << 3) | |
233 | #define SITD_RESULTS_MISSEDUF (1 << 2) | |
234 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) | |
235 | ||
236 | uint32_t bufptr[2]; | |
237 | #define SITD_BUFPTR_MASK 0xfffff000 | |
238 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff | |
239 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 | |
240 | #define SITD_BUFPTR_TPOS_SH 3 | |
241 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 | |
242 | ||
243 | uint32_t backptr; // Standard next link pointer | |
244 | } EHCIsitd; | |
245 | ||
246 | /* EHCI spec version 1.0 Section 3.5 | |
247 | */ | |
248 | typedef struct EHCIqtd { | |
249 | uint32_t next; // Standard next link pointer | |
250 | uint32_t altnext; // Standard next link pointer | |
251 | uint32_t token; | |
252 | #define QTD_TOKEN_DTOGGLE (1 << 31) | |
253 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 | |
254 | #define QTD_TOKEN_TBYTES_SH 16 | |
255 | #define QTD_TOKEN_IOC (1 << 15) | |
256 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 | |
257 | #define QTD_TOKEN_CPAGE_SH 12 | |
258 | #define QTD_TOKEN_CERR_MASK 0x00000c00 | |
259 | #define QTD_TOKEN_CERR_SH 10 | |
260 | #define QTD_TOKEN_PID_MASK 0x00000300 | |
261 | #define QTD_TOKEN_PID_SH 8 | |
262 | #define QTD_TOKEN_ACTIVE (1 << 7) | |
263 | #define QTD_TOKEN_HALT (1 << 6) | |
264 | #define QTD_TOKEN_DBERR (1 << 5) | |
265 | #define QTD_TOKEN_BABBLE (1 << 4) | |
266 | #define QTD_TOKEN_XACTERR (1 << 3) | |
267 | #define QTD_TOKEN_MISSEDUF (1 << 2) | |
268 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) | |
269 | #define QTD_TOKEN_PING (1 << 0) | |
270 | ||
271 | uint32_t bufptr[5]; // Standard buffer pointer | |
272 | #define QTD_BUFPTR_MASK 0xfffff000 | |
0ce668bc | 273 | #define QTD_BUFPTR_SH 12 |
94527ead GH |
274 | } EHCIqtd; |
275 | ||
276 | /* EHCI spec version 1.0 Section 3.6 | |
277 | */ | |
278 | typedef struct EHCIqh { | |
279 | uint32_t next; // Standard next link pointer | |
280 | ||
281 | /* endpoint characteristics */ | |
282 | uint32_t epchar; | |
283 | #define QH_EPCHAR_RL_MASK 0xf0000000 | |
284 | #define QH_EPCHAR_RL_SH 28 | |
285 | #define QH_EPCHAR_C (1 << 27) | |
286 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 | |
287 | #define QH_EPCHAR_MPLEN_SH 16 | |
288 | #define QH_EPCHAR_H (1 << 15) | |
289 | #define QH_EPCHAR_DTC (1 << 14) | |
290 | #define QH_EPCHAR_EPS_MASK 0x00003000 | |
291 | #define QH_EPCHAR_EPS_SH 12 | |
292 | #define EHCI_QH_EPS_FULL 0 | |
293 | #define EHCI_QH_EPS_LOW 1 | |
294 | #define EHCI_QH_EPS_HIGH 2 | |
295 | #define EHCI_QH_EPS_RESERVED 3 | |
296 | ||
297 | #define QH_EPCHAR_EP_MASK 0x00000f00 | |
298 | #define QH_EPCHAR_EP_SH 8 | |
299 | #define QH_EPCHAR_I (1 << 7) | |
300 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f | |
301 | #define QH_EPCHAR_DEVADDR_SH 0 | |
302 | ||
303 | /* endpoint capabilities */ | |
304 | uint32_t epcap; | |
305 | #define QH_EPCAP_MULT_MASK 0xc0000000 | |
306 | #define QH_EPCAP_MULT_SH 30 | |
307 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 | |
308 | #define QH_EPCAP_PORTNUM_SH 23 | |
309 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 | |
310 | #define QH_EPCAP_HUBADDR_SH 16 | |
311 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 | |
312 | #define QH_EPCAP_CMASK_SH 8 | |
313 | #define QH_EPCAP_SMASK_MASK 0x000000ff | |
314 | #define QH_EPCAP_SMASK_SH 0 | |
315 | ||
316 | uint32_t current_qtd; // Standard next link pointer | |
317 | uint32_t next_qtd; // Standard next link pointer | |
318 | uint32_t altnext_qtd; | |
319 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e | |
320 | #define QH_ALTNEXT_NAKCNT_SH 1 | |
321 | ||
322 | uint32_t token; // Same as QTD token | |
323 | uint32_t bufptr[5]; // Standard buffer pointer | |
324 | #define BUFPTR_CPROGMASK_MASK 0x000000ff | |
325 | #define BUFPTR_FRAMETAG_MASK 0x0000001f | |
326 | #define BUFPTR_SBYTES_MASK 0x00000fe0 | |
327 | #define BUFPTR_SBYTES_SH 5 | |
328 | } EHCIqh; | |
329 | ||
330 | /* EHCI spec version 1.0 Section 3.7 | |
331 | */ | |
332 | typedef struct EHCIfstn { | |
333 | uint32_t next; // Standard next link pointer | |
334 | uint32_t backptr; // Standard next link pointer | |
335 | } EHCIfstn; | |
336 | ||
eb36a88e | 337 | typedef struct EHCIPacket EHCIPacket; |
0122f472 GH |
338 | typedef struct EHCIQueue EHCIQueue; |
339 | typedef struct EHCIState EHCIState; | |
340 | ||
341 | enum async_state { | |
342 | EHCI_ASYNC_NONE = 0, | |
343 | EHCI_ASYNC_INFLIGHT, | |
344 | EHCI_ASYNC_FINISHED, | |
345 | }; | |
346 | ||
eb36a88e GH |
347 | struct EHCIPacket { |
348 | EHCIQueue *queue; | |
349 | QTAILQ_ENTRY(EHCIPacket) next; | |
350 | ||
351 | EHCIqtd qtd; /* copy of current QTD (being worked on) */ | |
352 | uint32_t qtdaddr; /* address QTD read from */ | |
353 | ||
354 | USBPacket packet; | |
355 | QEMUSGList sgl; | |
356 | int pid; | |
357 | uint32_t tbytes; | |
358 | enum async_state async; | |
359 | int usb_status; | |
360 | }; | |
361 | ||
0122f472 GH |
362 | struct EHCIQueue { |
363 | EHCIState *ehci; | |
8ac6d699 | 364 | QTAILQ_ENTRY(EHCIQueue) next; |
adddecb1 GH |
365 | uint32_t seen; |
366 | uint64_t ts; | |
0122f472 GH |
367 | |
368 | /* cached data from guest - needs to be flushed | |
369 | * when guest removes an entry (doorbell, handshake sequence) | |
370 | */ | |
eb36a88e GH |
371 | EHCIqh qh; /* copy of current QH (being worked on) */ |
372 | uint32_t qhaddr; /* address QH read from */ | |
373 | uint32_t qtdaddr; /* address QTD read from */ | |
374 | QTAILQ_HEAD(, EHCIPacket) packets; | |
0122f472 GH |
375 | }; |
376 | ||
df5d5c5c HG |
377 | typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; |
378 | ||
0122f472 | 379 | struct EHCIState { |
94527ead | 380 | PCIDevice dev; |
0122f472 | 381 | USBBus bus; |
94527ead | 382 | qemu_irq irq; |
e57964f5 | 383 | MemoryRegion mem; |
a0a3167a | 384 | int companion_count; |
16a2dee6 GH |
385 | |
386 | /* properties */ | |
387 | uint32_t freq; | |
388 | uint32_t maxframes; | |
389 | ||
94527ead GH |
390 | /* |
391 | * EHCI spec version 1.0 Section 2.3 | |
392 | * Host Controller Operational Registers | |
393 | */ | |
394 | union { | |
395 | uint8_t mmio[MMIO_SIZE]; | |
396 | struct { | |
397 | uint8_t cap[OPREGBASE]; | |
398 | uint32_t usbcmd; | |
399 | uint32_t usbsts; | |
400 | uint32_t usbintr; | |
401 | uint32_t frindex; | |
402 | uint32_t ctrldssegment; | |
403 | uint32_t periodiclistbase; | |
404 | uint32_t asynclistaddr; | |
405 | uint32_t notused[9]; | |
406 | uint32_t configflag; | |
407 | uint32_t portsc[NB_PORTS]; | |
408 | }; | |
409 | }; | |
0122f472 | 410 | |
94527ead GH |
411 | /* |
412 | * Internal states, shadow registers, etc | |
413 | */ | |
94527ead GH |
414 | QEMUTimer *frame_timer; |
415 | int attach_poll_counter; | |
416 | int astate; // Current state in asynchronous schedule | |
417 | int pstate; // Current state in periodic schedule | |
418 | USBPort ports[NB_PORTS]; | |
a0a3167a | 419 | USBPort *companion_ports[NB_PORTS]; |
94527ead | 420 | uint32_t usbsts_pending; |
df5d5c5c HG |
421 | EHCIQueueHead aqueues; |
422 | EHCIQueueHead pqueues; | |
94527ead | 423 | |
0122f472 GH |
424 | uint32_t a_fetch_addr; // which address to look at next |
425 | uint32_t p_fetch_addr; // which address to look at next | |
94527ead | 426 | |
0122f472 | 427 | USBPacket ipacket; |
0ce668bc | 428 | QEMUSGList isgl; |
0122f472 | 429 | |
adddecb1 | 430 | uint64_t last_run_ns; |
0122f472 | 431 | }; |
94527ead GH |
432 | |
433 | #define SET_LAST_RUN_CLOCK(s) \ | |
adddecb1 | 434 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
94527ead GH |
435 | |
436 | /* nifty macros from Arnon's EHCI version */ | |
437 | #define get_field(data, field) \ | |
438 | (((data) & field##_MASK) >> field##_SH) | |
439 | ||
440 | #define set_field(data, newval, field) do { \ | |
441 | uint32_t val = *data; \ | |
442 | val &= ~ field##_MASK; \ | |
443 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
444 | *data = val; \ | |
445 | } while(0) | |
446 | ||
26d53979 | 447 | static const char *ehci_state_names[] = { |
aac882e7 GH |
448 | [EST_INACTIVE] = "INACTIVE", |
449 | [EST_ACTIVE] = "ACTIVE", | |
450 | [EST_EXECUTING] = "EXECUTING", | |
451 | [EST_SLEEPING] = "SLEEPING", | |
452 | [EST_WAITLISTHEAD] = "WAITLISTHEAD", | |
453 | [EST_FETCHENTRY] = "FETCH ENTRY", | |
454 | [EST_FETCHQH] = "FETCH QH", | |
455 | [EST_FETCHITD] = "FETCH ITD", | |
456 | [EST_ADVANCEQUEUE] = "ADVANCEQUEUE", | |
457 | [EST_FETCHQTD] = "FETCH QTD", | |
458 | [EST_EXECUTE] = "EXECUTE", | |
459 | [EST_WRITEBACK] = "WRITEBACK", | |
460 | [EST_HORIZONTALQH] = "HORIZONTALQH", | |
26d53979 GH |
461 | }; |
462 | ||
463 | static const char *ehci_mmio_names[] = { | |
aac882e7 GH |
464 | [CAPLENGTH] = "CAPLENGTH", |
465 | [HCIVERSION] = "HCIVERSION", | |
466 | [HCSPARAMS] = "HCSPARAMS", | |
467 | [HCCPARAMS] = "HCCPARAMS", | |
468 | [USBCMD] = "USBCMD", | |
469 | [USBSTS] = "USBSTS", | |
470 | [USBINTR] = "USBINTR", | |
471 | [FRINDEX] = "FRINDEX", | |
472 | [PERIODICLISTBASE] = "P-LIST BASE", | |
473 | [ASYNCLISTADDR] = "A-LIST ADDR", | |
474 | [PORTSC_BEGIN] = "PORTSC #0", | |
475 | [PORTSC_BEGIN + 4] = "PORTSC #1", | |
476 | [PORTSC_BEGIN + 8] = "PORTSC #2", | |
477 | [PORTSC_BEGIN + 12] = "PORTSC #3", | |
335b8d20 GH |
478 | [PORTSC_BEGIN + 16] = "PORTSC #4", |
479 | [PORTSC_BEGIN + 20] = "PORTSC #5", | |
aac882e7 | 480 | [CONFIGFLAG] = "CONFIGFLAG", |
26d53979 | 481 | }; |
94527ead | 482 | |
26d53979 | 483 | static const char *nr2str(const char **n, size_t len, uint32_t nr) |
94527ead | 484 | { |
26d53979 GH |
485 | if (nr < len && n[nr] != NULL) { |
486 | return n[nr]; | |
94527ead | 487 | } else { |
26d53979 | 488 | return "unknown"; |
94527ead GH |
489 | } |
490 | } | |
94527ead | 491 | |
26d53979 GH |
492 | static const char *state2str(uint32_t state) |
493 | { | |
494 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
495 | } | |
496 | ||
497 | static const char *addr2str(target_phys_addr_t addr) | |
498 | { | |
499 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); | |
500 | } | |
501 | ||
439a97cc GH |
502 | static void ehci_trace_usbsts(uint32_t mask, int state) |
503 | { | |
504 | /* interrupts */ | |
505 | if (mask & USBSTS_INT) { | |
506 | trace_usb_ehci_usbsts("INT", state); | |
507 | } | |
508 | if (mask & USBSTS_ERRINT) { | |
509 | trace_usb_ehci_usbsts("ERRINT", state); | |
510 | } | |
511 | if (mask & USBSTS_PCD) { | |
512 | trace_usb_ehci_usbsts("PCD", state); | |
513 | } | |
514 | if (mask & USBSTS_FLR) { | |
515 | trace_usb_ehci_usbsts("FLR", state); | |
516 | } | |
517 | if (mask & USBSTS_HSE) { | |
518 | trace_usb_ehci_usbsts("HSE", state); | |
519 | } | |
520 | if (mask & USBSTS_IAA) { | |
521 | trace_usb_ehci_usbsts("IAA", state); | |
522 | } | |
523 | ||
524 | /* status */ | |
525 | if (mask & USBSTS_HALT) { | |
526 | trace_usb_ehci_usbsts("HALT", state); | |
527 | } | |
528 | if (mask & USBSTS_REC) { | |
529 | trace_usb_ehci_usbsts("REC", state); | |
530 | } | |
531 | if (mask & USBSTS_PSS) { | |
532 | trace_usb_ehci_usbsts("PSS", state); | |
533 | } | |
534 | if (mask & USBSTS_ASS) { | |
535 | trace_usb_ehci_usbsts("ASS", state); | |
536 | } | |
537 | } | |
538 | ||
539 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
540 | { | |
541 | if ((s->usbsts & mask) == mask) { | |
542 | return; | |
543 | } | |
544 | ehci_trace_usbsts(mask, 1); | |
545 | s->usbsts |= mask; | |
546 | } | |
547 | ||
548 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
549 | { | |
550 | if ((s->usbsts & mask) == 0) { | |
551 | return; | |
552 | } | |
553 | ehci_trace_usbsts(mask, 0); | |
554 | s->usbsts &= ~mask; | |
555 | } | |
94527ead GH |
556 | |
557 | static inline void ehci_set_interrupt(EHCIState *s, int intr) | |
558 | { | |
559 | int level = 0; | |
560 | ||
561 | // TODO honour interrupt threshold requests | |
562 | ||
439a97cc | 563 | ehci_set_usbsts(s, intr); |
94527ead GH |
564 | |
565 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { | |
566 | level = 1; | |
567 | } | |
568 | ||
569 | qemu_set_irq(s->irq, level); | |
570 | } | |
571 | ||
572 | static inline void ehci_record_interrupt(EHCIState *s, int intr) | |
573 | { | |
574 | s->usbsts_pending |= intr; | |
575 | } | |
576 | ||
577 | static inline void ehci_commit_interrupt(EHCIState *s) | |
578 | { | |
579 | if (!s->usbsts_pending) { | |
580 | return; | |
581 | } | |
582 | ehci_set_interrupt(s, s->usbsts_pending); | |
583 | s->usbsts_pending = 0; | |
584 | } | |
585 | ||
26d53979 GH |
586 | static void ehci_set_state(EHCIState *s, int async, int state) |
587 | { | |
588 | if (async) { | |
589 | trace_usb_ehci_state("async", state2str(state)); | |
590 | s->astate = state; | |
591 | } else { | |
592 | trace_usb_ehci_state("periodic", state2str(state)); | |
593 | s->pstate = state; | |
594 | } | |
595 | } | |
596 | ||
597 | static int ehci_get_state(EHCIState *s, int async) | |
598 | { | |
599 | return async ? s->astate : s->pstate; | |
600 | } | |
601 | ||
0122f472 GH |
602 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
603 | { | |
604 | if (async) { | |
605 | s->a_fetch_addr = addr; | |
606 | } else { | |
607 | s->p_fetch_addr = addr; | |
608 | } | |
609 | } | |
610 | ||
611 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
612 | { | |
613 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
614 | } | |
615 | ||
8ac6d699 | 616 | static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) |
26d53979 | 617 | { |
025b168c GH |
618 | /* need three here due to argument count limits */ |
619 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
620 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
621 | trace_usb_ehci_qh_fields(addr, | |
622 | get_field(qh->epchar, QH_EPCHAR_RL), | |
623 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
624 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
625 | get_field(qh->epchar, QH_EPCHAR_EP), | |
626 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
627 | trace_usb_ehci_qh_bits(addr, | |
628 | (bool)(qh->epchar & QH_EPCHAR_C), | |
629 | (bool)(qh->epchar & QH_EPCHAR_H), | |
630 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
631 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
26d53979 GH |
632 | } |
633 | ||
8ac6d699 | 634 | static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) |
26d53979 | 635 | { |
025b168c GH |
636 | /* need three here due to argument count limits */ |
637 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
638 | trace_usb_ehci_qtd_fields(addr, | |
639 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
640 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
641 | get_field(qtd->token, QTD_TOKEN_CERR), | |
642 | get_field(qtd->token, QTD_TOKEN_PID)); | |
643 | trace_usb_ehci_qtd_bits(addr, | |
644 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
645 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
646 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
647 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
648 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
26d53979 GH |
649 | } |
650 | ||
651 | static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) | |
652 | { | |
e654887f GH |
653 | trace_usb_ehci_itd(addr, itd->next, |
654 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
655 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
656 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
657 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
26d53979 GH |
658 | } |
659 | ||
2fe80192 GH |
660 | static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr, |
661 | EHCIsitd *sitd) | |
662 | { | |
663 | trace_usb_ehci_sitd(addr, sitd->next, | |
664 | (bool)(sitd->results & SITD_RESULTS_ACTIVE)); | |
665 | } | |
666 | ||
eb36a88e GH |
667 | /* packet management */ |
668 | ||
669 | static EHCIPacket *ehci_alloc_packet(EHCIQueue *q) | |
670 | { | |
671 | EHCIPacket *p; | |
672 | ||
673 | #if 1 | |
674 | /* temporary, we don't handle multiple packets per queue (yet) */ | |
675 | assert(QTAILQ_EMPTY(&q->packets)); | |
676 | #endif | |
677 | p = g_new0(EHCIPacket, 1); | |
678 | p->queue = q; | |
679 | usb_packet_init(&p->packet); | |
680 | QTAILQ_INSERT_TAIL(&q->packets, p, next); | |
681 | trace_usb_ehci_packet_action(p->queue, p, "alloc"); | |
682 | return p; | |
683 | } | |
684 | ||
685 | static void ehci_free_packet(EHCIPacket *p) | |
686 | { | |
687 | trace_usb_ehci_packet_action(p->queue, p, "free"); | |
688 | if (p->async == EHCI_ASYNC_INFLIGHT) { | |
689 | usb_cancel_packet(&p->packet); | |
690 | } | |
691 | QTAILQ_REMOVE(&p->queue->packets, p, next); | |
692 | usb_packet_cleanup(&p->packet); | |
693 | g_free(p); | |
694 | } | |
695 | ||
8ac6d699 GH |
696 | /* queue management */ |
697 | ||
698 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async) | |
699 | { | |
df5d5c5c | 700 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
701 | EHCIQueue *q; |
702 | ||
7267c094 | 703 | q = g_malloc0(sizeof(*q)); |
8ac6d699 | 704 | q->ehci = ehci; |
eb36a88e | 705 | QTAILQ_INIT(&q->packets); |
df5d5c5c | 706 | QTAILQ_INSERT_HEAD(head, q, next); |
8ac6d699 GH |
707 | trace_usb_ehci_queue_action(q, "alloc"); |
708 | return q; | |
709 | } | |
710 | ||
df5d5c5c | 711 | static void ehci_free_queue(EHCIQueue *q, int async) |
8ac6d699 | 712 | { |
df5d5c5c | 713 | EHCIQueueHead *head = async ? &q->ehci->aqueues : &q->ehci->pqueues; |
eb36a88e GH |
714 | EHCIPacket *p; |
715 | ||
8ac6d699 | 716 | trace_usb_ehci_queue_action(q, "free"); |
eb36a88e GH |
717 | while ((p = QTAILQ_FIRST(&q->packets)) != NULL) { |
718 | ehci_free_packet(p); | |
8ac6d699 | 719 | } |
df5d5c5c | 720 | QTAILQ_REMOVE(head, q, next); |
7267c094 | 721 | g_free(q); |
8ac6d699 GH |
722 | } |
723 | ||
df5d5c5c HG |
724 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr, |
725 | int async) | |
8ac6d699 | 726 | { |
df5d5c5c | 727 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
728 | EHCIQueue *q; |
729 | ||
df5d5c5c | 730 | QTAILQ_FOREACH(q, head, next) { |
8ac6d699 GH |
731 | if (addr == q->qhaddr) { |
732 | return q; | |
733 | } | |
734 | } | |
735 | return NULL; | |
736 | } | |
737 | ||
4be23939 | 738 | static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush) |
8ac6d699 | 739 | { |
df5d5c5c | 740 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
741 | EHCIQueue *q, *tmp; |
742 | ||
df5d5c5c | 743 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
8ac6d699 GH |
744 | if (q->seen) { |
745 | q->seen = 0; | |
adddecb1 | 746 | q->ts = ehci->last_run_ns; |
8ac6d699 GH |
747 | continue; |
748 | } | |
4be23939 | 749 | if (!flush && ehci->last_run_ns < q->ts + 250000000) { |
8ac6d699 GH |
750 | /* allow 0.25 sec idle */ |
751 | continue; | |
752 | } | |
df5d5c5c | 753 | ehci_free_queue(q, async); |
8ac6d699 GH |
754 | } |
755 | } | |
756 | ||
df5d5c5c | 757 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async) |
07771f6f | 758 | { |
df5d5c5c | 759 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
07771f6f | 760 | EHCIQueue *q, *tmp; |
eb36a88e | 761 | int addr; |
07771f6f | 762 | |
df5d5c5c | 763 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
eb36a88e GH |
764 | addr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); |
765 | if (addr != dev->addr) { | |
07771f6f GH |
766 | continue; |
767 | } | |
df5d5c5c | 768 | ehci_free_queue(q, async); |
07771f6f GH |
769 | } |
770 | } | |
771 | ||
df5d5c5c | 772 | static void ehci_queues_rip_all(EHCIState *ehci, int async) |
8ac6d699 | 773 | { |
df5d5c5c | 774 | EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues; |
8ac6d699 GH |
775 | EHCIQueue *q, *tmp; |
776 | ||
df5d5c5c HG |
777 | QTAILQ_FOREACH_SAFE(q, head, next, tmp) { |
778 | ehci_free_queue(q, async); | |
8ac6d699 GH |
779 | } |
780 | } | |
781 | ||
94527ead GH |
782 | /* Attach or detach a device on root hub */ |
783 | ||
784 | static void ehci_attach(USBPort *port) | |
785 | { | |
786 | EHCIState *s = port->opaque; | |
787 | uint32_t *portsc = &s->portsc[port->index]; | |
788 | ||
dcbd0b5c | 789 | trace_usb_ehci_port_attach(port->index, port->dev->product_desc); |
94527ead | 790 | |
a0a3167a HG |
791 | if (*portsc & PORTSC_POWNER) { |
792 | USBPort *companion = s->companion_ports[port->index]; | |
793 | companion->dev = port->dev; | |
794 | companion->ops->attach(companion); | |
795 | return; | |
796 | } | |
797 | ||
94527ead GH |
798 | *portsc |= PORTSC_CONNECT; |
799 | *portsc |= PORTSC_CSC; | |
800 | ||
a0a3167a | 801 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
802 | } |
803 | ||
804 | static void ehci_detach(USBPort *port) | |
805 | { | |
806 | EHCIState *s = port->opaque; | |
807 | uint32_t *portsc = &s->portsc[port->index]; | |
808 | ||
dcbd0b5c | 809 | trace_usb_ehci_port_detach(port->index); |
94527ead | 810 | |
a0a3167a HG |
811 | if (*portsc & PORTSC_POWNER) { |
812 | USBPort *companion = s->companion_ports[port->index]; | |
813 | companion->ops->detach(companion); | |
814 | companion->dev = NULL; | |
f76e1d81 HG |
815 | /* |
816 | * EHCI spec 4.2.2: "When a disconnect occurs... On the event, | |
817 | * the port ownership is returned immediately to the EHCI controller." | |
818 | */ | |
819 | *portsc &= ~PORTSC_POWNER; | |
a0a3167a HG |
820 | return; |
821 | } | |
822 | ||
df5d5c5c HG |
823 | ehci_queues_rip_device(s, port->dev, 0); |
824 | ehci_queues_rip_device(s, port->dev, 1); | |
4706ab6c | 825 | |
fbd97532 | 826 | *portsc &= ~(PORTSC_CONNECT|PORTSC_PED); |
94527ead GH |
827 | *portsc |= PORTSC_CSC; |
828 | ||
a0a3167a | 829 | ehci_set_interrupt(s, USBSTS_PCD); |
94527ead GH |
830 | } |
831 | ||
4706ab6c HG |
832 | static void ehci_child_detach(USBPort *port, USBDevice *child) |
833 | { | |
834 | EHCIState *s = port->opaque; | |
a0a3167a HG |
835 | uint32_t portsc = s->portsc[port->index]; |
836 | ||
837 | if (portsc & PORTSC_POWNER) { | |
838 | USBPort *companion = s->companion_ports[port->index]; | |
839 | companion->ops->child_detach(companion, child); | |
a0a3167a HG |
840 | return; |
841 | } | |
4706ab6c | 842 | |
df5d5c5c HG |
843 | ehci_queues_rip_device(s, child, 0); |
844 | ehci_queues_rip_device(s, child, 1); | |
4706ab6c HG |
845 | } |
846 | ||
a0a3167a HG |
847 | static void ehci_wakeup(USBPort *port) |
848 | { | |
849 | EHCIState *s = port->opaque; | |
850 | uint32_t portsc = s->portsc[port->index]; | |
851 | ||
852 | if (portsc & PORTSC_POWNER) { | |
853 | USBPort *companion = s->companion_ports[port->index]; | |
854 | if (companion->ops->wakeup) { | |
855 | companion->ops->wakeup(companion); | |
856 | } | |
857 | } | |
858 | } | |
859 | ||
860 | static int ehci_register_companion(USBBus *bus, USBPort *ports[], | |
861 | uint32_t portcount, uint32_t firstport) | |
862 | { | |
863 | EHCIState *s = container_of(bus, EHCIState, bus); | |
864 | uint32_t i; | |
865 | ||
866 | if (firstport + portcount > NB_PORTS) { | |
867 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport", | |
868 | "firstport on masterbus"); | |
869 | error_printf_unless_qmp( | |
870 | "firstport value of %u makes companion take ports %u - %u, which " | |
871 | "is outside of the valid range of 0 - %u\n", firstport, firstport, | |
872 | firstport + portcount - 1, NB_PORTS - 1); | |
873 | return -1; | |
874 | } | |
875 | ||
876 | for (i = 0; i < portcount; i++) { | |
877 | if (s->companion_ports[firstport + i]) { | |
878 | qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus", | |
879 | "an USB masterbus"); | |
880 | error_printf_unless_qmp( | |
881 | "port %u on masterbus %s already has a companion assigned\n", | |
882 | firstport + i, bus->qbus.name); | |
883 | return -1; | |
884 | } | |
885 | } | |
886 | ||
887 | for (i = 0; i < portcount; i++) { | |
888 | s->companion_ports[firstport + i] = ports[i]; | |
889 | s->ports[firstport + i].speedmask |= | |
890 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL; | |
891 | /* Ensure devs attached before the initial reset go to the companion */ | |
892 | s->portsc[firstport + i] = PORTSC_POWNER; | |
893 | } | |
894 | ||
895 | s->companion_count++; | |
896 | s->mmio[0x05] = (s->companion_count << 4) | portcount; | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
828143c6 GH |
901 | static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr) |
902 | { | |
903 | USBDevice *dev; | |
904 | USBPort *port; | |
905 | int i; | |
906 | ||
907 | for (i = 0; i < NB_PORTS; i++) { | |
908 | port = &ehci->ports[i]; | |
909 | if (!(ehci->portsc[i] & PORTSC_PED)) { | |
910 | DPRINTF("Port %d not enabled\n", i); | |
911 | continue; | |
912 | } | |
913 | dev = usb_find_device(port, addr); | |
914 | if (dev != NULL) { | |
915 | return dev; | |
916 | } | |
917 | } | |
918 | return NULL; | |
919 | } | |
920 | ||
94527ead GH |
921 | /* 4.1 host controller initialization */ |
922 | static void ehci_reset(void *opaque) | |
923 | { | |
924 | EHCIState *s = opaque; | |
94527ead | 925 | int i; |
a0a3167a | 926 | USBDevice *devs[NB_PORTS]; |
94527ead | 927 | |
439a97cc | 928 | trace_usb_ehci_reset(); |
94527ead | 929 | |
a0a3167a HG |
930 | /* |
931 | * Do the detach before touching portsc, so that it correctly gets send to | |
932 | * us or to our companion based on PORTSC_POWNER before the reset. | |
933 | */ | |
934 | for(i = 0; i < NB_PORTS; i++) { | |
935 | devs[i] = s->ports[i].dev; | |
891fb2cd GH |
936 | if (devs[i] && devs[i]->attached) { |
937 | usb_detach(&s->ports[i]); | |
a0a3167a HG |
938 | } |
939 | } | |
940 | ||
94527ead GH |
941 | memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); |
942 | ||
943 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
944 | s->usbsts = USBSTS_HALT; | |
945 | ||
946 | s->astate = EST_INACTIVE; | |
947 | s->pstate = EST_INACTIVE; | |
94527ead GH |
948 | s->attach_poll_counter = 0; |
949 | ||
950 | for(i = 0; i < NB_PORTS; i++) { | |
a0a3167a HG |
951 | if (s->companion_ports[i]) { |
952 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
953 | } else { | |
954 | s->portsc[i] = PORTSC_PPOWER; | |
955 | } | |
891fb2cd GH |
956 | if (devs[i] && devs[i]->attached) { |
957 | usb_attach(&s->ports[i]); | |
d28f4e2d | 958 | usb_device_reset(devs[i]); |
94527ead GH |
959 | } |
960 | } | |
df5d5c5c HG |
961 | ehci_queues_rip_all(s, 0); |
962 | ehci_queues_rip_all(s, 1); | |
81d37739 | 963 | qemu_del_timer(s->frame_timer); |
94527ead GH |
964 | } |
965 | ||
966 | static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) | |
967 | { | |
968 | EHCIState *s = ptr; | |
969 | uint32_t val; | |
970 | ||
971 | val = s->mmio[addr]; | |
972 | ||
973 | return val; | |
974 | } | |
975 | ||
976 | static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) | |
977 | { | |
978 | EHCIState *s = ptr; | |
979 | uint32_t val; | |
980 | ||
981 | val = s->mmio[addr] | (s->mmio[addr+1] << 8); | |
982 | ||
983 | return val; | |
984 | } | |
985 | ||
986 | static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) | |
987 | { | |
988 | EHCIState *s = ptr; | |
989 | uint32_t val; | |
990 | ||
991 | val = s->mmio[addr] | (s->mmio[addr+1] << 8) | | |
992 | (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); | |
993 | ||
439a97cc | 994 | trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); |
94527ead GH |
995 | return val; |
996 | } | |
997 | ||
998 | static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) | |
999 | { | |
1000 | fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); | |
1001 | exit(1); | |
1002 | } | |
1003 | ||
1004 | static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) | |
1005 | { | |
1006 | fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); | |
1007 | exit(1); | |
1008 | } | |
1009 | ||
a0a3167a HG |
1010 | static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner) |
1011 | { | |
1012 | USBDevice *dev = s->ports[port].dev; | |
1013 | uint32_t *portsc = &s->portsc[port]; | |
1014 | uint32_t orig; | |
1015 | ||
1016 | if (s->companion_ports[port] == NULL) | |
1017 | return; | |
1018 | ||
1019 | owner = owner & PORTSC_POWNER; | |
1020 | orig = *portsc & PORTSC_POWNER; | |
1021 | ||
1022 | if (!(owner ^ orig)) { | |
1023 | return; | |
1024 | } | |
1025 | ||
891fb2cd GH |
1026 | if (dev && dev->attached) { |
1027 | usb_detach(&s->ports[port]); | |
a0a3167a HG |
1028 | } |
1029 | ||
1030 | *portsc &= ~PORTSC_POWNER; | |
1031 | *portsc |= owner; | |
1032 | ||
891fb2cd GH |
1033 | if (dev && dev->attached) { |
1034 | usb_attach(&s->ports[port]); | |
a0a3167a HG |
1035 | } |
1036 | } | |
1037 | ||
94527ead GH |
1038 | static void handle_port_status_write(EHCIState *s, int port, uint32_t val) |
1039 | { | |
1040 | uint32_t *portsc = &s->portsc[port]; | |
94527ead GH |
1041 | USBDevice *dev = s->ports[port].dev; |
1042 | ||
fbd97532 HG |
1043 | /* Clear rwc bits */ |
1044 | *portsc &= ~(val & PORTSC_RWC_MASK); | |
1045 | /* The guest may clear, but not set the PED bit */ | |
1046 | *portsc &= val | ~PORTSC_PED; | |
a0a3167a HG |
1047 | /* POWNER is masked out by RO_MASK as it is RO when we've no companion */ |
1048 | handle_port_owner_write(s, port, val); | |
1049 | /* And finally apply RO_MASK */ | |
94527ead GH |
1050 | val &= PORTSC_RO_MASK; |
1051 | ||
94527ead | 1052 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { |
dcbd0b5c | 1053 | trace_usb_ehci_port_reset(port, 1); |
94527ead GH |
1054 | } |
1055 | ||
1056 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 1057 | trace_usb_ehci_port_reset(port, 0); |
891fb2cd | 1058 | if (dev && dev->attached) { |
d28f4e2d | 1059 | usb_port_reset(&s->ports[port]); |
94527ead GH |
1060 | *portsc &= ~PORTSC_CSC; |
1061 | } | |
1062 | ||
fbd97532 HG |
1063 | /* |
1064 | * Table 2.16 Set the enable bit(and enable bit change) to indicate | |
94527ead | 1065 | * to SW that this port has a high speed device attached |
94527ead | 1066 | */ |
891fb2cd | 1067 | if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) { |
fbd97532 HG |
1068 | val |= PORTSC_PED; |
1069 | } | |
94527ead GH |
1070 | } |
1071 | ||
1072 | *portsc &= ~PORTSC_RO_MASK; | |
1073 | *portsc |= val; | |
94527ead GH |
1074 | } |
1075 | ||
1076 | static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) | |
1077 | { | |
1078 | EHCIState *s = ptr; | |
c4f8e211 GH |
1079 | uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); |
1080 | uint32_t old = *mmio; | |
94527ead | 1081 | int i; |
439a97cc | 1082 | |
c4f8e211 | 1083 | trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); |
94527ead GH |
1084 | |
1085 | /* Only aligned reads are allowed on OHCI */ | |
1086 | if (addr & 3) { | |
1087 | fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" | |
1088 | TARGET_FMT_plx "\n", addr); | |
1089 | return; | |
1090 | } | |
1091 | ||
1092 | if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { | |
1093 | handle_port_status_write(s, (addr-PORTSC)/4, val); | |
c4f8e211 | 1094 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); |
94527ead GH |
1095 | return; |
1096 | } | |
1097 | ||
1098 | if (addr < OPREGBASE) { | |
1099 | fprintf(stderr, "usb-ehci: write attempt to read-only register" | |
1100 | TARGET_FMT_plx "\n", addr); | |
1101 | return; | |
1102 | } | |
1103 | ||
1104 | ||
1105 | /* Do any register specific pre-write processing here. */ | |
94527ead GH |
1106 | switch(addr) { |
1107 | case USBCMD: | |
94527ead | 1108 | if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) { |
94527ead GH |
1109 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
1110 | SET_LAST_RUN_CLOCK(s); | |
439a97cc | 1111 | ehci_clear_usbsts(s, USBSTS_HALT); |
94527ead GH |
1112 | } |
1113 | ||
1114 | if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
94527ead | 1115 | qemu_del_timer(s->frame_timer); |
e850c2b4 HG |
1116 | ehci_queues_rip_all(s, 0); |
1117 | ehci_queues_rip_all(s, 1); | |
439a97cc | 1118 | ehci_set_usbsts(s, USBSTS_HALT); |
94527ead GH |
1119 | } |
1120 | ||
1121 | if (val & USBCMD_HCRESET) { | |
94527ead | 1122 | ehci_reset(s); |
81d37739 | 1123 | val = s->usbcmd; |
94527ead GH |
1124 | } |
1125 | ||
1126 | /* not supporting dynamic frame list size at the moment */ | |
1127 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
1128 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
1129 | val & USBCMD_FLS); | |
1130 | val &= ~USBCMD_FLS; | |
1131 | } | |
94527ead GH |
1132 | break; |
1133 | ||
94527ead | 1134 | case USBSTS: |
a31f0531 JM |
1135 | val &= USBSTS_RO_MASK; // bits 6 through 31 are RO |
1136 | ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC | |
439a97cc | 1137 | val = s->usbsts; |
94527ead GH |
1138 | ehci_set_interrupt(s, 0); |
1139 | break; | |
1140 | ||
94527ead GH |
1141 | case USBINTR: |
1142 | val &= USBINTR_MASK; | |
94527ead GH |
1143 | break; |
1144 | ||
8a771f77 HG |
1145 | case FRINDEX: |
1146 | val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */ | |
1147 | break; | |
1148 | ||
94527ead | 1149 | case CONFIGFLAG: |
94527ead GH |
1150 | val &= 0x1; |
1151 | if (val) { | |
1152 | for(i = 0; i < NB_PORTS; i++) | |
a0a3167a | 1153 | handle_port_owner_write(s, i, 0); |
94527ead GH |
1154 | } |
1155 | break; | |
1156 | ||
1157 | case PERIODICLISTBASE: | |
1158 | if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1159 | fprintf(stderr, | |
1160 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
1161 | " is enabled and HC is enabled\n"); | |
1162 | } | |
94527ead GH |
1163 | break; |
1164 | ||
1165 | case ASYNCLISTADDR: | |
1166 | if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
1167 | fprintf(stderr, | |
1168 | "ehci: ASYNC list address register set while async schedule\n" | |
1169 | " is enabled and HC is enabled\n"); | |
1170 | } | |
94527ead GH |
1171 | break; |
1172 | } | |
1173 | ||
c4f8e211 GH |
1174 | *mmio = val; |
1175 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); | |
94527ead GH |
1176 | } |
1177 | ||
1178 | ||
1179 | // TODO : Put in common header file, duplication from usb-ohci.c | |
1180 | ||
1181 | /* Get an array of dwords from main memory */ | |
68d55358 DG |
1182 | static inline int get_dwords(EHCIState *ehci, uint32_t addr, |
1183 | uint32_t *buf, int num) | |
94527ead GH |
1184 | { |
1185 | int i; | |
1186 | ||
1187 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
4bf80119 | 1188 | pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf)); |
94527ead GH |
1189 | *buf = le32_to_cpu(*buf); |
1190 | } | |
1191 | ||
1192 | return 1; | |
1193 | } | |
1194 | ||
1195 | /* Put an array of dwords in to main memory */ | |
68d55358 DG |
1196 | static inline int put_dwords(EHCIState *ehci, uint32_t addr, |
1197 | uint32_t *buf, int num) | |
94527ead GH |
1198 | { |
1199 | int i; | |
1200 | ||
1201 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1202 | uint32_t tmp = cpu_to_le32(*buf); | |
4bf80119 | 1203 | pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp)); |
94527ead GH |
1204 | } |
1205 | ||
1206 | return 1; | |
1207 | } | |
1208 | ||
1209 | // 4.10.2 | |
1210 | ||
0122f472 | 1211 | static int ehci_qh_do_overlay(EHCIQueue *q) |
94527ead | 1212 | { |
eb36a88e | 1213 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead GH |
1214 | int i; |
1215 | int dtoggle; | |
1216 | int ping; | |
1217 | int eps; | |
1218 | int reload; | |
1219 | ||
eb36a88e GH |
1220 | assert(p != NULL); |
1221 | assert(p->qtdaddr == q->qtdaddr); | |
1222 | ||
94527ead GH |
1223 | // remember values in fields to preserve in qh after overlay |
1224 | ||
0122f472 GH |
1225 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1226 | ping = q->qh.token & QTD_TOKEN_PING; | |
94527ead | 1227 | |
eb36a88e GH |
1228 | q->qh.current_qtd = p->qtdaddr; |
1229 | q->qh.next_qtd = p->qtd.next; | |
1230 | q->qh.altnext_qtd = p->qtd.altnext; | |
1231 | q->qh.token = p->qtd.token; | |
94527ead GH |
1232 | |
1233 | ||
0122f472 | 1234 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
94527ead | 1235 | if (eps == EHCI_QH_EPS_HIGH) { |
0122f472 GH |
1236 | q->qh.token &= ~QTD_TOKEN_PING; |
1237 | q->qh.token |= ping; | |
94527ead GH |
1238 | } |
1239 | ||
0122f472 GH |
1240 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1241 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
94527ead GH |
1242 | |
1243 | for (i = 0; i < 5; i++) { | |
eb36a88e | 1244 | q->qh.bufptr[i] = p->qtd.bufptr[i]; |
94527ead GH |
1245 | } |
1246 | ||
0122f472 | 1247 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { |
94527ead | 1248 | // preserve QH DT bit |
0122f472 GH |
1249 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1250 | q->qh.token |= dtoggle; | |
94527ead GH |
1251 | } |
1252 | ||
0122f472 GH |
1253 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; |
1254 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
94527ead | 1255 | |
68d55358 DG |
1256 | put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, |
1257 | sizeof(EHCIqh) >> 2); | |
94527ead GH |
1258 | |
1259 | return 0; | |
1260 | } | |
1261 | ||
eb36a88e | 1262 | static int ehci_init_transfer(EHCIPacket *p) |
94527ead | 1263 | { |
0ce668bc | 1264 | uint32_t cpage, offset, bytes, plen; |
68d55358 | 1265 | dma_addr_t page; |
94527ead | 1266 | |
eb36a88e GH |
1267 | cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); |
1268 | bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); | |
1269 | offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK; | |
1270 | pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5); | |
94527ead | 1271 | |
0ce668bc GH |
1272 | while (bytes > 0) { |
1273 | if (cpage > 4) { | |
1274 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
1275 | return USB_RET_PROCERR; | |
1276 | } | |
94527ead | 1277 | |
eb36a88e | 1278 | page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK; |
0ce668bc GH |
1279 | page += offset; |
1280 | plen = bytes; | |
1281 | if (plen > 4096 - offset) { | |
1282 | plen = 4096 - offset; | |
1283 | offset = 0; | |
1284 | cpage++; | |
94527ead GH |
1285 | } |
1286 | ||
eb36a88e | 1287 | qemu_sglist_add(&p->sgl, page, plen); |
0ce668bc GH |
1288 | bytes -= plen; |
1289 | } | |
1290 | return 0; | |
1291 | } | |
94527ead | 1292 | |
0ce668bc GH |
1293 | static void ehci_finish_transfer(EHCIQueue *q, int status) |
1294 | { | |
1295 | uint32_t cpage, offset; | |
94527ead | 1296 | |
0ce668bc GH |
1297 | if (status > 0) { |
1298 | /* update cpage & offset */ | |
1299 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); | |
1300 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; | |
94527ead | 1301 | |
0ce668bc GH |
1302 | offset += status; |
1303 | cpage += offset >> QTD_BUFPTR_SH; | |
1304 | offset &= ~QTD_BUFPTR_MASK; | |
94527ead | 1305 | |
0ce668bc GH |
1306 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
1307 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; | |
1308 | q->qh.bufptr[0] |= offset; | |
1309 | } | |
94527ead GH |
1310 | } |
1311 | ||
d47e59b8 | 1312 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
94527ead | 1313 | { |
eb36a88e | 1314 | EHCIPacket *p; |
a0a3167a HG |
1315 | EHCIState *s = port->opaque; |
1316 | uint32_t portsc = s->portsc[port->index]; | |
1317 | ||
1318 | if (portsc & PORTSC_POWNER) { | |
1319 | USBPort *companion = s->companion_ports[port->index]; | |
1320 | companion->ops->complete(companion, packet); | |
1321 | return; | |
1322 | } | |
94527ead | 1323 | |
eb36a88e GH |
1324 | p = container_of(packet, EHCIPacket, packet); |
1325 | trace_usb_ehci_packet_action(p->queue, p, "wakeup"); | |
1326 | assert(p->async == EHCI_ASYNC_INFLIGHT); | |
1327 | p->async = EHCI_ASYNC_FINISHED; | |
1328 | p->usb_status = packet->result; | |
94527ead GH |
1329 | } |
1330 | ||
0122f472 | 1331 | static void ehci_execute_complete(EHCIQueue *q) |
94527ead | 1332 | { |
eb36a88e GH |
1333 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
1334 | ||
1335 | assert(p != NULL); | |
1336 | assert(p->qtdaddr == q->qtdaddr); | |
1337 | assert(p->async != EHCI_ASYNC_INFLIGHT); | |
1338 | p->async = EHCI_ASYNC_NONE; | |
94527ead GH |
1339 | |
1340 | DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", | |
0122f472 | 1341 | q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
94527ead | 1342 | |
eb36a88e GH |
1343 | if (p->usb_status < 0) { |
1344 | switch (p->usb_status) { | |
d61000a8 | 1345 | case USB_RET_IOERROR: |
94527ead | 1346 | case USB_RET_NODEV: |
d2bd525f | 1347 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
dd54cfe0 | 1348 | set_field(&q->qh.token, 0, QTD_TOKEN_CERR); |
d2bd525f | 1349 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1350 | break; |
1351 | case USB_RET_STALL: | |
0122f472 GH |
1352 | q->qh.token |= QTD_TOKEN_HALT; |
1353 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1354 | break; |
1355 | case USB_RET_NAK: | |
553a6a59 HG |
1356 | set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT); |
1357 | return; /* We're not done yet with this transaction */ | |
94527ead | 1358 | case USB_RET_BABBLE: |
d2bd525f | 1359 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
0122f472 | 1360 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1361 | break; |
1362 | default: | |
0122f472 | 1363 | /* should not be triggerable */ |
eb36a88e | 1364 | fprintf(stderr, "USB invalid response %d\n", p->usb_status); |
0122f472 | 1365 | assert(0); |
94527ead GH |
1366 | break; |
1367 | } | |
eb36a88e GH |
1368 | } else if ((p->usb_status > p->tbytes) && (p->pid == USB_TOKEN_IN)) { |
1369 | p->usb_status = USB_RET_BABBLE; | |
dd54cfe0 HG |
1370 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
1371 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead | 1372 | } else { |
94527ead GH |
1373 | // TODO check 4.12 for splits |
1374 | ||
eb36a88e GH |
1375 | if (p->tbytes && p->pid == USB_TOKEN_IN) { |
1376 | p->tbytes -= p->usb_status; | |
94527ead | 1377 | } else { |
eb36a88e | 1378 | p->tbytes = 0; |
94527ead GH |
1379 | } |
1380 | ||
eb36a88e GH |
1381 | DPRINTF("updating tbytes to %d\n", p->tbytes); |
1382 | set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES); | |
94527ead | 1383 | } |
eb36a88e GH |
1384 | ehci_finish_transfer(q, p->usb_status); |
1385 | qemu_sglist_destroy(&p->sgl); | |
1386 | usb_packet_unmap(&p->packet); | |
94527ead | 1387 | |
0122f472 GH |
1388 | q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1389 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
94527ead | 1390 | |
553a6a59 | 1391 | if (q->qh.token & QTD_TOKEN_IOC) { |
0122f472 | 1392 | ehci_record_interrupt(q->ehci, USBSTS_INT); |
94527ead | 1393 | } |
94527ead GH |
1394 | } |
1395 | ||
1396 | // 4.10.3 | |
1397 | ||
0122f472 | 1398 | static int ehci_execute(EHCIQueue *q) |
94527ead | 1399 | { |
eb36a88e | 1400 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead | 1401 | USBDevice *dev; |
079d0b7f | 1402 | USBEndpoint *ep; |
94527ead | 1403 | int ret; |
94527ead GH |
1404 | int endp; |
1405 | int devadr; | |
1406 | ||
eb36a88e GH |
1407 | assert(p != NULL); |
1408 | assert(p->qtdaddr == q->qtdaddr); | |
1409 | ||
0122f472 | 1410 | if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) { |
94527ead GH |
1411 | fprintf(stderr, "Attempting to execute inactive QH\n"); |
1412 | return USB_RET_PROCERR; | |
1413 | } | |
1414 | ||
eb36a88e GH |
1415 | p->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; |
1416 | if (p->tbytes > BUFF_SIZE) { | |
94527ead GH |
1417 | fprintf(stderr, "Request for more bytes than allowed\n"); |
1418 | return USB_RET_PROCERR; | |
1419 | } | |
1420 | ||
eb36a88e GH |
1421 | p->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
1422 | switch (p->pid) { | |
1423 | case 0: | |
1424 | p->pid = USB_TOKEN_OUT; | |
1425 | break; | |
1426 | case 1: | |
1427 | p->pid = USB_TOKEN_IN; | |
1428 | break; | |
1429 | case 2: | |
1430 | p->pid = USB_TOKEN_SETUP; | |
1431 | break; | |
1432 | default: | |
1433 | fprintf(stderr, "bad token\n"); | |
1434 | break; | |
94527ead GH |
1435 | } |
1436 | ||
eb36a88e | 1437 | if (ehci_init_transfer(p) != 0) { |
94527ead GH |
1438 | return USB_RET_PROCERR; |
1439 | } | |
1440 | ||
0122f472 GH |
1441 | endp = get_field(q->qh.epchar, QH_EPCHAR_EP); |
1442 | devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); | |
94527ead | 1443 | |
079d0b7f GH |
1444 | /* TODO: associating device with ehci port */ |
1445 | dev = ehci_find_device(q->ehci, devadr); | |
eb36a88e | 1446 | ep = usb_ep_get(dev, p->pid, endp); |
94527ead | 1447 | |
eb36a88e GH |
1448 | usb_packet_setup(&p->packet, p->pid, ep); |
1449 | usb_packet_map(&p->packet, &p->sgl); | |
0ce668bc | 1450 | |
eb36a88e | 1451 | ret = usb_handle_packet(dev, &p->packet); |
828143c6 GH |
1452 | DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd " |
1453 | "(total %d) endp %x ret %d\n", | |
1454 | q->qhaddr, q->qh.next, q->qtdaddr, q->pid, | |
1455 | q->packet.iov.size, q->tbytes, endp, ret); | |
94527ead GH |
1456 | |
1457 | if (ret > BUFF_SIZE) { | |
1458 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); | |
1459 | return USB_RET_PROCERR; | |
1460 | } | |
1461 | ||
94527ead GH |
1462 | return ret; |
1463 | } | |
1464 | ||
1465 | /* 4.7.2 | |
1466 | */ | |
1467 | ||
1468 | static int ehci_process_itd(EHCIState *ehci, | |
1469 | EHCIitd *itd) | |
1470 | { | |
94527ead | 1471 | USBDevice *dev; |
079d0b7f | 1472 | USBEndpoint *ep; |
94527ead | 1473 | int ret; |
828143c6 | 1474 | uint32_t i, len, pid, dir, devaddr, endp; |
e654887f | 1475 | uint32_t pg, off, ptr1, ptr2, max, mult; |
94527ead GH |
1476 | |
1477 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); | |
e654887f | 1478 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); |
94527ead | 1479 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); |
e654887f GH |
1480 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); |
1481 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
94527ead GH |
1482 | |
1483 | for(i = 0; i < 8; i++) { | |
1484 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
e654887f GH |
1485 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1486 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1487 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1488 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1489 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1490 | ||
1491 | if (len > max * mult) { | |
1492 | len = max * mult; | |
1493 | } | |
94527ead GH |
1494 | |
1495 | if (len > BUFF_SIZE) { | |
1496 | return USB_RET_PROCERR; | |
1497 | } | |
1498 | ||
68d55358 | 1499 | pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); |
e654887f GH |
1500 | if (off + len > 4096) { |
1501 | /* transfer crosses page border */ | |
0ce668bc GH |
1502 | uint32_t len2 = off + len - 4096; |
1503 | uint32_t len1 = len - len2; | |
1504 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len1); | |
1505 | qemu_sglist_add(&ehci->isgl, ptr2, len2); | |
e654887f | 1506 | } else { |
0ce668bc | 1507 | qemu_sglist_add(&ehci->isgl, ptr1 + off, len); |
e654887f | 1508 | } |
94527ead | 1509 | |
0ce668bc | 1510 | pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT; |
94527ead | 1511 | |
079d0b7f GH |
1512 | dev = ehci_find_device(ehci, devaddr); |
1513 | ep = usb_ep_get(dev, pid, endp); | |
aa0568ff GH |
1514 | if (ep->type == USB_ENDPOINT_XFER_ISOC) { |
1515 | usb_packet_setup(&ehci->ipacket, pid, ep); | |
1516 | usb_packet_map(&ehci->ipacket, &ehci->isgl); | |
1517 | ret = usb_handle_packet(dev, &ehci->ipacket); | |
1518 | assert(ret != USB_RET_ASYNC); | |
1519 | usb_packet_unmap(&ehci->ipacket); | |
1520 | } else { | |
1521 | DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); | |
1522 | ret = USB_RET_NAK; | |
1523 | } | |
0ce668bc GH |
1524 | qemu_sglist_destroy(&ehci->isgl); |
1525 | ||
5eafd438 | 1526 | if (ret < 0) { |
df787185 HG |
1527 | switch (ret) { |
1528 | default: | |
1529 | fprintf(stderr, "Unexpected iso usb result: %d\n", ret); | |
1530 | /* Fall through */ | |
d61000a8 | 1531 | case USB_RET_IOERROR: |
df787185 HG |
1532 | case USB_RET_NODEV: |
1533 | /* 3.3.2: XACTERR is only allowed on IN transactions */ | |
1534 | if (dir) { | |
1535 | itd->transact[i] |= ITD_XACT_XACTERR; | |
1536 | ehci_record_interrupt(ehci, USBSTS_ERRINT); | |
1537 | } | |
1538 | break; | |
1539 | case USB_RET_BABBLE: | |
1540 | itd->transact[i] |= ITD_XACT_BABBLE; | |
1541 | ehci_record_interrupt(ehci, USBSTS_ERRINT); | |
1542 | break; | |
5eafd438 HG |
1543 | case USB_RET_NAK: |
1544 | /* no data for us, so do a zero-length transfer */ | |
1545 | ret = 0; | |
1546 | break; | |
1547 | } | |
1548 | } | |
1549 | if (ret >= 0) { | |
1550 | if (!dir) { | |
1551 | /* OUT */ | |
1552 | set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); | |
1553 | } else { | |
1554 | /* IN */ | |
1555 | set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); | |
94527ead GH |
1556 | } |
1557 | } | |
df787185 HG |
1558 | if (itd->transact[i] & ITD_XACT_IOC) { |
1559 | ehci_record_interrupt(ehci, USBSTS_INT); | |
1560 | } | |
e654887f | 1561 | itd->transact[i] &= ~ITD_XACT_ACTIVE; |
94527ead GH |
1562 | } |
1563 | } | |
1564 | return 0; | |
1565 | } | |
1566 | ||
1567 | /* This state is the entry point for asynchronous schedule | |
1568 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1569 | */ | |
26d53979 | 1570 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
94527ead | 1571 | { |
0122f472 | 1572 | EHCIqh qh; |
94527ead GH |
1573 | int i = 0; |
1574 | int again = 0; | |
1575 | uint32_t entry = ehci->asynclistaddr; | |
1576 | ||
1577 | /* set reclamation flag at start event (4.8.6) */ | |
1578 | if (async) { | |
439a97cc | 1579 | ehci_set_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1580 | } |
1581 | ||
4be23939 | 1582 | ehci_queues_rip_unused(ehci, async, 0); |
8ac6d699 | 1583 | |
94527ead GH |
1584 | /* Find the head of the list (4.9.1.1) */ |
1585 | for(i = 0; i < MAX_QH; i++) { | |
68d55358 DG |
1586 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, |
1587 | sizeof(EHCIqh) >> 2); | |
8ac6d699 | 1588 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); |
94527ead | 1589 | |
0122f472 | 1590 | if (qh.epchar & QH_EPCHAR_H) { |
94527ead GH |
1591 | if (async) { |
1592 | entry |= (NLPTR_TYPE_QH << 1); | |
1593 | } | |
1594 | ||
0122f472 | 1595 | ehci_set_fetch_addr(ehci, async, entry); |
26d53979 | 1596 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1597 | again = 1; |
1598 | goto out; | |
1599 | } | |
1600 | ||
0122f472 | 1601 | entry = qh.next; |
94527ead | 1602 | if (entry == ehci->asynclistaddr) { |
94527ead GH |
1603 | break; |
1604 | } | |
1605 | } | |
1606 | ||
1607 | /* no head found for list. */ | |
1608 | ||
26d53979 | 1609 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1610 | |
1611 | out: | |
1612 | return again; | |
1613 | } | |
1614 | ||
1615 | ||
1616 | /* This state is the entry point for periodic schedule processing as | |
1617 | * well as being a continuation state for async processing. | |
1618 | */ | |
26d53979 | 1619 | static int ehci_state_fetchentry(EHCIState *ehci, int async) |
94527ead GH |
1620 | { |
1621 | int again = 0; | |
0122f472 | 1622 | uint32_t entry = ehci_get_fetch_addr(ehci, async); |
94527ead | 1623 | |
2a5ff735 | 1624 | if (NLPTR_TBIT(entry)) { |
26d53979 | 1625 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1626 | goto out; |
1627 | } | |
1628 | ||
1629 | /* section 4.8, only QH in async schedule */ | |
1630 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1631 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1632 | return -1; | |
1633 | } | |
1634 | ||
1635 | switch (NLPTR_TYPE_GET(entry)) { | |
1636 | case NLPTR_TYPE_QH: | |
26d53979 | 1637 | ehci_set_state(ehci, async, EST_FETCHQH); |
94527ead GH |
1638 | again = 1; |
1639 | break; | |
1640 | ||
1641 | case NLPTR_TYPE_ITD: | |
26d53979 | 1642 | ehci_set_state(ehci, async, EST_FETCHITD); |
94527ead GH |
1643 | again = 1; |
1644 | break; | |
1645 | ||
2fe80192 GH |
1646 | case NLPTR_TYPE_STITD: |
1647 | ehci_set_state(ehci, async, EST_FETCHSITD); | |
1648 | again = 1; | |
1649 | break; | |
1650 | ||
94527ead | 1651 | default: |
2fe80192 | 1652 | /* TODO: handle FSTN type */ |
94527ead GH |
1653 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " |
1654 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1655 | return -1; | |
1656 | } | |
1657 | ||
1658 | out: | |
1659 | return again; | |
1660 | } | |
1661 | ||
0122f472 | 1662 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
94527ead | 1663 | { |
eb36a88e | 1664 | EHCIPacket *p; |
0122f472 GH |
1665 | uint32_t entry; |
1666 | EHCIQueue *q; | |
94527ead | 1667 | |
0122f472 | 1668 | entry = ehci_get_fetch_addr(ehci, async); |
df5d5c5c | 1669 | q = ehci_find_queue_by_qh(ehci, entry, async); |
8ac6d699 GH |
1670 | if (NULL == q) { |
1671 | q = ehci_alloc_queue(ehci, async); | |
1672 | } | |
eb36a88e | 1673 | p = QTAILQ_FIRST(&q->packets); |
0122f472 | 1674 | q->qhaddr = entry; |
8ac6d699 GH |
1675 | q->seen++; |
1676 | ||
1677 | if (q->seen > 1) { | |
1678 | /* we are going in circles -- stop processing */ | |
1679 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1680 | q = NULL; | |
1681 | goto out; | |
1682 | } | |
94527ead | 1683 | |
68d55358 DG |
1684 | get_dwords(ehci, NLPTR_GET(q->qhaddr), |
1685 | (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); | |
8ac6d699 GH |
1686 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); |
1687 | ||
eb36a88e | 1688 | if (p && p->async == EHCI_ASYNC_INFLIGHT) { |
8ac6d699 GH |
1689 | /* I/O still in progress -- skip queue */ |
1690 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1691 | goto out; | |
1692 | } | |
eb36a88e | 1693 | if (p && p->async == EHCI_ASYNC_FINISHED) { |
8ac6d699 GH |
1694 | /* I/O finished -- continue processing queue */ |
1695 | trace_usb_ehci_queue_action(q, "resume"); | |
1696 | ehci_set_state(ehci, async, EST_EXECUTING); | |
1697 | goto out; | |
1698 | } | |
0122f472 GH |
1699 | |
1700 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
94527ead GH |
1701 | |
1702 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1703 | if (ehci->usbsts & USBSTS_REC) { | |
439a97cc | 1704 | ehci_clear_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1705 | } else { |
1706 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
0122f472 | 1707 | " - done processing\n", q->qhaddr); |
26d53979 | 1708 | ehci_set_state(ehci, async, EST_ACTIVE); |
0122f472 | 1709 | q = NULL; |
94527ead GH |
1710 | goto out; |
1711 | } | |
1712 | } | |
1713 | ||
1714 | #if EHCI_DEBUG | |
0122f472 | 1715 | if (q->qhaddr != q->qh.next) { |
94527ead | 1716 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", |
0122f472 GH |
1717 | q->qhaddr, |
1718 | q->qh.epchar & QH_EPCHAR_H, | |
1719 | q->qh.token & QTD_TOKEN_HALT, | |
1720 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1721 | q->qh.next); | |
94527ead GH |
1722 | } |
1723 | #endif | |
1724 | ||
0122f472 | 1725 | if (q->qh.token & QTD_TOKEN_HALT) { |
26d53979 | 1726 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead | 1727 | |
2a5ff735 HG |
1728 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && |
1729 | (NLPTR_TBIT(q->qh.current_qtd) == 0)) { | |
0122f472 | 1730 | q->qtdaddr = q->qh.current_qtd; |
26d53979 | 1731 | ehci_set_state(ehci, async, EST_FETCHQTD); |
94527ead GH |
1732 | |
1733 | } else { | |
1734 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
26d53979 | 1735 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
94527ead GH |
1736 | } |
1737 | ||
1738 | out: | |
0122f472 | 1739 | return q; |
94527ead GH |
1740 | } |
1741 | ||
26d53979 | 1742 | static int ehci_state_fetchitd(EHCIState *ehci, int async) |
94527ead | 1743 | { |
0122f472 | 1744 | uint32_t entry; |
94527ead GH |
1745 | EHCIitd itd; |
1746 | ||
0122f472 GH |
1747 | assert(!async); |
1748 | entry = ehci_get_fetch_addr(ehci, async); | |
1749 | ||
68d55358 | 1750 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
94527ead | 1751 | sizeof(EHCIitd) >> 2); |
0122f472 | 1752 | ehci_trace_itd(ehci, entry, &itd); |
94527ead GH |
1753 | |
1754 | if (ehci_process_itd(ehci, &itd) != 0) { | |
1755 | return -1; | |
1756 | } | |
1757 | ||
68d55358 DG |
1758 | put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd, |
1759 | sizeof(EHCIitd) >> 2); | |
0122f472 | 1760 | ehci_set_fetch_addr(ehci, async, itd.next); |
26d53979 | 1761 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1762 | |
1763 | return 1; | |
1764 | } | |
1765 | ||
2fe80192 GH |
1766 | static int ehci_state_fetchsitd(EHCIState *ehci, int async) |
1767 | { | |
1768 | uint32_t entry; | |
1769 | EHCIsitd sitd; | |
1770 | ||
1771 | assert(!async); | |
1772 | entry = ehci_get_fetch_addr(ehci, async); | |
1773 | ||
68d55358 | 1774 | get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd, |
2fe80192 GH |
1775 | sizeof(EHCIsitd) >> 2); |
1776 | ehci_trace_sitd(ehci, entry, &sitd); | |
1777 | ||
1778 | if (!(sitd.results & SITD_RESULTS_ACTIVE)) { | |
1779 | /* siTD is not active, nothing to do */; | |
1780 | } else { | |
1781 | /* TODO: split transfers are not implemented */ | |
1782 | fprintf(stderr, "WARNING: Skipping active siTD\n"); | |
1783 | } | |
1784 | ||
1785 | ehci_set_fetch_addr(ehci, async, sitd.next); | |
1786 | ehci_set_state(ehci, async, EST_FETCHENTRY); | |
1787 | return 1; | |
1788 | } | |
1789 | ||
94527ead | 1790 | /* Section 4.10.2 - paragraph 3 */ |
0122f472 | 1791 | static int ehci_state_advqueue(EHCIQueue *q, int async) |
94527ead GH |
1792 | { |
1793 | #if 0 | |
1794 | /* TO-DO: 4.10.2 - paragraph 2 | |
1795 | * if I-bit is set to 1 and QH is not active | |
1796 | * go to horizontal QH | |
1797 | */ | |
1798 | if (I-bit set) { | |
26d53979 | 1799 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1800 | goto out; |
1801 | } | |
1802 | #endif | |
1803 | ||
1804 | /* | |
1805 | * want data and alt-next qTD is valid | |
1806 | */ | |
0122f472 | 1807 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
0122f472 GH |
1808 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { |
1809 | q->qtdaddr = q->qh.altnext_qtd; | |
1810 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1811 | |
1812 | /* | |
1813 | * next qTD is valid | |
1814 | */ | |
2a5ff735 | 1815 | } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) { |
0122f472 GH |
1816 | q->qtdaddr = q->qh.next_qtd; |
1817 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1818 | |
1819 | /* | |
1820 | * no valid qTD, try next QH | |
1821 | */ | |
1822 | } else { | |
0122f472 | 1823 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1824 | } |
1825 | ||
1826 | return 1; | |
1827 | } | |
1828 | ||
1829 | /* Section 4.10.2 - paragraph 4 */ | |
0122f472 | 1830 | static int ehci_state_fetchqtd(EHCIQueue *q, int async) |
94527ead | 1831 | { |
eb36a88e GH |
1832 | EHCIqtd qtd; |
1833 | EHCIPacket *p; | |
94527ead GH |
1834 | int again = 0; |
1835 | ||
eb36a88e | 1836 | get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd, |
68d55358 | 1837 | sizeof(EHCIqtd) >> 2); |
eb36a88e | 1838 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd); |
94527ead | 1839 | |
eb36a88e GH |
1840 | if (qtd.token & QTD_TOKEN_ACTIVE) { |
1841 | p = ehci_alloc_packet(q); | |
1842 | p->qtdaddr = q->qtdaddr; | |
1843 | p->qtd = qtd; | |
0122f472 | 1844 | ehci_set_state(q->ehci, async, EST_EXECUTE); |
94527ead GH |
1845 | again = 1; |
1846 | } else { | |
0122f472 | 1847 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1848 | again = 1; |
1849 | } | |
1850 | ||
1851 | return again; | |
1852 | } | |
1853 | ||
0122f472 | 1854 | static int ehci_state_horizqh(EHCIQueue *q, int async) |
94527ead GH |
1855 | { |
1856 | int again = 0; | |
1857 | ||
0122f472 GH |
1858 | if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) { |
1859 | ehci_set_fetch_addr(q->ehci, async, q->qh.next); | |
1860 | ehci_set_state(q->ehci, async, EST_FETCHENTRY); | |
94527ead GH |
1861 | again = 1; |
1862 | } else { | |
0122f472 | 1863 | ehci_set_state(q->ehci, async, EST_ACTIVE); |
94527ead GH |
1864 | } |
1865 | ||
1866 | return again; | |
1867 | } | |
1868 | ||
8ac6d699 GH |
1869 | /* |
1870 | * Write the qh back to guest physical memory. This step isn't | |
1871 | * in the EHCI spec but we need to do it since we don't share | |
1872 | * physical memory with our guest VM. | |
1873 | * | |
1874 | * The first three dwords are read-only for the EHCI, so skip them | |
1875 | * when writing back the qh. | |
1876 | */ | |
1877 | static void ehci_flush_qh(EHCIQueue *q) | |
1878 | { | |
1879 | uint32_t *qh = (uint32_t *) &q->qh; | |
1880 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1881 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1882 | ||
68d55358 | 1883 | put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); |
8ac6d699 GH |
1884 | } |
1885 | ||
0122f472 | 1886 | static int ehci_state_execute(EHCIQueue *q, int async) |
94527ead | 1887 | { |
eb36a88e | 1888 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead | 1889 | int again = 0; |
94527ead | 1890 | |
eb36a88e GH |
1891 | assert(p != NULL); |
1892 | assert(p->qtdaddr == q->qtdaddr); | |
1893 | ||
0122f472 | 1894 | if (ehci_qh_do_overlay(q) != 0) { |
94527ead GH |
1895 | return -1; |
1896 | } | |
1897 | ||
94527ead GH |
1898 | // TODO verify enough time remains in the uframe as in 4.4.1.1 |
1899 | // TODO write back ptr to async list when done or out of time | |
1900 | // TODO Windows does not seem to ever set the MULT field | |
1901 | ||
1902 | if (!async) { | |
0122f472 | 1903 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1904 | if (!transactCtr) { |
0122f472 | 1905 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1906 | again = 1; |
1907 | goto out; | |
1908 | } | |
1909 | } | |
1910 | ||
1911 | if (async) { | |
0122f472 | 1912 | ehci_set_usbsts(q->ehci, USBSTS_REC); |
94527ead GH |
1913 | } |
1914 | ||
eb36a88e GH |
1915 | p->usb_status = ehci_execute(q); |
1916 | if (p->usb_status == USB_RET_PROCERR) { | |
94527ead GH |
1917 | again = -1; |
1918 | goto out; | |
1919 | } | |
eb36a88e | 1920 | if (p->usb_status == USB_RET_ASYNC) { |
8ac6d699 GH |
1921 | ehci_flush_qh(q); |
1922 | trace_usb_ehci_queue_action(q, "suspend"); | |
eb36a88e | 1923 | p->async = EHCI_ASYNC_INFLIGHT; |
8ac6d699 | 1924 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead | 1925 | again = 1; |
8ac6d699 | 1926 | goto out; |
94527ead GH |
1927 | } |
1928 | ||
8ac6d699 GH |
1929 | ehci_set_state(q->ehci, async, EST_EXECUTING); |
1930 | again = 1; | |
1931 | ||
94527ead GH |
1932 | out: |
1933 | return again; | |
1934 | } | |
1935 | ||
0122f472 | 1936 | static int ehci_state_executing(EHCIQueue *q, int async) |
94527ead | 1937 | { |
eb36a88e | 1938 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead | 1939 | int again = 0; |
94527ead | 1940 | |
eb36a88e GH |
1941 | assert(p != NULL); |
1942 | assert(p->qtdaddr == q->qtdaddr); | |
1943 | ||
0122f472 | 1944 | ehci_execute_complete(q); |
eb36a88e | 1945 | if (p->usb_status == USB_RET_ASYNC) { |
94527ead GH |
1946 | goto out; |
1947 | } | |
eb36a88e | 1948 | if (p->usb_status == USB_RET_PROCERR) { |
94527ead GH |
1949 | again = -1; |
1950 | goto out; | |
1951 | } | |
1952 | ||
1953 | // 4.10.3 | |
1954 | if (!async) { | |
0122f472 | 1955 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1956 | transactCtr--; |
0122f472 | 1957 | set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); |
94527ead GH |
1958 | // 4.10.3, bottom of page 82, should exit this state when transaction |
1959 | // counter decrements to 0 | |
1960 | } | |
1961 | ||
94527ead | 1962 | /* 4.10.5 */ |
eb36a88e | 1963 | if (p->usb_status == USB_RET_NAK) { |
0122f472 | 1964 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead | 1965 | } else { |
0122f472 | 1966 | ehci_set_state(q->ehci, async, EST_WRITEBACK); |
94527ead GH |
1967 | } |
1968 | ||
1969 | again = 1; | |
1970 | ||
1971 | out: | |
8ac6d699 | 1972 | ehci_flush_qh(q); |
94527ead GH |
1973 | return again; |
1974 | } | |
1975 | ||
1976 | ||
0122f472 | 1977 | static int ehci_state_writeback(EHCIQueue *q, int async) |
94527ead | 1978 | { |
eb36a88e | 1979 | EHCIPacket *p = QTAILQ_FIRST(&q->packets); |
94527ead GH |
1980 | int again = 0; |
1981 | ||
1982 | /* Write back the QTD from the QH area */ | |
eb36a88e GH |
1983 | assert(p != NULL); |
1984 | assert(p->qtdaddr == q->qtdaddr); | |
1985 | ||
1986 | ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd); | |
1987 | put_dwords(q->ehci, NLPTR_GET(p->qtdaddr), (uint32_t *) &q->qh.next_qtd, | |
68d55358 | 1988 | sizeof(EHCIqtd) >> 2); |
eb36a88e | 1989 | ehci_free_packet(p); |
94527ead | 1990 | |
d2bd525f GH |
1991 | /* |
1992 | * EHCI specs say go horizontal here. | |
1993 | * | |
1994 | * We can also advance the queue here for performance reasons. We | |
1995 | * need to take care to only take that shortcut in case we've | |
1996 | * processed the qtd just written back without errors, i.e. halt | |
1997 | * bit is clear. | |
94527ead | 1998 | */ |
d2bd525f GH |
1999 | if (q->qh.token & QTD_TOKEN_HALT) { |
2000 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
2001 | again = 1; | |
2002 | } else { | |
0122f472 | 2003 | ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE); |
94527ead | 2004 | again = 1; |
d2bd525f | 2005 | } |
94527ead GH |
2006 | return again; |
2007 | } | |
2008 | ||
2009 | /* | |
2010 | * This is the state machine that is common to both async and periodic | |
2011 | */ | |
2012 | ||
26d53979 GH |
2013 | static void ehci_advance_state(EHCIState *ehci, |
2014 | int async) | |
94527ead | 2015 | { |
0122f472 | 2016 | EHCIQueue *q = NULL; |
94527ead | 2017 | int again; |
94527ead GH |
2018 | |
2019 | do { | |
26d53979 | 2020 | switch(ehci_get_state(ehci, async)) { |
94527ead | 2021 | case EST_WAITLISTHEAD: |
26d53979 | 2022 | again = ehci_state_waitlisthead(ehci, async); |
94527ead GH |
2023 | break; |
2024 | ||
2025 | case EST_FETCHENTRY: | |
26d53979 | 2026 | again = ehci_state_fetchentry(ehci, async); |
94527ead GH |
2027 | break; |
2028 | ||
2029 | case EST_FETCHQH: | |
0122f472 GH |
2030 | q = ehci_state_fetchqh(ehci, async); |
2031 | again = q ? 1 : 0; | |
94527ead GH |
2032 | break; |
2033 | ||
2034 | case EST_FETCHITD: | |
26d53979 | 2035 | again = ehci_state_fetchitd(ehci, async); |
94527ead GH |
2036 | break; |
2037 | ||
2fe80192 GH |
2038 | case EST_FETCHSITD: |
2039 | again = ehci_state_fetchsitd(ehci, async); | |
2040 | break; | |
2041 | ||
94527ead | 2042 | case EST_ADVANCEQUEUE: |
0122f472 | 2043 | again = ehci_state_advqueue(q, async); |
94527ead GH |
2044 | break; |
2045 | ||
2046 | case EST_FETCHQTD: | |
0122f472 | 2047 | again = ehci_state_fetchqtd(q, async); |
94527ead GH |
2048 | break; |
2049 | ||
2050 | case EST_HORIZONTALQH: | |
0122f472 | 2051 | again = ehci_state_horizqh(q, async); |
94527ead GH |
2052 | break; |
2053 | ||
2054 | case EST_EXECUTE: | |
0122f472 | 2055 | again = ehci_state_execute(q, async); |
94527ead GH |
2056 | break; |
2057 | ||
2058 | case EST_EXECUTING: | |
8ac6d699 | 2059 | assert(q != NULL); |
0122f472 | 2060 | again = ehci_state_executing(q, async); |
94527ead GH |
2061 | break; |
2062 | ||
2063 | case EST_WRITEBACK: | |
b2467216 | 2064 | assert(q != NULL); |
0122f472 | 2065 | again = ehci_state_writeback(q, async); |
94527ead GH |
2066 | break; |
2067 | ||
2068 | default: | |
2069 | fprintf(stderr, "Bad state!\n"); | |
2070 | again = -1; | |
8ac6d699 | 2071 | assert(0); |
94527ead GH |
2072 | break; |
2073 | } | |
2074 | ||
2075 | if (again < 0) { | |
2076 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
2077 | ehci_reset(ehci); | |
2078 | again = 0; | |
2079 | } | |
2080 | } | |
2081 | while (again); | |
2082 | ||
2083 | ehci_commit_interrupt(ehci); | |
94527ead GH |
2084 | } |
2085 | ||
2086 | static void ehci_advance_async_state(EHCIState *ehci) | |
2087 | { | |
df5d5c5c | 2088 | const int async = 1; |
94527ead | 2089 | |
26d53979 | 2090 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2091 | case EST_INACTIVE: |
2092 | if (!(ehci->usbcmd & USBCMD_ASE)) { | |
2093 | break; | |
2094 | } | |
439a97cc | 2095 | ehci_set_usbsts(ehci, USBSTS_ASS); |
26d53979 | 2096 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2097 | // No break, fall through to ACTIVE |
2098 | ||
2099 | case EST_ACTIVE: | |
2100 | if ( !(ehci->usbcmd & USBCMD_ASE)) { | |
e850c2b4 | 2101 | ehci_queues_rip_all(ehci, async); |
439a97cc | 2102 | ehci_clear_usbsts(ehci, USBSTS_ASS); |
26d53979 | 2103 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2104 | break; |
2105 | } | |
2106 | ||
4be23939 | 2107 | /* make sure guest has acknowledged the doorbell interrupt */ |
94527ead GH |
2108 | /* TO-DO: is this really needed? */ |
2109 | if (ehci->usbsts & USBSTS_IAA) { | |
2110 | DPRINTF("IAA status bit still set.\n"); | |
2111 | break; | |
2112 | } | |
2113 | ||
94527ead GH |
2114 | /* check that address register has been set */ |
2115 | if (ehci->asynclistaddr == 0) { | |
2116 | break; | |
2117 | } | |
2118 | ||
26d53979 | 2119 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
26d53979 | 2120 | ehci_advance_state(ehci, async); |
4be23939 HG |
2121 | |
2122 | /* If the doorbell is set, the guest wants to make a change to the | |
2123 | * schedule. The host controller needs to release cached data. | |
2124 | * (section 4.8.2) | |
2125 | */ | |
2126 | if (ehci->usbcmd & USBCMD_IAAD) { | |
2127 | /* Remove all unseen qhs from the async qhs queue */ | |
2128 | ehci_queues_rip_unused(ehci, async, 1); | |
2129 | DPRINTF("ASYNC: doorbell request acknowledged\n"); | |
2130 | ehci->usbcmd &= ~USBCMD_IAAD; | |
2131 | ehci_set_interrupt(ehci, USBSTS_IAA); | |
2132 | } | |
94527ead GH |
2133 | break; |
2134 | ||
2135 | default: | |
2136 | /* this should only be due to a developer mistake */ | |
2137 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
2138 | "Resetting to active\n", ehci->astate); | |
0122f472 | 2139 | assert(0); |
94527ead GH |
2140 | } |
2141 | } | |
2142 | ||
2143 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
2144 | { | |
2145 | uint32_t entry; | |
2146 | uint32_t list; | |
df5d5c5c | 2147 | const int async = 0; |
94527ead GH |
2148 | |
2149 | // 4.6 | |
2150 | ||
26d53979 | 2151 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2152 | case EST_INACTIVE: |
2153 | if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2154 | ehci_set_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2155 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2156 | // No break, fall through to ACTIVE |
2157 | } else | |
2158 | break; | |
2159 | ||
2160 | case EST_ACTIVE: | |
2161 | if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) { | |
e850c2b4 | 2162 | ehci_queues_rip_all(ehci, async); |
439a97cc | 2163 | ehci_clear_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2164 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2165 | break; |
2166 | } | |
2167 | ||
2168 | list = ehci->periodiclistbase & 0xfffff000; | |
2169 | /* check that register has been set */ | |
2170 | if (list == 0) { | |
2171 | break; | |
2172 | } | |
2173 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2174 | ||
4bf80119 | 2175 | pci_dma_read(&ehci->dev, list, &entry, sizeof entry); |
94527ead GH |
2176 | entry = le32_to_cpu(entry); |
2177 | ||
2178 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2179 | ehci->frindex / 8, list, entry); | |
0122f472 | 2180 | ehci_set_fetch_addr(ehci, async,entry); |
26d53979 GH |
2181 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
2182 | ehci_advance_state(ehci, async); | |
4be23939 | 2183 | ehci_queues_rip_unused(ehci, async, 0); |
94527ead GH |
2184 | break; |
2185 | ||
94527ead GH |
2186 | default: |
2187 | /* this should only be due to a developer mistake */ | |
2188 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2189 | "Resetting to active\n", ehci->pstate); | |
0122f472 | 2190 | assert(0); |
94527ead GH |
2191 | } |
2192 | } | |
2193 | ||
2194 | static void ehci_frame_timer(void *opaque) | |
2195 | { | |
2196 | EHCIState *ehci = opaque; | |
2197 | int64_t expire_time, t_now; | |
adddecb1 | 2198 | uint64_t ns_elapsed; |
94527ead | 2199 | int frames; |
94527ead GH |
2200 | int i; |
2201 | int skipped_frames = 0; | |
2202 | ||
94527ead | 2203 | t_now = qemu_get_clock_ns(vm_clock); |
16a2dee6 | 2204 | expire_time = t_now + (get_ticks_per_sec() / ehci->freq); |
94527ead | 2205 | |
adddecb1 GH |
2206 | ns_elapsed = t_now - ehci->last_run_ns; |
2207 | frames = ns_elapsed / FRAME_TIMER_NS; | |
94527ead GH |
2208 | |
2209 | for (i = 0; i < frames; i++) { | |
2210 | if ( !(ehci->usbsts & USBSTS_HALT)) { | |
fcb70eca | 2211 | ehci->frindex += 8; |
94527ead | 2212 | |
58ea88d8 | 2213 | if (ehci->frindex == 0x00002000) { |
94527ead GH |
2214 | ehci_set_interrupt(ehci, USBSTS_FLR); |
2215 | } | |
2216 | ||
58ea88d8 HG |
2217 | if (ehci->frindex == 0x00004000) { |
2218 | ehci_set_interrupt(ehci, USBSTS_FLR); | |
2219 | ehci->frindex = 0; | |
2220 | } | |
94527ead GH |
2221 | } |
2222 | ||
16a2dee6 | 2223 | if (frames - i > ehci->maxframes) { |
94527ead GH |
2224 | skipped_frames++; |
2225 | } else { | |
d0539307 | 2226 | ehci_advance_periodic_state(ehci); |
94527ead GH |
2227 | } |
2228 | ||
adddecb1 | 2229 | ehci->last_run_ns += FRAME_TIMER_NS; |
94527ead GH |
2230 | } |
2231 | ||
2232 | #if 0 | |
2233 | if (skipped_frames) { | |
2234 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2235 | } | |
2236 | #endif | |
2237 | ||
2238 | /* Async is not inside loop since it executes everything it can once | |
2239 | * called | |
2240 | */ | |
d0539307 | 2241 | ehci_advance_async_state(ehci); |
94527ead GH |
2242 | |
2243 | qemu_mod_timer(ehci->frame_timer, expire_time); | |
2244 | } | |
2245 | ||
94527ead | 2246 | |
e57964f5 AK |
2247 | static const MemoryRegionOps ehci_mem_ops = { |
2248 | .old_mmio = { | |
2249 | .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl }, | |
2250 | .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel }, | |
2251 | }, | |
2252 | .endianness = DEVICE_LITTLE_ENDIAN, | |
94527ead GH |
2253 | }; |
2254 | ||
94527ead GH |
2255 | static int usb_ehci_initfn(PCIDevice *dev); |
2256 | ||
2257 | static USBPortOps ehci_port_ops = { | |
2258 | .attach = ehci_attach, | |
2259 | .detach = ehci_detach, | |
4706ab6c | 2260 | .child_detach = ehci_child_detach, |
a0a3167a | 2261 | .wakeup = ehci_wakeup, |
94527ead GH |
2262 | .complete = ehci_async_complete_packet, |
2263 | }; | |
2264 | ||
07771f6f | 2265 | static USBBusOps ehci_bus_ops = { |
a0a3167a | 2266 | .register_companion = ehci_register_companion, |
07771f6f GH |
2267 | }; |
2268 | ||
9490fb06 GH |
2269 | static const VMStateDescription vmstate_ehci = { |
2270 | .name = "ehci", | |
2271 | .unmigratable = 1, | |
2272 | }; | |
2273 | ||
3028376e GH |
2274 | static Property ehci_properties[] = { |
2275 | DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ), | |
2276 | DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), | |
2277 | DEFINE_PROP_END_OF_LIST(), | |
2278 | }; | |
2279 | ||
40021f08 AL |
2280 | static void ehci_class_init(ObjectClass *klass, void *data) |
2281 | { | |
39bffca2 | 2282 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2283 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2284 | ||
2285 | k->init = usb_ehci_initfn; | |
2286 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2287 | k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ | |
2288 | k->revision = 0x10; | |
2289 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2290 | dc->vmsd = &vmstate_ehci; |
2291 | dc->props = ehci_properties; | |
40021f08 AL |
2292 | } |
2293 | ||
39bffca2 AL |
2294 | static TypeInfo ehci_info = { |
2295 | .name = "usb-ehci", | |
2296 | .parent = TYPE_PCI_DEVICE, | |
2297 | .instance_size = sizeof(EHCIState), | |
2298 | .class_init = ehci_class_init, | |
e855761c AL |
2299 | }; |
2300 | ||
40021f08 AL |
2301 | static void ich9_ehci_class_init(ObjectClass *klass, void *data) |
2302 | { | |
39bffca2 | 2303 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
2304 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
2305 | ||
2306 | k->init = usb_ehci_initfn; | |
2307 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
2308 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; | |
2309 | k->revision = 0x03; | |
2310 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
2311 | dc->vmsd = &vmstate_ehci; |
2312 | dc->props = ehci_properties; | |
40021f08 AL |
2313 | } |
2314 | ||
39bffca2 AL |
2315 | static TypeInfo ich9_ehci_info = { |
2316 | .name = "ich9-usb-ehci1", | |
2317 | .parent = TYPE_PCI_DEVICE, | |
2318 | .instance_size = sizeof(EHCIState), | |
2319 | .class_init = ich9_ehci_class_init, | |
94527ead GH |
2320 | }; |
2321 | ||
2322 | static int usb_ehci_initfn(PCIDevice *dev) | |
2323 | { | |
2324 | EHCIState *s = DO_UPCAST(EHCIState, dev, dev); | |
2325 | uint8_t *pci_conf = s->dev.config; | |
2326 | int i; | |
2327 | ||
94527ead | 2328 | pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); |
94527ead GH |
2329 | |
2330 | /* capabilities pointer */ | |
2331 | pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); | |
2332 | //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); | |
2333 | ||
817e0b6f | 2334 | pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ |
94527ead GH |
2335 | pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); |
2336 | pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); | |
2337 | ||
2338 | // pci_conf[0x50] = 0x01; // power management caps | |
2339 | ||
4001f22f | 2340 | pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) |
94527ead GH |
2341 | pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) |
2342 | pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) | |
2343 | ||
2344 | pci_conf[0x64] = 0x00; | |
2345 | pci_conf[0x65] = 0x00; | |
2346 | pci_conf[0x66] = 0x00; | |
2347 | pci_conf[0x67] = 0x00; | |
2348 | pci_conf[0x68] = 0x01; | |
2349 | pci_conf[0x69] = 0x00; | |
2350 | pci_conf[0x6a] = 0x00; | |
2351 | pci_conf[0x6b] = 0x00; // USBLEGSUP | |
2352 | pci_conf[0x6c] = 0x00; | |
2353 | pci_conf[0x6d] = 0x00; | |
2354 | pci_conf[0x6e] = 0x00; | |
2355 | pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS | |
2356 | ||
2357 | // 2.2 host controller interface version | |
2358 | s->mmio[0x00] = (uint8_t) OPREGBASE; | |
2359 | s->mmio[0x01] = 0x00; | |
2360 | s->mmio[0x02] = 0x00; | |
2361 | s->mmio[0x03] = 0x01; // HC version | |
2362 | s->mmio[0x04] = NB_PORTS; // Number of downstream ports | |
2363 | s->mmio[0x05] = 0x00; // No companion ports at present | |
2364 | s->mmio[0x06] = 0x00; | |
2365 | s->mmio[0x07] = 0x00; | |
2366 | s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable | |
2367 | s->mmio[0x09] = 0x68; // EECP | |
2368 | s->mmio[0x0a] = 0x00; | |
2369 | s->mmio[0x0b] = 0x00; | |
2370 | ||
2371 | s->irq = s->dev.irq[3]; | |
2372 | ||
07771f6f | 2373 | usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); |
94527ead GH |
2374 | for(i = 0; i < NB_PORTS; i++) { |
2375 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2376 | USB_SPEED_MASK_HIGH); | |
94527ead GH |
2377 | s->ports[i].dev = 0; |
2378 | } | |
2379 | ||
2380 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
df5d5c5c HG |
2381 | QTAILQ_INIT(&s->aqueues); |
2382 | QTAILQ_INIT(&s->pqueues); | |
94527ead GH |
2383 | |
2384 | qemu_register_reset(ehci_reset, s); | |
2385 | ||
e57964f5 | 2386 | memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE); |
e824b2cc | 2387 | pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); |
94527ead | 2388 | |
94527ead GH |
2389 | return 0; |
2390 | } | |
2391 | ||
83f7d43a | 2392 | static void ehci_register_types(void) |
94527ead | 2393 | { |
39bffca2 AL |
2394 | type_register_static(&ehci_info); |
2395 | type_register_static(&ich9_ehci_info); | |
94527ead | 2396 | } |
83f7d43a AF |
2397 | |
2398 | type_init(ehci_register_types) | |
94527ead GH |
2399 | |
2400 | /* | |
2401 | * vim: expandtab ts=4 | |
2402 | */ |