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Commit | Line | Data |
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bb36d470 FB |
1 | /* |
2 | * USB UHCI controller emulation | |
5fafdf24 | 3 | * |
bb36d470 | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
54f254f9 AL |
6 | * Copyright (c) 2008 Max Krasnyansky |
7 | * Magor rewrite of the UHCI data structures parser and frame processor | |
8 | * Support for fully async operation and multiple outstanding transactions | |
9 | * | |
bb36d470 FB |
10 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
11 | * of this software and associated documentation files (the "Software"), to deal | |
12 | * in the Software without restriction, including without limitation the rights | |
13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
14 | * copies of the Software, and to permit persons to whom the Software is | |
15 | * furnished to do so, subject to the following conditions: | |
16 | * | |
17 | * The above copyright notice and this permission notice shall be included in | |
18 | * all copies or substantial portions of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
26 | * THE SOFTWARE. | |
27 | */ | |
f1ae32a1 GH |
28 | #include "hw/hw.h" |
29 | #include "hw/usb.h" | |
30 | #include "hw/pci.h" | |
87ecb68b | 31 | #include "qemu-timer.h" |
4f4321c1 | 32 | #include "iov.h" |
df5e66ee | 33 | #include "dma.h" |
50dcc0f8 | 34 | #include "trace.h" |
bb36d470 FB |
35 | |
36 | //#define DEBUG | |
54f254f9 | 37 | //#define DEBUG_DUMP_DATA |
bb36d470 | 38 | |
96217e31 TS |
39 | #define UHCI_CMD_FGR (1 << 4) |
40 | #define UHCI_CMD_EGSM (1 << 3) | |
bb36d470 FB |
41 | #define UHCI_CMD_GRESET (1 << 2) |
42 | #define UHCI_CMD_HCRESET (1 << 1) | |
43 | #define UHCI_CMD_RS (1 << 0) | |
44 | ||
45 | #define UHCI_STS_HCHALTED (1 << 5) | |
46 | #define UHCI_STS_HCPERR (1 << 4) | |
47 | #define UHCI_STS_HSERR (1 << 3) | |
48 | #define UHCI_STS_RD (1 << 2) | |
49 | #define UHCI_STS_USBERR (1 << 1) | |
50 | #define UHCI_STS_USBINT (1 << 0) | |
51 | ||
52 | #define TD_CTRL_SPD (1 << 29) | |
53 | #define TD_CTRL_ERROR_SHIFT 27 | |
54 | #define TD_CTRL_IOS (1 << 25) | |
55 | #define TD_CTRL_IOC (1 << 24) | |
56 | #define TD_CTRL_ACTIVE (1 << 23) | |
57 | #define TD_CTRL_STALL (1 << 22) | |
58 | #define TD_CTRL_BABBLE (1 << 20) | |
59 | #define TD_CTRL_NAK (1 << 19) | |
60 | #define TD_CTRL_TIMEOUT (1 << 18) | |
61 | ||
9159f679 | 62 | #define UHCI_PORT_SUSPEND (1 << 12) |
bb36d470 FB |
63 | #define UHCI_PORT_RESET (1 << 9) |
64 | #define UHCI_PORT_LSDA (1 << 8) | |
9159f679 | 65 | #define UHCI_PORT_RD (1 << 6) |
bb36d470 FB |
66 | #define UHCI_PORT_ENC (1 << 3) |
67 | #define UHCI_PORT_EN (1 << 2) | |
68 | #define UHCI_PORT_CSC (1 << 1) | |
69 | #define UHCI_PORT_CCS (1 << 0) | |
70 | ||
9159f679 GH |
71 | #define UHCI_PORT_READ_ONLY (0x1bb) |
72 | #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) | |
73 | ||
bb36d470 FB |
74 | #define FRAME_TIMER_FREQ 1000 |
75 | ||
3200d108 | 76 | #define FRAME_MAX_LOOPS 256 |
bb36d470 FB |
77 | |
78 | #define NB_PORTS 2 | |
79 | ||
60e1b2a6 | 80 | enum { |
0cd178ca GH |
81 | TD_RESULT_STOP_FRAME = 10, |
82 | TD_RESULT_COMPLETE, | |
83 | TD_RESULT_NEXT_QH, | |
4efe4ef3 GH |
84 | TD_RESULT_ASYNC_START, |
85 | TD_RESULT_ASYNC_CONT, | |
60e1b2a6 GH |
86 | }; |
87 | ||
7b5a44c5 | 88 | typedef struct UHCIState UHCIState; |
f8af1e88 GH |
89 | typedef struct UHCIAsync UHCIAsync; |
90 | typedef struct UHCIQueue UHCIQueue; | |
7b5a44c5 | 91 | |
54f254f9 AL |
92 | /* |
93 | * Pending async transaction. | |
94 | * 'packet' must be the first field because completion | |
95 | * handler does "(UHCIAsync *) pkt" cast. | |
96 | */ | |
f8af1e88 GH |
97 | |
98 | struct UHCIAsync { | |
54f254f9 | 99 | USBPacket packet; |
df5e66ee | 100 | QEMUSGList sgl; |
f8af1e88 | 101 | UHCIQueue *queue; |
ddf6583f | 102 | QTAILQ_ENTRY(UHCIAsync) next; |
54f254f9 | 103 | uint32_t td; |
8e65b7c0 | 104 | uint8_t isoc; |
54f254f9 | 105 | uint8_t done; |
f8af1e88 GH |
106 | }; |
107 | ||
108 | struct UHCIQueue { | |
109 | uint32_t token; | |
110 | UHCIState *uhci; | |
111 | QTAILQ_ENTRY(UHCIQueue) next; | |
112 | QTAILQ_HEAD(, UHCIAsync) asyncs; | |
113 | int8_t valid; | |
114 | }; | |
54f254f9 | 115 | |
bb36d470 FB |
116 | typedef struct UHCIPort { |
117 | USBPort port; | |
118 | uint16_t ctrl; | |
bb36d470 FB |
119 | } UHCIPort; |
120 | ||
7b5a44c5 | 121 | struct UHCIState { |
bb36d470 | 122 | PCIDevice dev; |
a03f66e4 | 123 | MemoryRegion io_bar; |
35e4977f | 124 | USBBus bus; /* Note unused when we're a companion controller */ |
bb36d470 FB |
125 | uint16_t cmd; /* cmd register */ |
126 | uint16_t status; | |
127 | uint16_t intr; /* interrupt enable register */ | |
128 | uint16_t frnum; /* frame number */ | |
129 | uint32_t fl_base_addr; /* frame list base address */ | |
130 | uint8_t sof_timing; | |
131 | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ | |
8e65b7c0 | 132 | int64_t expire_time; |
bb36d470 FB |
133 | QEMUTimer *frame_timer; |
134 | UHCIPort ports[NB_PORTS]; | |
4d611c9a PB |
135 | |
136 | /* Interrupts that should be raised at the end of the current frame. */ | |
137 | uint32_t pending_int_mask; | |
54f254f9 AL |
138 | |
139 | /* Active packets */ | |
f8af1e88 | 140 | QTAILQ_HEAD(, UHCIQueue) queues; |
64e58fe5 | 141 | uint8_t num_ports_vmstate; |
35e4977f HG |
142 | |
143 | /* Properties */ | |
144 | char *masterbus; | |
145 | uint32_t firstport; | |
7b5a44c5 | 146 | }; |
bb36d470 FB |
147 | |
148 | typedef struct UHCI_TD { | |
149 | uint32_t link; | |
150 | uint32_t ctrl; /* see TD_CTRL_xxx */ | |
151 | uint32_t token; | |
152 | uint32_t buffer; | |
153 | } UHCI_TD; | |
154 | ||
155 | typedef struct UHCI_QH { | |
156 | uint32_t link; | |
157 | uint32_t el_link; | |
158 | } UHCI_QH; | |
159 | ||
f8af1e88 GH |
160 | static inline int32_t uhci_queue_token(UHCI_TD *td) |
161 | { | |
162 | /* covers ep, dev, pid -> identifies the endpoint */ | |
163 | return td->token & 0x7ffff; | |
164 | } | |
165 | ||
166 | static UHCIQueue *uhci_queue_get(UHCIState *s, UHCI_TD *td) | |
167 | { | |
168 | uint32_t token = uhci_queue_token(td); | |
169 | UHCIQueue *queue; | |
170 | ||
171 | QTAILQ_FOREACH(queue, &s->queues, next) { | |
172 | if (queue->token == token) { | |
173 | return queue; | |
174 | } | |
175 | } | |
176 | ||
177 | queue = g_new0(UHCIQueue, 1); | |
178 | queue->uhci = s; | |
179 | queue->token = token; | |
180 | QTAILQ_INIT(&queue->asyncs); | |
181 | QTAILQ_INSERT_HEAD(&s->queues, queue, next); | |
50dcc0f8 | 182 | trace_usb_uhci_queue_add(queue->token); |
f8af1e88 GH |
183 | return queue; |
184 | } | |
185 | ||
186 | static void uhci_queue_free(UHCIQueue *queue) | |
187 | { | |
188 | UHCIState *s = queue->uhci; | |
189 | ||
50dcc0f8 | 190 | trace_usb_uhci_queue_del(queue->token); |
f8af1e88 GH |
191 | QTAILQ_REMOVE(&s->queues, queue, next); |
192 | g_free(queue); | |
193 | } | |
194 | ||
16ce543e | 195 | static UHCIAsync *uhci_async_alloc(UHCIQueue *queue, uint32_t addr) |
54f254f9 | 196 | { |
326700e3 | 197 | UHCIAsync *async = g_new0(UHCIAsync, 1); |
487414f1 | 198 | |
f8af1e88 | 199 | async->queue = queue; |
16ce543e | 200 | async->td = addr; |
4f4321c1 | 201 | usb_packet_init(&async->packet); |
f8af1e88 | 202 | pci_dma_sglist_init(&async->sgl, &queue->uhci->dev, 1); |
50dcc0f8 | 203 | trace_usb_uhci_packet_add(async->queue->token, async->td); |
54f254f9 AL |
204 | |
205 | return async; | |
206 | } | |
207 | ||
f8af1e88 | 208 | static void uhci_async_free(UHCIAsync *async) |
54f254f9 | 209 | { |
50dcc0f8 | 210 | trace_usb_uhci_packet_del(async->queue->token, async->td); |
4f4321c1 | 211 | usb_packet_cleanup(&async->packet); |
df5e66ee | 212 | qemu_sglist_destroy(&async->sgl); |
7267c094 | 213 | g_free(async); |
54f254f9 AL |
214 | } |
215 | ||
f8af1e88 | 216 | static void uhci_async_link(UHCIAsync *async) |
54f254f9 | 217 | { |
f8af1e88 GH |
218 | UHCIQueue *queue = async->queue; |
219 | QTAILQ_INSERT_TAIL(&queue->asyncs, async, next); | |
50dcc0f8 | 220 | trace_usb_uhci_packet_link_async(async->queue->token, async->td); |
54f254f9 AL |
221 | } |
222 | ||
f8af1e88 | 223 | static void uhci_async_unlink(UHCIAsync *async) |
54f254f9 | 224 | { |
f8af1e88 GH |
225 | UHCIQueue *queue = async->queue; |
226 | QTAILQ_REMOVE(&queue->asyncs, async, next); | |
50dcc0f8 | 227 | trace_usb_uhci_packet_unlink_async(async->queue->token, async->td); |
54f254f9 AL |
228 | } |
229 | ||
f8af1e88 | 230 | static void uhci_async_cancel(UHCIAsync *async) |
54f254f9 | 231 | { |
50dcc0f8 | 232 | trace_usb_uhci_packet_cancel(async->queue->token, async->td, async->done); |
54f254f9 AL |
233 | if (!async->done) |
234 | usb_cancel_packet(&async->packet); | |
f8af1e88 | 235 | uhci_async_free(async); |
54f254f9 AL |
236 | } |
237 | ||
238 | /* | |
239 | * Mark all outstanding async packets as invalid. | |
240 | * This is used for canceling them when TDs are removed by the HCD. | |
241 | */ | |
f8af1e88 | 242 | static void uhci_async_validate_begin(UHCIState *s) |
54f254f9 | 243 | { |
f8af1e88 | 244 | UHCIQueue *queue; |
54f254f9 | 245 | |
f8af1e88 GH |
246 | QTAILQ_FOREACH(queue, &s->queues, next) { |
247 | queue->valid--; | |
54f254f9 | 248 | } |
54f254f9 AL |
249 | } |
250 | ||
251 | /* | |
252 | * Cancel async packets that are no longer valid | |
253 | */ | |
254 | static void uhci_async_validate_end(UHCIState *s) | |
255 | { | |
f8af1e88 GH |
256 | UHCIQueue *queue, *n; |
257 | UHCIAsync *async; | |
54f254f9 | 258 | |
f8af1e88 GH |
259 | QTAILQ_FOREACH_SAFE(queue, &s->queues, next, n) { |
260 | if (queue->valid > 0) { | |
54f254f9 AL |
261 | continue; |
262 | } | |
f8af1e88 GH |
263 | while (!QTAILQ_EMPTY(&queue->asyncs)) { |
264 | async = QTAILQ_FIRST(&queue->asyncs); | |
265 | uhci_async_unlink(async); | |
266 | uhci_async_cancel(async); | |
267 | } | |
268 | uhci_queue_free(queue); | |
54f254f9 AL |
269 | } |
270 | } | |
271 | ||
07771f6f GH |
272 | static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) |
273 | { | |
f8af1e88 | 274 | UHCIQueue *queue; |
07771f6f GH |
275 | UHCIAsync *curr, *n; |
276 | ||
f8af1e88 GH |
277 | QTAILQ_FOREACH(queue, &s->queues, next) { |
278 | QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { | |
279 | if (!usb_packet_is_inflight(&curr->packet) || | |
280 | curr->packet.ep->dev != dev) { | |
281 | continue; | |
282 | } | |
283 | uhci_async_unlink(curr); | |
284 | uhci_async_cancel(curr); | |
07771f6f | 285 | } |
07771f6f GH |
286 | } |
287 | } | |
288 | ||
54f254f9 AL |
289 | static void uhci_async_cancel_all(UHCIState *s) |
290 | { | |
f8af1e88 | 291 | UHCIQueue *queue; |
ddf6583f | 292 | UHCIAsync *curr, *n; |
54f254f9 | 293 | |
f8af1e88 GH |
294 | QTAILQ_FOREACH(queue, &s->queues, next) { |
295 | QTAILQ_FOREACH_SAFE(curr, &queue->asyncs, next, n) { | |
296 | uhci_async_unlink(curr); | |
297 | uhci_async_cancel(curr); | |
298 | } | |
60f8afcb | 299 | uhci_queue_free(queue); |
54f254f9 | 300 | } |
54f254f9 AL |
301 | } |
302 | ||
f8af1e88 | 303 | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, UHCI_TD *td) |
54f254f9 | 304 | { |
f8af1e88 GH |
305 | uint32_t token = uhci_queue_token(td); |
306 | UHCIQueue *queue; | |
ddf6583f | 307 | UHCIAsync *async; |
e8ee3c72 | 308 | |
f8af1e88 GH |
309 | QTAILQ_FOREACH(queue, &s->queues, next) { |
310 | if (queue->token == token) { | |
311 | break; | |
54f254f9 | 312 | } |
f8af1e88 GH |
313 | } |
314 | if (queue == NULL) { | |
315 | return NULL; | |
54f254f9 | 316 | } |
e8ee3c72 | 317 | |
f8af1e88 GH |
318 | QTAILQ_FOREACH(async, &queue->asyncs, next) { |
319 | if (async->td == addr) { | |
320 | return async; | |
321 | } | |
322 | } | |
e8ee3c72 | 323 | |
f8af1e88 | 324 | return NULL; |
54f254f9 AL |
325 | } |
326 | ||
bb36d470 FB |
327 | static void uhci_update_irq(UHCIState *s) |
328 | { | |
329 | int level; | |
330 | if (((s->status2 & 1) && (s->intr & (1 << 2))) || | |
331 | ((s->status2 & 2) && (s->intr & (1 << 3))) || | |
332 | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || | |
333 | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || | |
334 | (s->status & UHCI_STS_HSERR) || | |
335 | (s->status & UHCI_STS_HCPERR)) { | |
336 | level = 1; | |
337 | } else { | |
338 | level = 0; | |
339 | } | |
d537cf6c | 340 | qemu_set_irq(s->dev.irq[3], level); |
bb36d470 FB |
341 | } |
342 | ||
c8075ac3 | 343 | static void uhci_reset(void *opaque) |
bb36d470 | 344 | { |
c8075ac3 | 345 | UHCIState *s = opaque; |
bb36d470 FB |
346 | uint8_t *pci_conf; |
347 | int i; | |
348 | UHCIPort *port; | |
349 | ||
50dcc0f8 | 350 | trace_usb_uhci_reset(); |
6f382b5e | 351 | |
bb36d470 FB |
352 | pci_conf = s->dev.config; |
353 | ||
354 | pci_conf[0x6a] = 0x01; /* usb clock */ | |
355 | pci_conf[0x6b] = 0x00; | |
356 | s->cmd = 0; | |
357 | s->status = 0; | |
358 | s->status2 = 0; | |
359 | s->intr = 0; | |
360 | s->fl_base_addr = 0; | |
361 | s->sof_timing = 64; | |
54f254f9 | 362 | |
bb36d470 FB |
363 | for(i = 0; i < NB_PORTS; i++) { |
364 | port = &s->ports[i]; | |
365 | port->ctrl = 0x0080; | |
891fb2cd | 366 | if (port->port.dev && port->port.dev->attached) { |
d28f4e2d | 367 | usb_port_reset(&port->port); |
618c169b | 368 | } |
bb36d470 | 369 | } |
54f254f9 AL |
370 | |
371 | uhci_async_cancel_all(s); | |
bb36d470 FB |
372 | } |
373 | ||
817afc61 | 374 | static void uhci_pre_save(void *opaque) |
b9dc033c AZ |
375 | { |
376 | UHCIState *s = opaque; | |
b9dc033c | 377 | |
6f382b5e | 378 | uhci_async_cancel_all(s); |
b9dc033c AZ |
379 | } |
380 | ||
817afc61 JQ |
381 | static const VMStateDescription vmstate_uhci_port = { |
382 | .name = "uhci port", | |
383 | .version_id = 1, | |
384 | .minimum_version_id = 1, | |
385 | .minimum_version_id_old = 1, | |
386 | .fields = (VMStateField []) { | |
387 | VMSTATE_UINT16(ctrl, UHCIPort), | |
388 | VMSTATE_END_OF_LIST() | |
389 | } | |
390 | }; | |
391 | ||
392 | static const VMStateDescription vmstate_uhci = { | |
393 | .name = "uhci", | |
6881dd5f | 394 | .version_id = 2, |
817afc61 JQ |
395 | .minimum_version_id = 1, |
396 | .minimum_version_id_old = 1, | |
397 | .pre_save = uhci_pre_save, | |
398 | .fields = (VMStateField []) { | |
399 | VMSTATE_PCI_DEVICE(dev, UHCIState), | |
400 | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), | |
401 | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, | |
402 | vmstate_uhci_port, UHCIPort), | |
403 | VMSTATE_UINT16(cmd, UHCIState), | |
404 | VMSTATE_UINT16(status, UHCIState), | |
405 | VMSTATE_UINT16(intr, UHCIState), | |
406 | VMSTATE_UINT16(frnum, UHCIState), | |
407 | VMSTATE_UINT32(fl_base_addr, UHCIState), | |
408 | VMSTATE_UINT8(sof_timing, UHCIState), | |
409 | VMSTATE_UINT8(status2, UHCIState), | |
410 | VMSTATE_TIMER(frame_timer, UHCIState), | |
6881dd5f | 411 | VMSTATE_INT64_V(expire_time, UHCIState, 2), |
817afc61 JQ |
412 | VMSTATE_END_OF_LIST() |
413 | } | |
414 | }; | |
b9dc033c | 415 | |
bb36d470 FB |
416 | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
417 | { | |
418 | UHCIState *s = opaque; | |
3b46e624 | 419 | |
bb36d470 FB |
420 | addr &= 0x1f; |
421 | switch(addr) { | |
422 | case 0x0c: | |
423 | s->sof_timing = val; | |
424 | break; | |
425 | } | |
426 | } | |
427 | ||
428 | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) | |
429 | { | |
430 | UHCIState *s = opaque; | |
431 | uint32_t val; | |
432 | ||
433 | addr &= 0x1f; | |
434 | switch(addr) { | |
435 | case 0x0c: | |
436 | val = s->sof_timing; | |
d80cfb3f | 437 | break; |
bb36d470 FB |
438 | default: |
439 | val = 0xff; | |
440 | break; | |
441 | } | |
442 | return val; | |
443 | } | |
444 | ||
445 | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) | |
446 | { | |
447 | UHCIState *s = opaque; | |
3b46e624 | 448 | |
bb36d470 | 449 | addr &= 0x1f; |
50dcc0f8 | 450 | trace_usb_uhci_mmio_writew(addr, val); |
54f254f9 | 451 | |
bb36d470 FB |
452 | switch(addr) { |
453 | case 0x00: | |
454 | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { | |
455 | /* start frame processing */ | |
50dcc0f8 | 456 | trace_usb_uhci_schedule_start(); |
94cc916a GH |
457 | s->expire_time = qemu_get_clock_ns(vm_clock) + |
458 | (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
74475455 | 459 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
52328140 | 460 | s->status &= ~UHCI_STS_HCHALTED; |
467d409f | 461 | } else if (!(val & UHCI_CMD_RS)) { |
52328140 | 462 | s->status |= UHCI_STS_HCHALTED; |
bb36d470 FB |
463 | } |
464 | if (val & UHCI_CMD_GRESET) { | |
465 | UHCIPort *port; | |
bb36d470 FB |
466 | int i; |
467 | ||
468 | /* send reset on the USB bus */ | |
469 | for(i = 0; i < NB_PORTS; i++) { | |
470 | port = &s->ports[i]; | |
d28f4e2d | 471 | usb_device_reset(port->port.dev); |
bb36d470 FB |
472 | } |
473 | uhci_reset(s); | |
474 | return; | |
475 | } | |
5e9ab4c4 | 476 | if (val & UHCI_CMD_HCRESET) { |
bb36d470 FB |
477 | uhci_reset(s); |
478 | return; | |
479 | } | |
480 | s->cmd = val; | |
481 | break; | |
482 | case 0x02: | |
483 | s->status &= ~val; | |
484 | /* XXX: the chip spec is not coherent, so we add a hidden | |
485 | register to distinguish between IOC and SPD */ | |
486 | if (val & UHCI_STS_USBINT) | |
487 | s->status2 = 0; | |
488 | uhci_update_irq(s); | |
489 | break; | |
490 | case 0x04: | |
491 | s->intr = val; | |
492 | uhci_update_irq(s); | |
493 | break; | |
494 | case 0x06: | |
495 | if (s->status & UHCI_STS_HCHALTED) | |
496 | s->frnum = val & 0x7ff; | |
497 | break; | |
498 | case 0x10 ... 0x1f: | |
499 | { | |
500 | UHCIPort *port; | |
501 | USBDevice *dev; | |
502 | int n; | |
503 | ||
504 | n = (addr >> 1) & 7; | |
505 | if (n >= NB_PORTS) | |
506 | return; | |
507 | port = &s->ports[n]; | |
a594cfbf | 508 | dev = port->port.dev; |
891fb2cd | 509 | if (dev && dev->attached) { |
bb36d470 | 510 | /* port reset */ |
5fafdf24 | 511 | if ( (val & UHCI_PORT_RESET) && |
bb36d470 | 512 | !(port->ctrl & UHCI_PORT_RESET) ) { |
d28f4e2d | 513 | usb_device_reset(dev); |
bb36d470 FB |
514 | } |
515 | } | |
9159f679 GH |
516 | port->ctrl &= UHCI_PORT_READ_ONLY; |
517 | port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); | |
bb36d470 | 518 | /* some bits are reset when a '1' is written to them */ |
9159f679 | 519 | port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
bb36d470 FB |
520 | } |
521 | break; | |
522 | } | |
523 | } | |
524 | ||
525 | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) | |
526 | { | |
527 | UHCIState *s = opaque; | |
528 | uint32_t val; | |
529 | ||
530 | addr &= 0x1f; | |
531 | switch(addr) { | |
532 | case 0x00: | |
533 | val = s->cmd; | |
534 | break; | |
535 | case 0x02: | |
536 | val = s->status; | |
537 | break; | |
538 | case 0x04: | |
539 | val = s->intr; | |
540 | break; | |
541 | case 0x06: | |
542 | val = s->frnum; | |
543 | break; | |
544 | case 0x10 ... 0x1f: | |
545 | { | |
546 | UHCIPort *port; | |
547 | int n; | |
548 | n = (addr >> 1) & 7; | |
5fafdf24 | 549 | if (n >= NB_PORTS) |
bb36d470 FB |
550 | goto read_default; |
551 | port = &s->ports[n]; | |
552 | val = port->ctrl; | |
553 | } | |
554 | break; | |
555 | default: | |
556 | read_default: | |
557 | val = 0xff7f; /* disabled port */ | |
558 | break; | |
559 | } | |
54f254f9 | 560 | |
50dcc0f8 | 561 | trace_usb_uhci_mmio_readw(addr, val); |
54f254f9 | 562 | |
bb36d470 FB |
563 | return val; |
564 | } | |
565 | ||
566 | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) | |
567 | { | |
568 | UHCIState *s = opaque; | |
569 | ||
570 | addr &= 0x1f; | |
50dcc0f8 | 571 | trace_usb_uhci_mmio_writel(addr, val); |
54f254f9 | 572 | |
bb36d470 FB |
573 | switch(addr) { |
574 | case 0x08: | |
575 | s->fl_base_addr = val & ~0xfff; | |
576 | break; | |
577 | } | |
578 | } | |
579 | ||
580 | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) | |
581 | { | |
582 | UHCIState *s = opaque; | |
583 | uint32_t val; | |
584 | ||
585 | addr &= 0x1f; | |
586 | switch(addr) { | |
587 | case 0x08: | |
588 | val = s->fl_base_addr; | |
589 | break; | |
590 | default: | |
591 | val = 0xffffffff; | |
592 | break; | |
593 | } | |
50dcc0f8 | 594 | trace_usb_uhci_mmio_readl(addr, val); |
bb36d470 FB |
595 | return val; |
596 | } | |
597 | ||
96217e31 TS |
598 | /* signal resume if controller suspended */ |
599 | static void uhci_resume (void *opaque) | |
600 | { | |
601 | UHCIState *s = (UHCIState *)opaque; | |
602 | ||
603 | if (!s) | |
604 | return; | |
605 | ||
606 | if (s->cmd & UHCI_CMD_EGSM) { | |
607 | s->cmd |= UHCI_CMD_FGR; | |
608 | s->status |= UHCI_STS_RD; | |
609 | uhci_update_irq(s); | |
610 | } | |
611 | } | |
612 | ||
618c169b | 613 | static void uhci_attach(USBPort *port1) |
bb36d470 FB |
614 | { |
615 | UHCIState *s = port1->opaque; | |
616 | UHCIPort *port = &s->ports[port1->index]; | |
617 | ||
618c169b GH |
618 | /* set connect status */ |
619 | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; | |
61064870 | 620 | |
618c169b GH |
621 | /* update speed */ |
622 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
623 | port->ctrl |= UHCI_PORT_LSDA; | |
bb36d470 | 624 | } else { |
618c169b GH |
625 | port->ctrl &= ~UHCI_PORT_LSDA; |
626 | } | |
96217e31 | 627 | |
618c169b GH |
628 | uhci_resume(s); |
629 | } | |
96217e31 | 630 | |
618c169b GH |
631 | static void uhci_detach(USBPort *port1) |
632 | { | |
633 | UHCIState *s = port1->opaque; | |
634 | UHCIPort *port = &s->ports[port1->index]; | |
635 | ||
4706ab6c HG |
636 | uhci_async_cancel_device(s, port1->dev); |
637 | ||
618c169b GH |
638 | /* set connect status */ |
639 | if (port->ctrl & UHCI_PORT_CCS) { | |
640 | port->ctrl &= ~UHCI_PORT_CCS; | |
641 | port->ctrl |= UHCI_PORT_CSC; | |
bb36d470 | 642 | } |
618c169b GH |
643 | /* disable port */ |
644 | if (port->ctrl & UHCI_PORT_EN) { | |
645 | port->ctrl &= ~UHCI_PORT_EN; | |
646 | port->ctrl |= UHCI_PORT_ENC; | |
647 | } | |
648 | ||
649 | uhci_resume(s); | |
bb36d470 FB |
650 | } |
651 | ||
4706ab6c HG |
652 | static void uhci_child_detach(USBPort *port1, USBDevice *child) |
653 | { | |
654 | UHCIState *s = port1->opaque; | |
655 | ||
656 | uhci_async_cancel_device(s, child); | |
657 | } | |
658 | ||
d47e59b8 | 659 | static void uhci_wakeup(USBPort *port1) |
9159f679 | 660 | { |
d47e59b8 HG |
661 | UHCIState *s = port1->opaque; |
662 | UHCIPort *port = &s->ports[port1->index]; | |
9159f679 GH |
663 | |
664 | if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { | |
665 | port->ctrl |= UHCI_PORT_RD; | |
666 | uhci_resume(s); | |
667 | } | |
668 | } | |
669 | ||
461700c1 | 670 | static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) |
bb36d470 | 671 | { |
461700c1 GH |
672 | USBDevice *dev; |
673 | int i; | |
54f254f9 | 674 | |
461700c1 | 675 | for (i = 0; i < NB_PORTS; i++) { |
54f254f9 | 676 | UHCIPort *port = &s->ports[i]; |
461700c1 GH |
677 | if (!(port->ctrl & UHCI_PORT_EN)) { |
678 | continue; | |
679 | } | |
680 | dev = usb_find_device(&port->port, addr); | |
681 | if (dev != NULL) { | |
682 | return dev; | |
891fb2cd | 683 | } |
bb36d470 | 684 | } |
461700c1 | 685 | return NULL; |
bb36d470 FB |
686 | } |
687 | ||
d47e59b8 | 688 | static void uhci_async_complete(USBPort *port, USBPacket *packet); |
54f254f9 | 689 | static void uhci_process_frame(UHCIState *s); |
4d611c9a | 690 | |
bb36d470 FB |
691 | /* return -1 if fatal error (frame must be stopped) |
692 | 0 if TD successful | |
693 | 1 if TD unsuccessful or inactive | |
694 | */ | |
54f254f9 | 695 | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
bb36d470 | 696 | { |
54f254f9 | 697 | int len = 0, max_len, err, ret; |
bb36d470 | 698 | uint8_t pid; |
bb36d470 | 699 | |
54f254f9 AL |
700 | max_len = ((td->token >> 21) + 1) & 0x7ff; |
701 | pid = td->token & 0xff; | |
702 | ||
4f4321c1 | 703 | ret = async->packet.result; |
54f254f9 | 704 | |
54f254f9 AL |
705 | if (td->ctrl & TD_CTRL_IOS) |
706 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
bb36d470 | 707 | |
54f254f9 AL |
708 | if (ret < 0) |
709 | goto out; | |
b9dc033c | 710 | |
4f4321c1 | 711 | len = async->packet.result; |
54f254f9 AL |
712 | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
713 | ||
714 | /* The NAK bit may have been set by a previous frame, so clear it | |
715 | here. The docs are somewhat unclear, but win2k relies on this | |
716 | behavior. */ | |
717 | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); | |
5bd2c0d7 PB |
718 | if (td->ctrl & TD_CTRL_IOC) |
719 | *int_mask |= 0x01; | |
54f254f9 AL |
720 | |
721 | if (pid == USB_TOKEN_IN) { | |
722 | if (len > max_len) { | |
54f254f9 AL |
723 | ret = USB_RET_BABBLE; |
724 | goto out; | |
4d611c9a | 725 | } |
b9dc033c | 726 | |
54f254f9 | 727 | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { |
bb36d470 FB |
728 | *int_mask |= 0x02; |
729 | /* short packet: do not update QH */ | |
50dcc0f8 GH |
730 | trace_usb_uhci_packet_complete_shortxfer(async->queue->token, |
731 | async->td); | |
60e1b2a6 | 732 | return TD_RESULT_NEXT_QH; |
bb36d470 | 733 | } |
54f254f9 AL |
734 | } |
735 | ||
736 | /* success */ | |
50dcc0f8 | 737 | trace_usb_uhci_packet_complete_success(async->queue->token, async->td); |
60e1b2a6 | 738 | return TD_RESULT_COMPLETE; |
54f254f9 AL |
739 | |
740 | out: | |
741 | switch(ret) { | |
742 | case USB_RET_STALL: | |
743 | td->ctrl |= TD_CTRL_STALL; | |
744 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
8656954a | 745 | s->status |= UHCI_STS_USBERR; |
0070f095 GH |
746 | if (td->ctrl & TD_CTRL_IOC) { |
747 | *int_mask |= 0x01; | |
748 | } | |
8656954a | 749 | uhci_update_irq(s); |
50dcc0f8 | 750 | trace_usb_uhci_packet_complete_stall(async->queue->token, async->td); |
60e1b2a6 | 751 | return TD_RESULT_NEXT_QH; |
54f254f9 AL |
752 | |
753 | case USB_RET_BABBLE: | |
754 | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; | |
755 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
8656954a | 756 | s->status |= UHCI_STS_USBERR; |
0070f095 GH |
757 | if (td->ctrl & TD_CTRL_IOC) { |
758 | *int_mask |= 0x01; | |
759 | } | |
8656954a | 760 | uhci_update_irq(s); |
54f254f9 | 761 | /* frame interrupted */ |
50dcc0f8 | 762 | trace_usb_uhci_packet_complete_babble(async->queue->token, async->td); |
60e1b2a6 | 763 | return TD_RESULT_STOP_FRAME; |
54f254f9 AL |
764 | |
765 | case USB_RET_NAK: | |
766 | td->ctrl |= TD_CTRL_NAK; | |
767 | if (pid == USB_TOKEN_SETUP) | |
768 | break; | |
60e1b2a6 | 769 | return TD_RESULT_NEXT_QH; |
54f254f9 | 770 | |
d61000a8 | 771 | case USB_RET_IOERROR: |
54f254f9 AL |
772 | case USB_RET_NODEV: |
773 | default: | |
774 | break; | |
775 | } | |
776 | ||
777 | /* Retry the TD if error count is not zero */ | |
778 | ||
779 | td->ctrl |= TD_CTRL_TIMEOUT; | |
780 | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3; | |
781 | if (err != 0) { | |
782 | err--; | |
783 | if (err == 0) { | |
bb36d470 | 784 | td->ctrl &= ~TD_CTRL_ACTIVE; |
54f254f9 | 785 | s->status |= UHCI_STS_USBERR; |
5bd2c0d7 PB |
786 | if (td->ctrl & TD_CTRL_IOC) |
787 | *int_mask |= 0x01; | |
54f254f9 | 788 | uhci_update_irq(s); |
50dcc0f8 GH |
789 | trace_usb_uhci_packet_complete_error(async->queue->token, |
790 | async->td); | |
bb36d470 FB |
791 | } |
792 | } | |
54f254f9 AL |
793 | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) | |
794 | (err << TD_CTRL_ERROR_SHIFT); | |
60e1b2a6 | 795 | return TD_RESULT_NEXT_QH; |
bb36d470 FB |
796 | } |
797 | ||
54f254f9 AL |
798 | static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
799 | { | |
800 | UHCIAsync *async; | |
5d808245 | 801 | int len = 0, max_len; |
f8af1e88 | 802 | uint8_t pid; |
079d0b7f GH |
803 | USBDevice *dev; |
804 | USBEndpoint *ep; | |
54f254f9 AL |
805 | |
806 | /* Is active ? */ | |
807 | if (!(td->ctrl & TD_CTRL_ACTIVE)) | |
60e1b2a6 | 808 | return TD_RESULT_NEXT_QH; |
54f254f9 | 809 | |
f8af1e88 | 810 | async = uhci_async_find_td(s, addr, td); |
54f254f9 AL |
811 | if (async) { |
812 | /* Already submitted */ | |
f8af1e88 | 813 | async->queue->valid = 32; |
54f254f9 AL |
814 | |
815 | if (!async->done) | |
4efe4ef3 | 816 | return TD_RESULT_ASYNC_CONT; |
54f254f9 | 817 | |
f8af1e88 | 818 | uhci_async_unlink(async); |
54f254f9 AL |
819 | goto done; |
820 | } | |
821 | ||
822 | /* Allocate new packet */ | |
16ce543e | 823 | async = uhci_async_alloc(uhci_queue_get(s, td), addr); |
54f254f9 | 824 | if (!async) |
60e1b2a6 | 825 | return TD_RESULT_NEXT_QH; |
54f254f9 | 826 | |
8e65b7c0 DA |
827 | /* valid needs to be large enough to handle 10 frame delay |
828 | * for initial isochronous requests | |
829 | */ | |
f8af1e88 | 830 | async->queue->valid = 32; |
f8af1e88 | 831 | async->isoc = td->ctrl & TD_CTRL_IOS; |
54f254f9 AL |
832 | |
833 | max_len = ((td->token >> 21) + 1) & 0x7ff; | |
834 | pid = td->token & 0xff; | |
835 | ||
079d0b7f GH |
836 | dev = uhci_find_device(s, (td->token >> 8) & 0x7f); |
837 | ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); | |
838 | usb_packet_setup(&async->packet, pid, ep); | |
df5e66ee GH |
839 | qemu_sglist_add(&async->sgl, td->buffer, max_len); |
840 | usb_packet_map(&async->packet, &async->sgl); | |
54f254f9 AL |
841 | |
842 | switch(pid) { | |
843 | case USB_TOKEN_OUT: | |
844 | case USB_TOKEN_SETUP: | |
079d0b7f | 845 | len = usb_handle_packet(dev, &async->packet); |
5d808245 AJ |
846 | if (len >= 0) |
847 | len = max_len; | |
54f254f9 AL |
848 | break; |
849 | ||
850 | case USB_TOKEN_IN: | |
079d0b7f | 851 | len = usb_handle_packet(dev, &async->packet); |
54f254f9 AL |
852 | break; |
853 | ||
854 | default: | |
855 | /* invalid pid : frame interrupted */ | |
f8af1e88 | 856 | uhci_async_free(async); |
54f254f9 AL |
857 | s->status |= UHCI_STS_HCPERR; |
858 | uhci_update_irq(s); | |
60e1b2a6 | 859 | return TD_RESULT_STOP_FRAME; |
54f254f9 AL |
860 | } |
861 | ||
5d808245 | 862 | if (len == USB_RET_ASYNC) { |
f8af1e88 | 863 | uhci_async_link(async); |
4efe4ef3 | 864 | return TD_RESULT_ASYNC_START; |
54f254f9 AL |
865 | } |
866 | ||
4f4321c1 | 867 | async->packet.result = len; |
54f254f9 AL |
868 | |
869 | done: | |
5d808245 | 870 | len = uhci_complete_td(s, td, async, int_mask); |
df5e66ee | 871 | usb_packet_unmap(&async->packet); |
f8af1e88 | 872 | uhci_async_free(async); |
5d808245 | 873 | return len; |
54f254f9 AL |
874 | } |
875 | ||
d47e59b8 | 876 | static void uhci_async_complete(USBPort *port, USBPacket *packet) |
4d611c9a | 877 | { |
7b5a44c5 | 878 | UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
f8af1e88 | 879 | UHCIState *s = async->queue->uhci; |
54f254f9 | 880 | |
8e65b7c0 DA |
881 | if (async->isoc) { |
882 | UHCI_TD td; | |
883 | uint32_t link = async->td; | |
884 | uint32_t int_mask = 0, val; | |
d4c4e6fd | 885 | |
9fe2fd67 | 886 | pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
8e65b7c0 DA |
887 | le32_to_cpus(&td.link); |
888 | le32_to_cpus(&td.ctrl); | |
889 | le32_to_cpus(&td.token); | |
890 | le32_to_cpus(&td.buffer); | |
891 | ||
f8af1e88 | 892 | uhci_async_unlink(async); |
d4c4e6fd | 893 | uhci_complete_td(s, &td, async, &int_mask); |
8e65b7c0 | 894 | s->pending_int_mask |= int_mask; |
54f254f9 | 895 | |
8e65b7c0 DA |
896 | /* update the status bits of the TD */ |
897 | val = cpu_to_le32(td.ctrl); | |
9fe2fd67 | 898 | pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
f8af1e88 | 899 | uhci_async_free(async); |
8e65b7c0 DA |
900 | } else { |
901 | async->done = 1; | |
902 | uhci_process_frame(s); | |
903 | } | |
54f254f9 AL |
904 | } |
905 | ||
906 | static int is_valid(uint32_t link) | |
907 | { | |
908 | return (link & 1) == 0; | |
909 | } | |
910 | ||
911 | static int is_qh(uint32_t link) | |
912 | { | |
913 | return (link & 2) != 0; | |
914 | } | |
915 | ||
916 | static int depth_first(uint32_t link) | |
917 | { | |
918 | return (link & 4) != 0; | |
919 | } | |
920 | ||
921 | /* QH DB used for detecting QH loops */ | |
922 | #define UHCI_MAX_QUEUES 128 | |
923 | typedef struct { | |
924 | uint32_t addr[UHCI_MAX_QUEUES]; | |
925 | int count; | |
926 | } QhDb; | |
927 | ||
928 | static void qhdb_reset(QhDb *db) | |
929 | { | |
930 | db->count = 0; | |
931 | } | |
932 | ||
933 | /* Add QH to DB. Returns 1 if already present or DB is full. */ | |
934 | static int qhdb_insert(QhDb *db, uint32_t addr) | |
935 | { | |
936 | int i; | |
937 | for (i = 0; i < db->count; i++) | |
938 | if (db->addr[i] == addr) | |
939 | return 1; | |
940 | ||
941 | if (db->count >= UHCI_MAX_QUEUES) | |
942 | return 1; | |
943 | ||
944 | db->addr[db->count++] = addr; | |
945 | return 0; | |
946 | } | |
947 | ||
5a248289 GH |
948 | static void uhci_fill_queue(UHCIState *s, UHCI_TD *td) |
949 | { | |
950 | uint32_t int_mask = 0; | |
951 | uint32_t plink = td->link; | |
952 | uint32_t token = uhci_queue_token(td); | |
953 | UHCI_TD ptd; | |
954 | int ret; | |
955 | ||
5a248289 GH |
956 | while (is_valid(plink)) { |
957 | pci_dma_read(&s->dev, plink & ~0xf, &ptd, sizeof(ptd)); | |
958 | le32_to_cpus(&ptd.link); | |
959 | le32_to_cpus(&ptd.ctrl); | |
960 | le32_to_cpus(&ptd.token); | |
961 | le32_to_cpus(&ptd.buffer); | |
962 | if (!(ptd.ctrl & TD_CTRL_ACTIVE)) { | |
963 | break; | |
964 | } | |
965 | if (uhci_queue_token(&ptd) != token) { | |
966 | break; | |
967 | } | |
50dcc0f8 | 968 | trace_usb_uhci_td_queue(plink & ~0xf, ptd.ctrl, ptd.token); |
5a248289 | 969 | ret = uhci_handle_td(s, plink, &ptd, &int_mask); |
4efe4ef3 | 970 | assert(ret == TD_RESULT_ASYNC_START); |
5a248289 GH |
971 | assert(int_mask == 0); |
972 | plink = ptd.link; | |
973 | } | |
974 | } | |
975 | ||
54f254f9 AL |
976 | static void uhci_process_frame(UHCIState *s) |
977 | { | |
978 | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; | |
3200d108 | 979 | uint32_t curr_qh, td_count = 0, bytes_count = 0; |
54f254f9 | 980 | int cnt, ret; |
4d611c9a | 981 | UHCI_TD td; |
54f254f9 AL |
982 | UHCI_QH qh; |
983 | QhDb qhdb; | |
4d611c9a | 984 | |
54f254f9 AL |
985 | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
986 | ||
9fe2fd67 | 987 | pci_dma_read(&s->dev, frame_addr, &link, 4); |
54f254f9 | 988 | le32_to_cpus(&link); |
b9dc033c | 989 | |
54f254f9 AL |
990 | int_mask = 0; |
991 | curr_qh = 0; | |
992 | ||
993 | qhdb_reset(&qhdb); | |
994 | ||
995 | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { | |
996 | if (is_qh(link)) { | |
997 | /* QH */ | |
50dcc0f8 | 998 | trace_usb_uhci_qh_load(link & ~0xf); |
54f254f9 AL |
999 | |
1000 | if (qhdb_insert(&qhdb, link)) { | |
1001 | /* | |
1002 | * We're going in circles. Which is not a bug because | |
3200d108 GH |
1003 | * HCD is allowed to do that as part of the BW management. |
1004 | * | |
1005 | * Stop processing here if | |
1006 | * (a) no transaction has been done since we've been | |
1007 | * here last time, or | |
1008 | * (b) we've reached the usb 1.1 bandwidth, which is | |
1009 | * 1280 bytes/frame. | |
54f254f9 | 1010 | */ |
3200d108 | 1011 | if (td_count == 0) { |
50dcc0f8 | 1012 | trace_usb_uhci_frame_loop_stop_idle(); |
3200d108 GH |
1013 | break; |
1014 | } else if (bytes_count >= 1280) { | |
50dcc0f8 | 1015 | trace_usb_uhci_frame_loop_stop_bandwidth(); |
3200d108 GH |
1016 | break; |
1017 | } else { | |
50dcc0f8 | 1018 | trace_usb_uhci_frame_loop_continue(); |
3200d108 GH |
1019 | td_count = 0; |
1020 | qhdb_reset(&qhdb); | |
1021 | qhdb_insert(&qhdb, link); | |
1022 | } | |
54f254f9 AL |
1023 | } |
1024 | ||
9fe2fd67 | 1025 | pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); |
54f254f9 AL |
1026 | le32_to_cpus(&qh.link); |
1027 | le32_to_cpus(&qh.el_link); | |
1028 | ||
54f254f9 AL |
1029 | if (!is_valid(qh.el_link)) { |
1030 | /* QH w/o elements */ | |
1031 | curr_qh = 0; | |
1032 | link = qh.link; | |
1033 | } else { | |
1034 | /* QH with elements */ | |
1035 | curr_qh = link; | |
1036 | link = qh.el_link; | |
1037 | } | |
1038 | continue; | |
1039 | } | |
1040 | ||
1041 | /* TD */ | |
9fe2fd67 | 1042 | pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
b9dc033c AZ |
1043 | le32_to_cpus(&td.link); |
1044 | le32_to_cpus(&td.ctrl); | |
1045 | le32_to_cpus(&td.token); | |
1046 | le32_to_cpus(&td.buffer); | |
50dcc0f8 | 1047 | trace_usb_uhci_td_load(curr_qh & ~0xf, link & ~0xf, td.ctrl, td.token); |
54f254f9 AL |
1048 | |
1049 | old_td_ctrl = td.ctrl; | |
1050 | ret = uhci_handle_td(s, link, &td, &int_mask); | |
b9dc033c | 1051 | if (old_td_ctrl != td.ctrl) { |
54f254f9 | 1052 | /* update the status bits of the TD */ |
b9dc033c | 1053 | val = cpu_to_le32(td.ctrl); |
9fe2fd67 | 1054 | pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
b9dc033c | 1055 | } |
54f254f9 | 1056 | |
971a5a40 | 1057 | switch (ret) { |
60e1b2a6 | 1058 | case TD_RESULT_STOP_FRAME: /* interrupted frame */ |
971a5a40 | 1059 | goto out; |
b9dc033c | 1060 | |
60e1b2a6 | 1061 | case TD_RESULT_NEXT_QH: |
4efe4ef3 | 1062 | case TD_RESULT_ASYNC_CONT: |
50dcc0f8 | 1063 | trace_usb_uhci_td_nextqh(curr_qh & ~0xf, link & ~0xf); |
54f254f9 AL |
1064 | link = curr_qh ? qh.link : td.link; |
1065 | continue; | |
54f254f9 | 1066 | |
4efe4ef3 | 1067 | case TD_RESULT_ASYNC_START: |
50dcc0f8 | 1068 | trace_usb_uhci_td_async(curr_qh & ~0xf, link & ~0xf); |
5a248289 GH |
1069 | if (is_valid(td.link)) { |
1070 | uhci_fill_queue(s, &td); | |
1071 | } | |
971a5a40 GH |
1072 | link = curr_qh ? qh.link : td.link; |
1073 | continue; | |
54f254f9 | 1074 | |
60e1b2a6 | 1075 | case TD_RESULT_COMPLETE: |
50dcc0f8 | 1076 | trace_usb_uhci_td_complete(curr_qh & ~0xf, link & ~0xf); |
971a5a40 GH |
1077 | link = td.link; |
1078 | td_count++; | |
1079 | bytes_count += (td.ctrl & 0x7ff) + 1; | |
54f254f9 | 1080 | |
971a5a40 GH |
1081 | if (curr_qh) { |
1082 | /* update QH element link */ | |
1083 | qh.el_link = link; | |
1084 | val = cpu_to_le32(qh.el_link); | |
1085 | pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); | |
54f254f9 | 1086 | |
971a5a40 GH |
1087 | if (!depth_first(link)) { |
1088 | /* done with this QH */ | |
971a5a40 GH |
1089 | curr_qh = 0; |
1090 | link = qh.link; | |
1091 | } | |
54f254f9 | 1092 | } |
971a5a40 GH |
1093 | break; |
1094 | ||
1095 | default: | |
1096 | assert(!"unknown return code"); | |
4d611c9a | 1097 | } |
54f254f9 AL |
1098 | |
1099 | /* go to the next entry */ | |
4d611c9a | 1100 | } |
54f254f9 | 1101 | |
971a5a40 | 1102 | out: |
8e65b7c0 | 1103 | s->pending_int_mask |= int_mask; |
4d611c9a PB |
1104 | } |
1105 | ||
bb36d470 FB |
1106 | static void uhci_frame_timer(void *opaque) |
1107 | { | |
1108 | UHCIState *s = opaque; | |
8e65b7c0 DA |
1109 | |
1110 | /* prepare the timer for the next frame */ | |
1111 | s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
bb36d470 FB |
1112 | |
1113 | if (!(s->cmd & UHCI_CMD_RS)) { | |
54f254f9 | 1114 | /* Full stop */ |
50dcc0f8 | 1115 | trace_usb_uhci_schedule_stop(); |
bb36d470 | 1116 | qemu_del_timer(s->frame_timer); |
d9a528db | 1117 | uhci_async_cancel_all(s); |
52328140 FB |
1118 | /* set hchalted bit in status - UHCI11D 2.1.2 */ |
1119 | s->status |= UHCI_STS_HCHALTED; | |
bb36d470 FB |
1120 | return; |
1121 | } | |
54f254f9 AL |
1122 | |
1123 | /* Complete the previous frame */ | |
4d611c9a PB |
1124 | if (s->pending_int_mask) { |
1125 | s->status2 |= s->pending_int_mask; | |
54f254f9 | 1126 | s->status |= UHCI_STS_USBINT; |
4d611c9a PB |
1127 | uhci_update_irq(s); |
1128 | } | |
8e65b7c0 | 1129 | s->pending_int_mask = 0; |
b9dc033c | 1130 | |
54f254f9 AL |
1131 | /* Start new frame */ |
1132 | s->frnum = (s->frnum + 1) & 0x7ff; | |
1133 | ||
50dcc0f8 | 1134 | trace_usb_uhci_frame_start(s->frnum); |
54f254f9 AL |
1135 | |
1136 | uhci_async_validate_begin(s); | |
1137 | ||
1138 | uhci_process_frame(s); | |
1139 | ||
1140 | uhci_async_validate_end(s); | |
b9dc033c | 1141 | |
8e65b7c0 | 1142 | qemu_mod_timer(s->frame_timer, s->expire_time); |
bb36d470 FB |
1143 | } |
1144 | ||
a03f66e4 AK |
1145 | static const MemoryRegionPortio uhci_portio[] = { |
1146 | { 0, 32, 2, .write = uhci_ioport_writew, }, | |
1147 | { 0, 32, 2, .read = uhci_ioport_readw, }, | |
1148 | { 0, 32, 4, .write = uhci_ioport_writel, }, | |
1149 | { 0, 32, 4, .read = uhci_ioport_readl, }, | |
1150 | { 0, 32, 1, .write = uhci_ioport_writeb, }, | |
1151 | { 0, 32, 1, .read = uhci_ioport_readb, }, | |
1152 | PORTIO_END_OF_LIST() | |
1153 | }; | |
1154 | ||
1155 | static const MemoryRegionOps uhci_ioport_ops = { | |
1156 | .old_portio = uhci_portio, | |
1157 | }; | |
bb36d470 | 1158 | |
0d86d2be GH |
1159 | static USBPortOps uhci_port_ops = { |
1160 | .attach = uhci_attach, | |
618c169b | 1161 | .detach = uhci_detach, |
4706ab6c | 1162 | .child_detach = uhci_child_detach, |
9159f679 | 1163 | .wakeup = uhci_wakeup, |
13a9a0d3 | 1164 | .complete = uhci_async_complete, |
0d86d2be GH |
1165 | }; |
1166 | ||
07771f6f | 1167 | static USBBusOps uhci_bus_ops = { |
07771f6f GH |
1168 | }; |
1169 | ||
dc638fad | 1170 | static int usb_uhci_common_initfn(PCIDevice *dev) |
bb36d470 | 1171 | { |
dc638fad | 1172 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
6cf9b6f1 | 1173 | uint8_t *pci_conf = s->dev.config; |
bb36d470 FB |
1174 | int i; |
1175 | ||
db579e9e | 1176 | pci_conf[PCI_CLASS_PROG] = 0x00; |
db579e9e | 1177 | /* TODO: reset value should be 0. */ |
817e0b6f | 1178 | pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */ |
e59d33a7 | 1179 | pci_conf[USB_SBRN] = USB_RELEASE_1; // release number |
3b46e624 | 1180 | |
35e4977f HG |
1181 | if (s->masterbus) { |
1182 | USBPort *ports[NB_PORTS]; | |
1183 | for(i = 0; i < NB_PORTS; i++) { | |
1184 | ports[i] = &s->ports[i].port; | |
1185 | } | |
1186 | if (usb_register_companion(s->masterbus, ports, NB_PORTS, | |
1187 | s->firstport, s, &uhci_port_ops, | |
1188 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { | |
1189 | return -1; | |
1190 | } | |
1191 | } else { | |
1192 | usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); | |
1193 | for (i = 0; i < NB_PORTS; i++) { | |
1194 | usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, | |
1195 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); | |
1196 | } | |
bb36d470 | 1197 | } |
74475455 | 1198 | s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); |
64e58fe5 | 1199 | s->num_ports_vmstate = NB_PORTS; |
f8af1e88 | 1200 | QTAILQ_INIT(&s->queues); |
bb36d470 | 1201 | |
a08d4367 | 1202 | qemu_register_reset(uhci_reset, s); |
bb36d470 | 1203 | |
a03f66e4 | 1204 | memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); |
38ca0f6d PB |
1205 | /* Use region 4 for consistency with real hardware. BSD guests seem |
1206 | to rely on this. */ | |
e824b2cc | 1207 | pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); |
6f382b5e | 1208 | |
6cf9b6f1 | 1209 | return 0; |
bb36d470 | 1210 | } |
afcc3cdf | 1211 | |
30235a54 HC |
1212 | static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1213 | { | |
1214 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1215 | uint8_t *pci_conf = s->dev.config; | |
1216 | ||
30235a54 HC |
1217 | /* USB misc control 1/2 */ |
1218 | pci_set_long(pci_conf + 0x40,0x00001000); | |
1219 | /* PM capability */ | |
1220 | pci_set_long(pci_conf + 0x80,0x00020001); | |
1221 | /* USB legacy support */ | |
1222 | pci_set_long(pci_conf + 0xc0,0x00002000); | |
1223 | ||
dc638fad | 1224 | return usb_uhci_common_initfn(dev); |
30235a54 HC |
1225 | } |
1226 | ||
a03f66e4 AK |
1227 | static int usb_uhci_exit(PCIDevice *dev) |
1228 | { | |
1229 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1230 | ||
1231 | memory_region_destroy(&s->io_bar); | |
1232 | return 0; | |
1233 | } | |
1234 | ||
1b5a7570 GH |
1235 | static Property uhci_properties[] = { |
1236 | DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), | |
1237 | DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), | |
1238 | DEFINE_PROP_END_OF_LIST(), | |
1239 | }; | |
1240 | ||
40021f08 AL |
1241 | static void piix3_uhci_class_init(ObjectClass *klass, void *data) |
1242 | { | |
39bffca2 | 1243 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1244 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1245 | ||
1246 | k->init = usb_uhci_common_initfn; | |
1247 | k->exit = usb_uhci_exit; | |
1248 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1249 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; | |
1250 | k->revision = 0x01; | |
1251 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1252 | dc->vmsd = &vmstate_uhci; |
1253 | dc->props = uhci_properties; | |
40021f08 AL |
1254 | } |
1255 | ||
39bffca2 AL |
1256 | static TypeInfo piix3_uhci_info = { |
1257 | .name = "piix3-usb-uhci", | |
1258 | .parent = TYPE_PCI_DEVICE, | |
1259 | .instance_size = sizeof(UHCIState), | |
1260 | .class_init = piix3_uhci_class_init, | |
e855761c AL |
1261 | }; |
1262 | ||
40021f08 AL |
1263 | static void piix4_uhci_class_init(ObjectClass *klass, void *data) |
1264 | { | |
39bffca2 | 1265 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1266 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1267 | ||
1268 | k->init = usb_uhci_common_initfn; | |
1269 | k->exit = usb_uhci_exit; | |
1270 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1271 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; | |
1272 | k->revision = 0x01; | |
1273 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1274 | dc->vmsd = &vmstate_uhci; |
1275 | dc->props = uhci_properties; | |
40021f08 AL |
1276 | } |
1277 | ||
39bffca2 AL |
1278 | static TypeInfo piix4_uhci_info = { |
1279 | .name = "piix4-usb-uhci", | |
1280 | .parent = TYPE_PCI_DEVICE, | |
1281 | .instance_size = sizeof(UHCIState), | |
1282 | .class_init = piix4_uhci_class_init, | |
e855761c AL |
1283 | }; |
1284 | ||
40021f08 AL |
1285 | static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) |
1286 | { | |
39bffca2 | 1287 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1288 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1289 | ||
1290 | k->init = usb_uhci_vt82c686b_initfn; | |
1291 | k->exit = usb_uhci_exit; | |
1292 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
1293 | k->device_id = PCI_DEVICE_ID_VIA_UHCI; | |
1294 | k->revision = 0x01; | |
1295 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1296 | dc->vmsd = &vmstate_uhci; |
1297 | dc->props = uhci_properties; | |
40021f08 AL |
1298 | } |
1299 | ||
39bffca2 AL |
1300 | static TypeInfo vt82c686b_uhci_info = { |
1301 | .name = "vt82c686b-usb-uhci", | |
1302 | .parent = TYPE_PCI_DEVICE, | |
1303 | .instance_size = sizeof(UHCIState), | |
1304 | .class_init = vt82c686b_uhci_class_init, | |
e855761c AL |
1305 | }; |
1306 | ||
40021f08 AL |
1307 | static void ich9_uhci1_class_init(ObjectClass *klass, void *data) |
1308 | { | |
39bffca2 | 1309 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1310 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1311 | ||
1312 | k->init = usb_uhci_common_initfn; | |
1313 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1314 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; | |
1315 | k->revision = 0x03; | |
1316 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1317 | dc->vmsd = &vmstate_uhci; |
1318 | dc->props = uhci_properties; | |
40021f08 AL |
1319 | } |
1320 | ||
39bffca2 AL |
1321 | static TypeInfo ich9_uhci1_info = { |
1322 | .name = "ich9-usb-uhci1", | |
1323 | .parent = TYPE_PCI_DEVICE, | |
1324 | .instance_size = sizeof(UHCIState), | |
1325 | .class_init = ich9_uhci1_class_init, | |
e855761c AL |
1326 | }; |
1327 | ||
40021f08 AL |
1328 | static void ich9_uhci2_class_init(ObjectClass *klass, void *data) |
1329 | { | |
39bffca2 | 1330 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1331 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1332 | ||
1333 | k->init = usb_uhci_common_initfn; | |
1334 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1335 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; | |
1336 | k->revision = 0x03; | |
1337 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1338 | dc->vmsd = &vmstate_uhci; |
1339 | dc->props = uhci_properties; | |
40021f08 AL |
1340 | } |
1341 | ||
39bffca2 AL |
1342 | static TypeInfo ich9_uhci2_info = { |
1343 | .name = "ich9-usb-uhci2", | |
1344 | .parent = TYPE_PCI_DEVICE, | |
1345 | .instance_size = sizeof(UHCIState), | |
1346 | .class_init = ich9_uhci2_class_init, | |
e855761c AL |
1347 | }; |
1348 | ||
40021f08 AL |
1349 | static void ich9_uhci3_class_init(ObjectClass *klass, void *data) |
1350 | { | |
39bffca2 | 1351 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1352 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1353 | ||
1354 | k->init = usb_uhci_common_initfn; | |
1355 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1356 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; | |
1357 | k->revision = 0x03; | |
1358 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1359 | dc->vmsd = &vmstate_uhci; |
1360 | dc->props = uhci_properties; | |
40021f08 AL |
1361 | } |
1362 | ||
39bffca2 AL |
1363 | static TypeInfo ich9_uhci3_info = { |
1364 | .name = "ich9-usb-uhci3", | |
1365 | .parent = TYPE_PCI_DEVICE, | |
1366 | .instance_size = sizeof(UHCIState), | |
1367 | .class_init = ich9_uhci3_class_init, | |
6cf9b6f1 | 1368 | }; |
afcc3cdf | 1369 | |
83f7d43a | 1370 | static void uhci_register_types(void) |
6cf9b6f1 | 1371 | { |
39bffca2 AL |
1372 | type_register_static(&piix3_uhci_info); |
1373 | type_register_static(&piix4_uhci_info); | |
1374 | type_register_static(&vt82c686b_uhci_info); | |
1375 | type_register_static(&ich9_uhci1_info); | |
1376 | type_register_static(&ich9_uhci2_info); | |
1377 | type_register_static(&ich9_uhci3_info); | |
6cf9b6f1 | 1378 | } |
83f7d43a AF |
1379 | |
1380 | type_init(uhci_register_types) |