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62c6ae04 HM |
1 | /* |
2 | * USB xHCI controller emulation | |
3 | * | |
4 | * Copyright (c) 2011 Securiforest | |
5 | * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> | |
6 | * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 | |
7 | * | |
8 | * This library is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU Lesser General Public | |
10 | * License as published by the Free Software Foundation; either | |
11 | * version 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This library is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * Lesser General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU Lesser General Public | |
19 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
f1ae32a1 | 21 | #include "hw/hw.h" |
1de7afc9 | 22 | #include "qemu/timer.h" |
f1ae32a1 | 23 | #include "hw/usb.h" |
a2cb15b0 MT |
24 | #include "hw/pci/pci.h" |
25 | #include "hw/pci/msi.h" | |
26 | #include "hw/pci/msix.h" | |
2d754a10 | 27 | #include "trace.h" |
62c6ae04 HM |
28 | |
29 | //#define DEBUG_XHCI | |
30 | //#define DEBUG_DATA | |
31 | ||
32 | #ifdef DEBUG_XHCI | |
33 | #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) | |
34 | #else | |
35 | #define DPRINTF(...) do {} while (0) | |
36 | #endif | |
024426ac GH |
37 | #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ |
38 | __func__, __LINE__, _msg); abort(); } while (0) | |
62c6ae04 | 39 | |
d95e74ea GH |
40 | #define MAXPORTS_2 15 |
41 | #define MAXPORTS_3 15 | |
62c6ae04 | 42 | |
0846e635 | 43 | #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) |
d95e74ea GH |
44 | #define MAXSLOTS 64 |
45 | #define MAXINTRS 16 | |
62c6ae04 HM |
46 | |
47 | #define TD_QUEUE 24 | |
62c6ae04 HM |
48 | |
49 | /* Very pessimistic, let's hope it's enough for all cases */ | |
50 | #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS) | |
51 | /* Do not deliver ER Full events. NEC's driver does some things not bound | |
52 | * to the specs when it gets them */ | |
53 | #define ER_FULL_HACK | |
54 | ||
55 | #define LEN_CAP 0x40 | |
62c6ae04 | 56 | #define LEN_OPER (0x400 + 0x10 * MAXPORTS) |
106b214c | 57 | #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) |
62c6ae04 HM |
58 | #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) |
59 | ||
106b214c GH |
60 | #define OFF_OPER LEN_CAP |
61 | #define OFF_RUNTIME 0x1000 | |
62 | #define OFF_DOORBELL 0x2000 | |
4c47f800 GH |
63 | #define OFF_MSIX_TABLE 0x3000 |
64 | #define OFF_MSIX_PBA 0x3800 | |
62c6ae04 | 65 | /* must be power of 2 */ |
106b214c | 66 | #define LEN_REGS 0x4000 |
62c6ae04 | 67 | |
106b214c GH |
68 | #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME |
69 | #error Increase OFF_RUNTIME | |
70 | #endif | |
71 | #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL | |
72 | #error Increase OFF_DOORBELL | |
73 | #endif | |
62c6ae04 HM |
74 | #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS |
75 | # error Increase LEN_REGS | |
76 | #endif | |
77 | ||
62c6ae04 HM |
78 | /* bit definitions */ |
79 | #define USBCMD_RS (1<<0) | |
80 | #define USBCMD_HCRST (1<<1) | |
81 | #define USBCMD_INTE (1<<2) | |
82 | #define USBCMD_HSEE (1<<3) | |
83 | #define USBCMD_LHCRST (1<<7) | |
84 | #define USBCMD_CSS (1<<8) | |
85 | #define USBCMD_CRS (1<<9) | |
86 | #define USBCMD_EWE (1<<10) | |
87 | #define USBCMD_EU3S (1<<11) | |
88 | ||
89 | #define USBSTS_HCH (1<<0) | |
90 | #define USBSTS_HSE (1<<2) | |
91 | #define USBSTS_EINT (1<<3) | |
92 | #define USBSTS_PCD (1<<4) | |
93 | #define USBSTS_SSS (1<<8) | |
94 | #define USBSTS_RSS (1<<9) | |
95 | #define USBSTS_SRE (1<<10) | |
96 | #define USBSTS_CNR (1<<11) | |
97 | #define USBSTS_HCE (1<<12) | |
98 | ||
99 | ||
100 | #define PORTSC_CCS (1<<0) | |
101 | #define PORTSC_PED (1<<1) | |
102 | #define PORTSC_OCA (1<<3) | |
103 | #define PORTSC_PR (1<<4) | |
104 | #define PORTSC_PLS_SHIFT 5 | |
105 | #define PORTSC_PLS_MASK 0xf | |
106 | #define PORTSC_PP (1<<9) | |
107 | #define PORTSC_SPEED_SHIFT 10 | |
108 | #define PORTSC_SPEED_MASK 0xf | |
109 | #define PORTSC_SPEED_FULL (1<<10) | |
110 | #define PORTSC_SPEED_LOW (2<<10) | |
111 | #define PORTSC_SPEED_HIGH (3<<10) | |
112 | #define PORTSC_SPEED_SUPER (4<<10) | |
113 | #define PORTSC_PIC_SHIFT 14 | |
114 | #define PORTSC_PIC_MASK 0x3 | |
115 | #define PORTSC_LWS (1<<16) | |
116 | #define PORTSC_CSC (1<<17) | |
117 | #define PORTSC_PEC (1<<18) | |
118 | #define PORTSC_WRC (1<<19) | |
119 | #define PORTSC_OCC (1<<20) | |
120 | #define PORTSC_PRC (1<<21) | |
121 | #define PORTSC_PLC (1<<22) | |
122 | #define PORTSC_CEC (1<<23) | |
123 | #define PORTSC_CAS (1<<24) | |
124 | #define PORTSC_WCE (1<<25) | |
125 | #define PORTSC_WDE (1<<26) | |
126 | #define PORTSC_WOE (1<<27) | |
127 | #define PORTSC_DR (1<<30) | |
128 | #define PORTSC_WPR (1<<31) | |
129 | ||
130 | #define CRCR_RCS (1<<0) | |
131 | #define CRCR_CS (1<<1) | |
132 | #define CRCR_CA (1<<2) | |
133 | #define CRCR_CRR (1<<3) | |
134 | ||
135 | #define IMAN_IP (1<<0) | |
136 | #define IMAN_IE (1<<1) | |
137 | ||
138 | #define ERDP_EHB (1<<3) | |
139 | ||
140 | #define TRB_SIZE 16 | |
141 | typedef struct XHCITRB { | |
142 | uint64_t parameter; | |
143 | uint32_t status; | |
144 | uint32_t control; | |
59a70ccd | 145 | dma_addr_t addr; |
62c6ae04 HM |
146 | bool ccs; |
147 | } XHCITRB; | |
148 | ||
85e05d82 GH |
149 | enum { |
150 | PLS_U0 = 0, | |
151 | PLS_U1 = 1, | |
152 | PLS_U2 = 2, | |
153 | PLS_U3 = 3, | |
154 | PLS_DISABLED = 4, | |
155 | PLS_RX_DETECT = 5, | |
156 | PLS_INACTIVE = 6, | |
157 | PLS_POLLING = 7, | |
158 | PLS_RECOVERY = 8, | |
159 | PLS_HOT_RESET = 9, | |
160 | PLS_COMPILANCE_MODE = 10, | |
161 | PLS_TEST_MODE = 11, | |
162 | PLS_RESUME = 15, | |
163 | }; | |
62c6ae04 HM |
164 | |
165 | typedef enum TRBType { | |
166 | TRB_RESERVED = 0, | |
167 | TR_NORMAL, | |
168 | TR_SETUP, | |
169 | TR_DATA, | |
170 | TR_STATUS, | |
171 | TR_ISOCH, | |
172 | TR_LINK, | |
173 | TR_EVDATA, | |
174 | TR_NOOP, | |
175 | CR_ENABLE_SLOT, | |
176 | CR_DISABLE_SLOT, | |
177 | CR_ADDRESS_DEVICE, | |
178 | CR_CONFIGURE_ENDPOINT, | |
179 | CR_EVALUATE_CONTEXT, | |
180 | CR_RESET_ENDPOINT, | |
181 | CR_STOP_ENDPOINT, | |
182 | CR_SET_TR_DEQUEUE, | |
183 | CR_RESET_DEVICE, | |
184 | CR_FORCE_EVENT, | |
185 | CR_NEGOTIATE_BW, | |
186 | CR_SET_LATENCY_TOLERANCE, | |
187 | CR_GET_PORT_BANDWIDTH, | |
188 | CR_FORCE_HEADER, | |
189 | CR_NOOP, | |
190 | ER_TRANSFER = 32, | |
191 | ER_COMMAND_COMPLETE, | |
192 | ER_PORT_STATUS_CHANGE, | |
193 | ER_BANDWIDTH_REQUEST, | |
194 | ER_DOORBELL, | |
195 | ER_HOST_CONTROLLER, | |
196 | ER_DEVICE_NOTIFICATION, | |
197 | ER_MFINDEX_WRAP, | |
198 | /* vendor specific bits */ | |
199 | CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48, | |
200 | CR_VENDOR_NEC_FIRMWARE_REVISION = 49, | |
201 | CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, | |
202 | } TRBType; | |
203 | ||
204 | #define CR_LINK TR_LINK | |
205 | ||
206 | typedef enum TRBCCode { | |
207 | CC_INVALID = 0, | |
208 | CC_SUCCESS, | |
209 | CC_DATA_BUFFER_ERROR, | |
210 | CC_BABBLE_DETECTED, | |
211 | CC_USB_TRANSACTION_ERROR, | |
212 | CC_TRB_ERROR, | |
213 | CC_STALL_ERROR, | |
214 | CC_RESOURCE_ERROR, | |
215 | CC_BANDWIDTH_ERROR, | |
216 | CC_NO_SLOTS_ERROR, | |
217 | CC_INVALID_STREAM_TYPE_ERROR, | |
218 | CC_SLOT_NOT_ENABLED_ERROR, | |
219 | CC_EP_NOT_ENABLED_ERROR, | |
220 | CC_SHORT_PACKET, | |
221 | CC_RING_UNDERRUN, | |
222 | CC_RING_OVERRUN, | |
223 | CC_VF_ER_FULL, | |
224 | CC_PARAMETER_ERROR, | |
225 | CC_BANDWIDTH_OVERRUN, | |
226 | CC_CONTEXT_STATE_ERROR, | |
227 | CC_NO_PING_RESPONSE_ERROR, | |
228 | CC_EVENT_RING_FULL_ERROR, | |
229 | CC_INCOMPATIBLE_DEVICE_ERROR, | |
230 | CC_MISSED_SERVICE_ERROR, | |
231 | CC_COMMAND_RING_STOPPED, | |
232 | CC_COMMAND_ABORTED, | |
233 | CC_STOPPED, | |
234 | CC_STOPPED_LENGTH_INVALID, | |
235 | CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, | |
236 | CC_ISOCH_BUFFER_OVERRUN = 31, | |
237 | CC_EVENT_LOST_ERROR, | |
238 | CC_UNDEFINED_ERROR, | |
239 | CC_INVALID_STREAM_ID_ERROR, | |
240 | CC_SECONDARY_BANDWIDTH_ERROR, | |
241 | CC_SPLIT_TRANSACTION_ERROR | |
242 | } TRBCCode; | |
243 | ||
244 | #define TRB_C (1<<0) | |
245 | #define TRB_TYPE_SHIFT 10 | |
246 | #define TRB_TYPE_MASK 0x3f | |
247 | #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) | |
248 | ||
249 | #define TRB_EV_ED (1<<2) | |
250 | ||
251 | #define TRB_TR_ENT (1<<1) | |
252 | #define TRB_TR_ISP (1<<2) | |
253 | #define TRB_TR_NS (1<<3) | |
254 | #define TRB_TR_CH (1<<4) | |
255 | #define TRB_TR_IOC (1<<5) | |
256 | #define TRB_TR_IDT (1<<6) | |
257 | #define TRB_TR_TBC_SHIFT 7 | |
258 | #define TRB_TR_TBC_MASK 0x3 | |
259 | #define TRB_TR_BEI (1<<9) | |
260 | #define TRB_TR_TLBPC_SHIFT 16 | |
261 | #define TRB_TR_TLBPC_MASK 0xf | |
262 | #define TRB_TR_FRAMEID_SHIFT 20 | |
263 | #define TRB_TR_FRAMEID_MASK 0x7ff | |
264 | #define TRB_TR_SIA (1<<31) | |
265 | ||
266 | #define TRB_TR_DIR (1<<16) | |
267 | ||
268 | #define TRB_CR_SLOTID_SHIFT 24 | |
269 | #define TRB_CR_SLOTID_MASK 0xff | |
270 | #define TRB_CR_EPID_SHIFT 16 | |
271 | #define TRB_CR_EPID_MASK 0x1f | |
272 | ||
273 | #define TRB_CR_BSR (1<<9) | |
274 | #define TRB_CR_DC (1<<9) | |
275 | ||
276 | #define TRB_LK_TC (1<<1) | |
277 | ||
2d1de850 GH |
278 | #define TRB_INTR_SHIFT 22 |
279 | #define TRB_INTR_MASK 0x3ff | |
280 | #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) | |
281 | ||
62c6ae04 HM |
282 | #define EP_TYPE_MASK 0x7 |
283 | #define EP_TYPE_SHIFT 3 | |
284 | ||
285 | #define EP_STATE_MASK 0x7 | |
286 | #define EP_DISABLED (0<<0) | |
287 | #define EP_RUNNING (1<<0) | |
288 | #define EP_HALTED (2<<0) | |
289 | #define EP_STOPPED (3<<0) | |
290 | #define EP_ERROR (4<<0) | |
291 | ||
292 | #define SLOT_STATE_MASK 0x1f | |
293 | #define SLOT_STATE_SHIFT 27 | |
294 | #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) | |
295 | #define SLOT_ENABLED 0 | |
296 | #define SLOT_DEFAULT 1 | |
297 | #define SLOT_ADDRESSED 2 | |
298 | #define SLOT_CONFIGURED 3 | |
299 | ||
300 | #define SLOT_CONTEXT_ENTRIES_MASK 0x1f | |
301 | #define SLOT_CONTEXT_ENTRIES_SHIFT 27 | |
302 | ||
1d8a4e69 | 303 | typedef struct XHCIState XHCIState; |
024426ac GH |
304 | typedef struct XHCIStreamContext XHCIStreamContext; |
305 | typedef struct XHCIEPContext XHCIEPContext; | |
1d8a4e69 | 306 | |
85e05d82 GH |
307 | #define get_field(data, field) \ |
308 | (((data) >> field##_SHIFT) & field##_MASK) | |
309 | ||
310 | #define set_field(data, newval, field) do { \ | |
311 | uint32_t val = *data; \ | |
312 | val &= ~(field##_MASK << field##_SHIFT); \ | |
313 | val |= ((newval) & field##_MASK) << field##_SHIFT; \ | |
314 | *data = val; \ | |
315 | } while (0) | |
316 | ||
62c6ae04 HM |
317 | typedef enum EPType { |
318 | ET_INVALID = 0, | |
319 | ET_ISO_OUT, | |
320 | ET_BULK_OUT, | |
321 | ET_INTR_OUT, | |
322 | ET_CONTROL, | |
323 | ET_ISO_IN, | |
324 | ET_BULK_IN, | |
325 | ET_INTR_IN, | |
326 | } EPType; | |
327 | ||
328 | typedef struct XHCIRing { | |
59a70ccd | 329 | dma_addr_t dequeue; |
62c6ae04 HM |
330 | bool ccs; |
331 | } XHCIRing; | |
332 | ||
333 | typedef struct XHCIPort { | |
1d8a4e69 | 334 | XHCIState *xhci; |
62c6ae04 | 335 | uint32_t portsc; |
0846e635 GH |
336 | uint32_t portnr; |
337 | USBPort *uport; | |
338 | uint32_t speedmask; | |
1d8a4e69 GH |
339 | char name[16]; |
340 | MemoryRegion mem; | |
62c6ae04 HM |
341 | } XHCIPort; |
342 | ||
62c6ae04 HM |
343 | typedef struct XHCITransfer { |
344 | XHCIState *xhci; | |
345 | USBPacket packet; | |
d5a15814 | 346 | QEMUSGList sgl; |
7c605a23 GH |
347 | bool running_async; |
348 | bool running_retry; | |
62c6ae04 HM |
349 | bool cancelled; |
350 | bool complete; | |
a6fb2ddb | 351 | bool int_req; |
62c6ae04 HM |
352 | unsigned int iso_pkts; |
353 | unsigned int slotid; | |
354 | unsigned int epid; | |
024426ac | 355 | unsigned int streamid; |
62c6ae04 HM |
356 | bool in_xfer; |
357 | bool iso_xfer; | |
62c6ae04 HM |
358 | |
359 | unsigned int trb_count; | |
360 | unsigned int trb_alloced; | |
361 | XHCITRB *trbs; | |
362 | ||
62c6ae04 HM |
363 | TRBCCode status; |
364 | ||
365 | unsigned int pkts; | |
366 | unsigned int pktsize; | |
367 | unsigned int cur_pkt; | |
3d139684 GH |
368 | |
369 | uint64_t mfindex_kick; | |
62c6ae04 HM |
370 | } XHCITransfer; |
371 | ||
024426ac GH |
372 | struct XHCIStreamContext { |
373 | dma_addr_t pctx; | |
374 | unsigned int sct; | |
375 | XHCIRing ring; | |
376 | XHCIStreamContext *sstreams; | |
377 | }; | |
378 | ||
379 | struct XHCIEPContext { | |
3d139684 GH |
380 | XHCIState *xhci; |
381 | unsigned int slotid; | |
382 | unsigned int epid; | |
383 | ||
62c6ae04 HM |
384 | XHCIRing ring; |
385 | unsigned int next_xfer; | |
386 | unsigned int comp_xfer; | |
387 | XHCITransfer transfers[TD_QUEUE]; | |
7c605a23 | 388 | XHCITransfer *retry; |
62c6ae04 | 389 | EPType type; |
59a70ccd | 390 | dma_addr_t pctx; |
62c6ae04 | 391 | unsigned int max_psize; |
62c6ae04 | 392 | uint32_t state; |
3d139684 | 393 | |
024426ac GH |
394 | /* streams */ |
395 | unsigned int max_pstreams; | |
396 | bool lsa; | |
397 | unsigned int nr_pstreams; | |
398 | XHCIStreamContext *pstreams; | |
399 | ||
3d139684 GH |
400 | /* iso xfer scheduling */ |
401 | unsigned int interval; | |
402 | int64_t mfindex_last; | |
403 | QEMUTimer *kick_timer; | |
024426ac | 404 | }; |
62c6ae04 HM |
405 | |
406 | typedef struct XHCISlot { | |
407 | bool enabled; | |
4034e693 | 408 | bool addressed; |
59a70ccd | 409 | dma_addr_t ctx; |
ccaf87a0 | 410 | USBPort *uport; |
62c6ae04 HM |
411 | XHCIEPContext * eps[31]; |
412 | } XHCISlot; | |
413 | ||
414 | typedef struct XHCIEvent { | |
415 | TRBType type; | |
416 | TRBCCode ccode; | |
417 | uint64_t ptr; | |
418 | uint32_t length; | |
419 | uint32_t flags; | |
420 | uint8_t slotid; | |
421 | uint8_t epid; | |
422 | } XHCIEvent; | |
423 | ||
962d11e1 GH |
424 | typedef struct XHCIInterrupter { |
425 | uint32_t iman; | |
426 | uint32_t imod; | |
427 | uint32_t erstsz; | |
428 | uint32_t erstba_low; | |
429 | uint32_t erstba_high; | |
430 | uint32_t erdp_low; | |
431 | uint32_t erdp_high; | |
432 | ||
433 | bool msix_used, er_pcs, er_full; | |
434 | ||
435 | dma_addr_t er_start; | |
436 | uint32_t er_size; | |
437 | unsigned int er_ep_idx; | |
438 | ||
439 | XHCIEvent ev_buffer[EV_QUEUE]; | |
440 | unsigned int ev_buffer_put; | |
441 | unsigned int ev_buffer_get; | |
442 | ||
443 | } XHCIInterrupter; | |
444 | ||
62c6ae04 HM |
445 | struct XHCIState { |
446 | PCIDevice pci_dev; | |
447 | USBBus bus; | |
448 | qemu_irq irq; | |
449 | MemoryRegion mem; | |
1b067564 GH |
450 | MemoryRegion mem_cap; |
451 | MemoryRegion mem_oper; | |
452 | MemoryRegion mem_runtime; | |
453 | MemoryRegion mem_doorbell; | |
62c6ae04 | 454 | |
0846e635 GH |
455 | /* properties */ |
456 | uint32_t numports_2; | |
457 | uint32_t numports_3; | |
91062ae0 GH |
458 | uint32_t numintrs; |
459 | uint32_t numslots; | |
c5e9b02d | 460 | uint32_t flags; |
0846e635 | 461 | |
62c6ae04 HM |
462 | /* Operational Registers */ |
463 | uint32_t usbcmd; | |
464 | uint32_t usbsts; | |
465 | uint32_t dnctrl; | |
466 | uint32_t crcr_low; | |
467 | uint32_t crcr_high; | |
468 | uint32_t dcbaap_low; | |
469 | uint32_t dcbaap_high; | |
470 | uint32_t config; | |
471 | ||
0846e635 | 472 | USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; |
62c6ae04 HM |
473 | XHCIPort ports[MAXPORTS]; |
474 | XHCISlot slots[MAXSLOTS]; | |
0846e635 | 475 | uint32_t numports; |
62c6ae04 HM |
476 | |
477 | /* Runtime Registers */ | |
01546fa6 GH |
478 | int64_t mfindex_start; |
479 | QEMUTimer *mfwrap_timer; | |
962d11e1 | 480 | XHCIInterrupter intr[MAXINTRS]; |
62c6ae04 HM |
481 | |
482 | XHCIRing cmd_ring; | |
483 | }; | |
484 | ||
485 | typedef struct XHCIEvRingSeg { | |
486 | uint32_t addr_low; | |
487 | uint32_t addr_high; | |
488 | uint32_t size; | |
489 | uint32_t rsvd; | |
490 | } XHCIEvRingSeg; | |
491 | ||
c5e9b02d GH |
492 | enum xhci_flags { |
493 | XHCI_FLAG_USE_MSI = 1, | |
4c47f800 | 494 | XHCI_FLAG_USE_MSI_X, |
c5e9b02d GH |
495 | }; |
496 | ||
01546fa6 | 497 | static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, |
024426ac | 498 | unsigned int epid, unsigned int streamid); |
0bc85da6 GH |
499 | static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, |
500 | unsigned int epid); | |
962d11e1 GH |
501 | static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); |
502 | static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); | |
01546fa6 | 503 | |
f10de44e GH |
504 | static const char *TRBType_names[] = { |
505 | [TRB_RESERVED] = "TRB_RESERVED", | |
506 | [TR_NORMAL] = "TR_NORMAL", | |
507 | [TR_SETUP] = "TR_SETUP", | |
508 | [TR_DATA] = "TR_DATA", | |
509 | [TR_STATUS] = "TR_STATUS", | |
510 | [TR_ISOCH] = "TR_ISOCH", | |
511 | [TR_LINK] = "TR_LINK", | |
512 | [TR_EVDATA] = "TR_EVDATA", | |
513 | [TR_NOOP] = "TR_NOOP", | |
514 | [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", | |
515 | [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", | |
516 | [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", | |
517 | [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", | |
518 | [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", | |
519 | [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", | |
520 | [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", | |
521 | [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", | |
522 | [CR_RESET_DEVICE] = "CR_RESET_DEVICE", | |
523 | [CR_FORCE_EVENT] = "CR_FORCE_EVENT", | |
524 | [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", | |
525 | [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", | |
526 | [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", | |
527 | [CR_FORCE_HEADER] = "CR_FORCE_HEADER", | |
528 | [CR_NOOP] = "CR_NOOP", | |
529 | [ER_TRANSFER] = "ER_TRANSFER", | |
530 | [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", | |
531 | [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", | |
532 | [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", | |
533 | [ER_DOORBELL] = "ER_DOORBELL", | |
534 | [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", | |
535 | [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", | |
536 | [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", | |
537 | [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE", | |
538 | [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", | |
539 | [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", | |
540 | }; | |
541 | ||
873123fe GH |
542 | static const char *TRBCCode_names[] = { |
543 | [CC_INVALID] = "CC_INVALID", | |
544 | [CC_SUCCESS] = "CC_SUCCESS", | |
545 | [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", | |
546 | [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", | |
547 | [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", | |
548 | [CC_TRB_ERROR] = "CC_TRB_ERROR", | |
549 | [CC_STALL_ERROR] = "CC_STALL_ERROR", | |
550 | [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", | |
551 | [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", | |
552 | [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", | |
553 | [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", | |
554 | [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", | |
555 | [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", | |
556 | [CC_SHORT_PACKET] = "CC_SHORT_PACKET", | |
557 | [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", | |
558 | [CC_RING_OVERRUN] = "CC_RING_OVERRUN", | |
559 | [CC_VF_ER_FULL] = "CC_VF_ER_FULL", | |
560 | [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", | |
561 | [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", | |
562 | [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", | |
563 | [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", | |
564 | [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", | |
565 | [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", | |
566 | [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", | |
567 | [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", | |
568 | [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", | |
569 | [CC_STOPPED] = "CC_STOPPED", | |
570 | [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", | |
571 | [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] | |
572 | = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", | |
573 | [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", | |
574 | [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", | |
575 | [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", | |
576 | [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", | |
577 | [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", | |
578 | [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", | |
579 | }; | |
580 | ||
f10de44e GH |
581 | static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) |
582 | { | |
583 | if (index >= llen || list[index] == NULL) { | |
584 | return "???"; | |
585 | } | |
586 | return list[index]; | |
587 | } | |
588 | ||
589 | static const char *trb_name(XHCITRB *trb) | |
590 | { | |
591 | return lookup_name(TRB_TYPE(*trb), TRBType_names, | |
592 | ARRAY_SIZE(TRBType_names)); | |
593 | } | |
f10de44e | 594 | |
873123fe GH |
595 | static const char *event_name(XHCIEvent *event) |
596 | { | |
597 | return lookup_name(event->ccode, TRBCCode_names, | |
598 | ARRAY_SIZE(TRBCCode_names)); | |
599 | } | |
600 | ||
01546fa6 GH |
601 | static uint64_t xhci_mfindex_get(XHCIState *xhci) |
602 | { | |
603 | int64_t now = qemu_get_clock_ns(vm_clock); | |
604 | return (now - xhci->mfindex_start) / 125000; | |
605 | } | |
606 | ||
607 | static void xhci_mfwrap_update(XHCIState *xhci) | |
608 | { | |
609 | const uint32_t bits = USBCMD_RS | USBCMD_EWE; | |
610 | uint32_t mfindex, left; | |
611 | int64_t now; | |
612 | ||
613 | if ((xhci->usbcmd & bits) == bits) { | |
614 | now = qemu_get_clock_ns(vm_clock); | |
615 | mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; | |
616 | left = 0x4000 - mfindex; | |
617 | qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000); | |
618 | } else { | |
619 | qemu_del_timer(xhci->mfwrap_timer); | |
620 | } | |
621 | } | |
622 | ||
623 | static void xhci_mfwrap_timer(void *opaque) | |
624 | { | |
625 | XHCIState *xhci = opaque; | |
626 | XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; | |
627 | ||
962d11e1 | 628 | xhci_event(xhci, &wrap, 0); |
01546fa6 GH |
629 | xhci_mfwrap_update(xhci); |
630 | } | |
62c6ae04 | 631 | |
59a70ccd | 632 | static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) |
62c6ae04 | 633 | { |
59a70ccd DG |
634 | if (sizeof(dma_addr_t) == 4) { |
635 | return low; | |
636 | } else { | |
637 | return low | (((dma_addr_t)high << 16) << 16); | |
638 | } | |
62c6ae04 HM |
639 | } |
640 | ||
59a70ccd | 641 | static inline dma_addr_t xhci_mask64(uint64_t addr) |
62c6ae04 | 642 | { |
59a70ccd DG |
643 | if (sizeof(dma_addr_t) == 4) { |
644 | return addr & 0xffffffff; | |
645 | } else { | |
646 | return addr; | |
647 | } | |
62c6ae04 HM |
648 | } |
649 | ||
616b5d53 DG |
650 | static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, |
651 | uint32_t *buf, size_t len) | |
652 | { | |
653 | int i; | |
654 | ||
655 | assert((len % sizeof(uint32_t)) == 0); | |
656 | ||
657 | pci_dma_read(&xhci->pci_dev, addr, buf, len); | |
658 | ||
659 | for (i = 0; i < (len / sizeof(uint32_t)); i++) { | |
660 | buf[i] = le32_to_cpu(buf[i]); | |
661 | } | |
662 | } | |
663 | ||
664 | static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, | |
665 | uint32_t *buf, size_t len) | |
666 | { | |
667 | int i; | |
668 | uint32_t tmp[len / sizeof(uint32_t)]; | |
669 | ||
670 | assert((len % sizeof(uint32_t)) == 0); | |
671 | ||
672 | for (i = 0; i < (len / sizeof(uint32_t)); i++) { | |
673 | tmp[i] = cpu_to_le32(buf[i]); | |
674 | } | |
675 | pci_dma_write(&xhci->pci_dev, addr, tmp, len); | |
676 | } | |
677 | ||
0846e635 GH |
678 | static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) |
679 | { | |
680 | int index; | |
681 | ||
682 | if (!uport->dev) { | |
683 | return NULL; | |
684 | } | |
685 | switch (uport->dev->speed) { | |
686 | case USB_SPEED_LOW: | |
687 | case USB_SPEED_FULL: | |
688 | case USB_SPEED_HIGH: | |
689 | index = uport->index; | |
690 | break; | |
691 | case USB_SPEED_SUPER: | |
692 | index = uport->index + xhci->numports_2; | |
693 | break; | |
694 | default: | |
695 | return NULL; | |
696 | } | |
697 | return &xhci->ports[index]; | |
698 | } | |
699 | ||
4c4abe7c | 700 | static void xhci_intx_update(XHCIState *xhci) |
62c6ae04 HM |
701 | { |
702 | int level = 0; | |
703 | ||
4c47f800 GH |
704 | if (msix_enabled(&xhci->pci_dev) || |
705 | msi_enabled(&xhci->pci_dev)) { | |
4c4abe7c GH |
706 | return; |
707 | } | |
708 | ||
962d11e1 GH |
709 | if (xhci->intr[0].iman & IMAN_IP && |
710 | xhci->intr[0].iman & IMAN_IE && | |
215bff17 | 711 | xhci->usbcmd & USBCMD_INTE) { |
62c6ae04 HM |
712 | level = 1; |
713 | } | |
714 | ||
4c4abe7c GH |
715 | trace_usb_xhci_irq_intx(level); |
716 | qemu_set_irq(xhci->irq, level); | |
717 | } | |
718 | ||
962d11e1 | 719 | static void xhci_msix_update(XHCIState *xhci, int v) |
4c47f800 GH |
720 | { |
721 | bool enabled; | |
722 | ||
723 | if (!msix_enabled(&xhci->pci_dev)) { | |
724 | return; | |
725 | } | |
726 | ||
962d11e1 GH |
727 | enabled = xhci->intr[v].iman & IMAN_IE; |
728 | if (enabled == xhci->intr[v].msix_used) { | |
4c47f800 GH |
729 | return; |
730 | } | |
731 | ||
732 | if (enabled) { | |
962d11e1 GH |
733 | trace_usb_xhci_irq_msix_use(v); |
734 | msix_vector_use(&xhci->pci_dev, v); | |
735 | xhci->intr[v].msix_used = true; | |
4c47f800 | 736 | } else { |
962d11e1 GH |
737 | trace_usb_xhci_irq_msix_unuse(v); |
738 | msix_vector_unuse(&xhci->pci_dev, v); | |
739 | xhci->intr[v].msix_used = false; | |
4c47f800 GH |
740 | } |
741 | } | |
742 | ||
962d11e1 | 743 | static void xhci_intr_raise(XHCIState *xhci, int v) |
4c4abe7c | 744 | { |
962d11e1 GH |
745 | xhci->intr[v].erdp_low |= ERDP_EHB; |
746 | xhci->intr[v].iman |= IMAN_IP; | |
2cae4119 GH |
747 | xhci->usbsts |= USBSTS_EINT; |
748 | ||
962d11e1 | 749 | if (!(xhci->intr[v].iman & IMAN_IE)) { |
4c4abe7c GH |
750 | return; |
751 | } | |
752 | ||
753 | if (!(xhci->usbcmd & USBCMD_INTE)) { | |
754 | return; | |
755 | } | |
756 | ||
4c47f800 | 757 | if (msix_enabled(&xhci->pci_dev)) { |
962d11e1 GH |
758 | trace_usb_xhci_irq_msix(v); |
759 | msix_notify(&xhci->pci_dev, v); | |
4c47f800 GH |
760 | return; |
761 | } | |
762 | ||
c5e9b02d | 763 | if (msi_enabled(&xhci->pci_dev)) { |
962d11e1 GH |
764 | trace_usb_xhci_irq_msi(v); |
765 | msi_notify(&xhci->pci_dev, v); | |
4c4abe7c | 766 | return; |
62c6ae04 | 767 | } |
4c4abe7c | 768 | |
962d11e1 GH |
769 | if (v == 0) { |
770 | trace_usb_xhci_irq_intx(1); | |
771 | qemu_set_irq(xhci->irq, 1); | |
772 | } | |
62c6ae04 HM |
773 | } |
774 | ||
775 | static inline int xhci_running(XHCIState *xhci) | |
776 | { | |
962d11e1 | 777 | return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full; |
62c6ae04 HM |
778 | } |
779 | ||
780 | static void xhci_die(XHCIState *xhci) | |
781 | { | |
782 | xhci->usbsts |= USBSTS_HCE; | |
783 | fprintf(stderr, "xhci: asserted controller error\n"); | |
784 | } | |
785 | ||
962d11e1 | 786 | static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) |
62c6ae04 | 787 | { |
962d11e1 | 788 | XHCIInterrupter *intr = &xhci->intr[v]; |
62c6ae04 | 789 | XHCITRB ev_trb; |
59a70ccd | 790 | dma_addr_t addr; |
62c6ae04 HM |
791 | |
792 | ev_trb.parameter = cpu_to_le64(event->ptr); | |
793 | ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); | |
794 | ev_trb.control = (event->slotid << 24) | (event->epid << 16) | | |
795 | event->flags | (event->type << TRB_TYPE_SHIFT); | |
962d11e1 | 796 | if (intr->er_pcs) { |
62c6ae04 HM |
797 | ev_trb.control |= TRB_C; |
798 | } | |
799 | ev_trb.control = cpu_to_le32(ev_trb.control); | |
800 | ||
962d11e1 | 801 | trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), |
873123fe GH |
802 | event_name(event), ev_trb.parameter, |
803 | ev_trb.status, ev_trb.control); | |
62c6ae04 | 804 | |
962d11e1 | 805 | addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; |
59a70ccd | 806 | pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE); |
62c6ae04 | 807 | |
962d11e1 GH |
808 | intr->er_ep_idx++; |
809 | if (intr->er_ep_idx >= intr->er_size) { | |
810 | intr->er_ep_idx = 0; | |
811 | intr->er_pcs = !intr->er_pcs; | |
62c6ae04 HM |
812 | } |
813 | } | |
814 | ||
962d11e1 | 815 | static void xhci_events_update(XHCIState *xhci, int v) |
62c6ae04 | 816 | { |
962d11e1 | 817 | XHCIInterrupter *intr = &xhci->intr[v]; |
59a70ccd | 818 | dma_addr_t erdp; |
62c6ae04 HM |
819 | unsigned int dp_idx; |
820 | bool do_irq = 0; | |
821 | ||
822 | if (xhci->usbsts & USBSTS_HCH) { | |
823 | return; | |
824 | } | |
825 | ||
962d11e1 GH |
826 | erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); |
827 | if (erdp < intr->er_start || | |
828 | erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { | |
59a70ccd | 829 | fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); |
962d11e1 GH |
830 | fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", |
831 | v, intr->er_start, intr->er_size); | |
62c6ae04 HM |
832 | xhci_die(xhci); |
833 | return; | |
834 | } | |
962d11e1 GH |
835 | dp_idx = (erdp - intr->er_start) / TRB_SIZE; |
836 | assert(dp_idx < intr->er_size); | |
62c6ae04 HM |
837 | |
838 | /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus | |
839 | * deadlocks when the ER is full. Hack it by holding off events until | |
840 | * the driver decides to free at least half of the ring */ | |
962d11e1 GH |
841 | if (intr->er_full) { |
842 | int er_free = dp_idx - intr->er_ep_idx; | |
62c6ae04 | 843 | if (er_free <= 0) { |
962d11e1 | 844 | er_free += intr->er_size; |
62c6ae04 | 845 | } |
962d11e1 | 846 | if (er_free < (intr->er_size/2)) { |
62c6ae04 HM |
847 | DPRINTF("xhci_events_update(): event ring still " |
848 | "more than half full (hack)\n"); | |
849 | return; | |
850 | } | |
851 | } | |
852 | ||
962d11e1 GH |
853 | while (intr->ev_buffer_put != intr->ev_buffer_get) { |
854 | assert(intr->er_full); | |
855 | if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) { | |
62c6ae04 HM |
856 | DPRINTF("xhci_events_update(): event ring full again\n"); |
857 | #ifndef ER_FULL_HACK | |
858 | XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; | |
962d11e1 | 859 | xhci_write_event(xhci, &full, v); |
62c6ae04 HM |
860 | #endif |
861 | do_irq = 1; | |
862 | break; | |
863 | } | |
962d11e1 GH |
864 | XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get]; |
865 | xhci_write_event(xhci, event, v); | |
866 | intr->ev_buffer_get++; | |
62c6ae04 | 867 | do_irq = 1; |
962d11e1 GH |
868 | if (intr->ev_buffer_get == EV_QUEUE) { |
869 | intr->ev_buffer_get = 0; | |
62c6ae04 HM |
870 | } |
871 | } | |
872 | ||
873 | if (do_irq) { | |
962d11e1 | 874 | xhci_intr_raise(xhci, v); |
62c6ae04 HM |
875 | } |
876 | ||
962d11e1 | 877 | if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) { |
62c6ae04 | 878 | DPRINTF("xhci_events_update(): event ring no longer full\n"); |
962d11e1 | 879 | intr->er_full = 0; |
62c6ae04 | 880 | } |
62c6ae04 HM |
881 | } |
882 | ||
962d11e1 | 883 | static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) |
62c6ae04 | 884 | { |
2d1de850 | 885 | XHCIInterrupter *intr; |
59a70ccd | 886 | dma_addr_t erdp; |
62c6ae04 HM |
887 | unsigned int dp_idx; |
888 | ||
91062ae0 GH |
889 | if (v >= xhci->numintrs) { |
890 | DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); | |
2d1de850 GH |
891 | return; |
892 | } | |
893 | intr = &xhci->intr[v]; | |
894 | ||
962d11e1 | 895 | if (intr->er_full) { |
62c6ae04 | 896 | DPRINTF("xhci_event(): ER full, queueing\n"); |
962d11e1 | 897 | if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { |
62c6ae04 HM |
898 | fprintf(stderr, "xhci: event queue full, dropping event!\n"); |
899 | return; | |
900 | } | |
962d11e1 GH |
901 | intr->ev_buffer[intr->ev_buffer_put++] = *event; |
902 | if (intr->ev_buffer_put == EV_QUEUE) { | |
903 | intr->ev_buffer_put = 0; | |
62c6ae04 HM |
904 | } |
905 | return; | |
906 | } | |
907 | ||
962d11e1 GH |
908 | erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); |
909 | if (erdp < intr->er_start || | |
910 | erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { | |
59a70ccd | 911 | fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); |
962d11e1 GH |
912 | fprintf(stderr, "xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", |
913 | v, intr->er_start, intr->er_size); | |
62c6ae04 HM |
914 | xhci_die(xhci); |
915 | return; | |
916 | } | |
917 | ||
962d11e1 GH |
918 | dp_idx = (erdp - intr->er_start) / TRB_SIZE; |
919 | assert(dp_idx < intr->er_size); | |
62c6ae04 | 920 | |
962d11e1 | 921 | if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) { |
62c6ae04 HM |
922 | DPRINTF("xhci_event(): ER full, queueing\n"); |
923 | #ifndef ER_FULL_HACK | |
924 | XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; | |
925 | xhci_write_event(xhci, &full); | |
926 | #endif | |
962d11e1 GH |
927 | intr->er_full = 1; |
928 | if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) { | |
62c6ae04 HM |
929 | fprintf(stderr, "xhci: event queue full, dropping event!\n"); |
930 | return; | |
931 | } | |
962d11e1 GH |
932 | intr->ev_buffer[intr->ev_buffer_put++] = *event; |
933 | if (intr->ev_buffer_put == EV_QUEUE) { | |
934 | intr->ev_buffer_put = 0; | |
62c6ae04 HM |
935 | } |
936 | } else { | |
962d11e1 | 937 | xhci_write_event(xhci, event, v); |
62c6ae04 HM |
938 | } |
939 | ||
962d11e1 | 940 | xhci_intr_raise(xhci, v); |
62c6ae04 HM |
941 | } |
942 | ||
943 | static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, | |
59a70ccd | 944 | dma_addr_t base) |
62c6ae04 | 945 | { |
62c6ae04 HM |
946 | ring->dequeue = base; |
947 | ring->ccs = 1; | |
948 | } | |
949 | ||
950 | static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, | |
59a70ccd | 951 | dma_addr_t *addr) |
62c6ae04 HM |
952 | { |
953 | while (1) { | |
954 | TRBType type; | |
59a70ccd | 955 | pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE); |
62c6ae04 HM |
956 | trb->addr = ring->dequeue; |
957 | trb->ccs = ring->ccs; | |
958 | le64_to_cpus(&trb->parameter); | |
959 | le32_to_cpus(&trb->status); | |
960 | le32_to_cpus(&trb->control); | |
961 | ||
0703a4a7 GH |
962 | trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), |
963 | trb->parameter, trb->status, trb->control); | |
62c6ae04 HM |
964 | |
965 | if ((trb->control & TRB_C) != ring->ccs) { | |
966 | return 0; | |
967 | } | |
968 | ||
969 | type = TRB_TYPE(*trb); | |
970 | ||
971 | if (type != TR_LINK) { | |
972 | if (addr) { | |
973 | *addr = ring->dequeue; | |
974 | } | |
975 | ring->dequeue += TRB_SIZE; | |
976 | return type; | |
977 | } else { | |
978 | ring->dequeue = xhci_mask64(trb->parameter); | |
979 | if (trb->control & TRB_LK_TC) { | |
980 | ring->ccs = !ring->ccs; | |
981 | } | |
982 | } | |
983 | } | |
984 | } | |
985 | ||
986 | static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) | |
987 | { | |
988 | XHCITRB trb; | |
989 | int length = 0; | |
59a70ccd | 990 | dma_addr_t dequeue = ring->dequeue; |
62c6ae04 HM |
991 | bool ccs = ring->ccs; |
992 | /* hack to bundle together the two/three TDs that make a setup transfer */ | |
993 | bool control_td_set = 0; | |
994 | ||
995 | while (1) { | |
996 | TRBType type; | |
59a70ccd | 997 | pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE); |
62c6ae04 HM |
998 | le64_to_cpus(&trb.parameter); |
999 | le32_to_cpus(&trb.status); | |
1000 | le32_to_cpus(&trb.control); | |
1001 | ||
62c6ae04 HM |
1002 | if ((trb.control & TRB_C) != ccs) { |
1003 | return -length; | |
1004 | } | |
1005 | ||
1006 | type = TRB_TYPE(trb); | |
1007 | ||
1008 | if (type == TR_LINK) { | |
1009 | dequeue = xhci_mask64(trb.parameter); | |
1010 | if (trb.control & TRB_LK_TC) { | |
1011 | ccs = !ccs; | |
1012 | } | |
1013 | continue; | |
1014 | } | |
1015 | ||
1016 | length += 1; | |
1017 | dequeue += TRB_SIZE; | |
1018 | ||
1019 | if (type == TR_SETUP) { | |
1020 | control_td_set = 1; | |
1021 | } else if (type == TR_STATUS) { | |
1022 | control_td_set = 0; | |
1023 | } | |
1024 | ||
1025 | if (!control_td_set && !(trb.control & TRB_TR_CH)) { | |
1026 | return length; | |
1027 | } | |
1028 | } | |
1029 | } | |
1030 | ||
962d11e1 | 1031 | static void xhci_er_reset(XHCIState *xhci, int v) |
62c6ae04 | 1032 | { |
962d11e1 | 1033 | XHCIInterrupter *intr = &xhci->intr[v]; |
62c6ae04 HM |
1034 | XHCIEvRingSeg seg; |
1035 | ||
e099ad4b GH |
1036 | if (intr->erstsz == 0) { |
1037 | /* disabled */ | |
1038 | intr->er_start = 0; | |
1039 | intr->er_size = 0; | |
1040 | return; | |
1041 | } | |
62c6ae04 | 1042 | /* cache the (sole) event ring segment location */ |
962d11e1 GH |
1043 | if (intr->erstsz != 1) { |
1044 | fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); | |
62c6ae04 HM |
1045 | xhci_die(xhci); |
1046 | return; | |
1047 | } | |
962d11e1 | 1048 | dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); |
59a70ccd | 1049 | pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg)); |
62c6ae04 HM |
1050 | le32_to_cpus(&seg.addr_low); |
1051 | le32_to_cpus(&seg.addr_high); | |
1052 | le32_to_cpus(&seg.size); | |
1053 | if (seg.size < 16 || seg.size > 4096) { | |
1054 | fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size); | |
1055 | xhci_die(xhci); | |
1056 | return; | |
1057 | } | |
962d11e1 GH |
1058 | intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); |
1059 | intr->er_size = seg.size; | |
62c6ae04 | 1060 | |
962d11e1 GH |
1061 | intr->er_ep_idx = 0; |
1062 | intr->er_pcs = 1; | |
1063 | intr->er_full = 0; | |
62c6ae04 | 1064 | |
962d11e1 GH |
1065 | DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", |
1066 | v, intr->er_start, intr->er_size); | |
62c6ae04 HM |
1067 | } |
1068 | ||
1069 | static void xhci_run(XHCIState *xhci) | |
1070 | { | |
fc0ddaca | 1071 | trace_usb_xhci_run(); |
62c6ae04 | 1072 | xhci->usbsts &= ~USBSTS_HCH; |
01546fa6 | 1073 | xhci->mfindex_start = qemu_get_clock_ns(vm_clock); |
62c6ae04 HM |
1074 | } |
1075 | ||
1076 | static void xhci_stop(XHCIState *xhci) | |
1077 | { | |
fc0ddaca | 1078 | trace_usb_xhci_stop(); |
62c6ae04 HM |
1079 | xhci->usbsts |= USBSTS_HCH; |
1080 | xhci->crcr_low &= ~CRCR_CRR; | |
1081 | } | |
1082 | ||
024426ac GH |
1083 | static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, |
1084 | dma_addr_t base) | |
1085 | { | |
1086 | XHCIStreamContext *stctx; | |
1087 | unsigned int i; | |
1088 | ||
1089 | stctx = g_new0(XHCIStreamContext, count); | |
1090 | for (i = 0; i < count; i++) { | |
1091 | stctx[i].pctx = base + i * 16; | |
1092 | stctx[i].sct = -1; | |
1093 | } | |
1094 | return stctx; | |
1095 | } | |
1096 | ||
1097 | static void xhci_reset_streams(XHCIEPContext *epctx) | |
1098 | { | |
1099 | unsigned int i; | |
1100 | ||
1101 | for (i = 0; i < epctx->nr_pstreams; i++) { | |
1102 | epctx->pstreams[i].sct = -1; | |
1103 | g_free(epctx->pstreams[i].sstreams); | |
1104 | } | |
1105 | } | |
1106 | ||
1107 | static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) | |
1108 | { | |
1109 | assert(epctx->pstreams == NULL); | |
1110 | epctx->nr_pstreams = 2 << epctx->max_pstreams; | |
1111 | epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); | |
1112 | } | |
1113 | ||
1114 | static void xhci_free_streams(XHCIEPContext *epctx) | |
1115 | { | |
1116 | int i; | |
1117 | ||
1118 | assert(epctx->pstreams != NULL); | |
1119 | ||
1120 | if (!epctx->lsa) { | |
1121 | for (i = 0; i < epctx->nr_pstreams; i++) { | |
1122 | g_free(epctx->pstreams[i].sstreams); | |
1123 | } | |
1124 | } | |
1125 | g_free(epctx->pstreams); | |
1126 | epctx->pstreams = NULL; | |
1127 | epctx->nr_pstreams = 0; | |
1128 | } | |
1129 | ||
1130 | static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, | |
1131 | unsigned int streamid, | |
1132 | uint32_t *cc_error) | |
1133 | { | |
1134 | XHCIStreamContext *sctx; | |
1135 | dma_addr_t base; | |
1136 | uint32_t ctx[2], sct; | |
1137 | ||
1138 | assert(streamid != 0); | |
1139 | if (epctx->lsa) { | |
1140 | if (streamid >= epctx->nr_pstreams) { | |
1141 | *cc_error = CC_INVALID_STREAM_ID_ERROR; | |
1142 | return NULL; | |
1143 | } | |
1144 | sctx = epctx->pstreams + streamid; | |
1145 | } else { | |
1146 | FIXME("secondary streams not implemented yet"); | |
1147 | } | |
1148 | ||
1149 | if (sctx->sct == -1) { | |
1150 | xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); | |
685cbd2f HP |
1151 | fprintf(stderr, "%s: init sctx #%d @ " DMA_ADDR_FMT ": %08x %08x\n", |
1152 | __func__, streamid, sctx->pctx, ctx[0], ctx[1]); | |
024426ac GH |
1153 | sct = (ctx[0] >> 1) & 0x07; |
1154 | if (epctx->lsa && sct != 1) { | |
1155 | *cc_error = CC_INVALID_STREAM_TYPE_ERROR; | |
1156 | return NULL; | |
1157 | } | |
1158 | sctx->sct = sct; | |
1159 | base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); | |
1160 | xhci_ring_init(epctx->xhci, &sctx->ring, base); | |
1161 | } | |
1162 | return sctx; | |
1163 | } | |
1164 | ||
62c6ae04 | 1165 | static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, |
024426ac | 1166 | XHCIStreamContext *sctx, uint32_t state) |
62c6ae04 HM |
1167 | { |
1168 | uint32_t ctx[5]; | |
024426ac | 1169 | uint32_t ctx2[2]; |
62c6ae04 | 1170 | |
616b5d53 | 1171 | xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); |
62c6ae04 HM |
1172 | ctx[0] &= ~EP_STATE_MASK; |
1173 | ctx[0] |= state; | |
024426ac GH |
1174 | |
1175 | /* update ring dequeue ptr */ | |
1176 | if (epctx->nr_pstreams) { | |
1177 | if (sctx != NULL) { | |
1178 | xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); | |
1179 | ctx2[0] &= 0xe; | |
1180 | ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; | |
1181 | ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; | |
1182 | xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); | |
1183 | } | |
1184 | } else { | |
1185 | ctx[2] = epctx->ring.dequeue | epctx->ring.ccs; | |
1186 | ctx[3] = (epctx->ring.dequeue >> 16) >> 16; | |
1187 | DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", | |
1188 | epctx->pctx, state, ctx[3], ctx[2]); | |
1189 | } | |
1190 | ||
616b5d53 | 1191 | xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); |
62c6ae04 HM |
1192 | epctx->state = state; |
1193 | } | |
1194 | ||
3d139684 GH |
1195 | static void xhci_ep_kick_timer(void *opaque) |
1196 | { | |
1197 | XHCIEPContext *epctx = opaque; | |
024426ac | 1198 | xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0); |
3d139684 GH |
1199 | } |
1200 | ||
492b21f6 GH |
1201 | static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, |
1202 | unsigned int slotid, | |
1203 | unsigned int epid) | |
1204 | { | |
1205 | XHCIEPContext *epctx; | |
1206 | int i; | |
1207 | ||
1208 | epctx = g_new0(XHCIEPContext, 1); | |
1209 | epctx->xhci = xhci; | |
1210 | epctx->slotid = slotid; | |
1211 | epctx->epid = epid; | |
1212 | ||
1213 | for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) { | |
1214 | usb_packet_init(&epctx->transfers[i].packet); | |
1215 | } | |
1216 | epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx); | |
1217 | ||
1218 | return epctx; | |
1219 | } | |
1220 | ||
62c6ae04 | 1221 | static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, |
59a70ccd | 1222 | unsigned int epid, dma_addr_t pctx, |
62c6ae04 HM |
1223 | uint32_t *ctx) |
1224 | { | |
1225 | XHCISlot *slot; | |
1226 | XHCIEPContext *epctx; | |
59a70ccd | 1227 | dma_addr_t dequeue; |
62c6ae04 | 1228 | |
c1f6b493 | 1229 | trace_usb_xhci_ep_enable(slotid, epid); |
91062ae0 | 1230 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1231 | assert(epid >= 1 && epid <= 31); |
1232 | ||
62c6ae04 HM |
1233 | slot = &xhci->slots[slotid-1]; |
1234 | if (slot->eps[epid-1]) { | |
0bc85da6 | 1235 | xhci_disable_ep(xhci, slotid, epid); |
62c6ae04 HM |
1236 | } |
1237 | ||
492b21f6 | 1238 | epctx = xhci_alloc_epctx(xhci, slotid, epid); |
62c6ae04 HM |
1239 | slot->eps[epid-1] = epctx; |
1240 | ||
1241 | dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); | |
62c6ae04 HM |
1242 | |
1243 | epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; | |
1244 | DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type); | |
1245 | epctx->pctx = pctx; | |
1246 | epctx->max_psize = ctx[1]>>16; | |
1247 | epctx->max_psize *= 1+((ctx[1]>>8)&0xff); | |
024426ac GH |
1248 | epctx->max_pstreams = (ctx[0] >> 10) & 0xf; |
1249 | epctx->lsa = (ctx[0] >> 15) & 1; | |
62c6ae04 HM |
1250 | DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n", |
1251 | epid/2, epid%2, epctx->max_psize); | |
024426ac GH |
1252 | if (epctx->max_pstreams) { |
1253 | xhci_alloc_streams(epctx, dequeue); | |
1254 | } else { | |
1255 | xhci_ring_init(xhci, &epctx->ring, dequeue); | |
1256 | epctx->ring.ccs = ctx[2] & 1; | |
1257 | } | |
62c6ae04 | 1258 | |
3d139684 GH |
1259 | epctx->interval = 1 << (ctx[0] >> 16) & 0xff; |
1260 | epctx->mfindex_last = 0; | |
3d139684 | 1261 | |
62c6ae04 HM |
1262 | epctx->state = EP_RUNNING; |
1263 | ctx[0] &= ~EP_STATE_MASK; | |
1264 | ctx[0] |= EP_RUNNING; | |
1265 | ||
1266 | return CC_SUCCESS; | |
1267 | } | |
1268 | ||
3151f209 HG |
1269 | static int xhci_ep_nuke_one_xfer(XHCITransfer *t) |
1270 | { | |
1271 | int killed = 0; | |
1272 | ||
1273 | if (t->running_async) { | |
1274 | usb_cancel_packet(&t->packet); | |
1275 | t->running_async = 0; | |
1276 | t->cancelled = 1; | |
1277 | DPRINTF("xhci: cancelling transfer, waiting for it to complete\n"); | |
1278 | killed = 1; | |
1279 | } | |
1280 | if (t->running_retry) { | |
1281 | XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1]; | |
1282 | if (epctx) { | |
1283 | epctx->retry = NULL; | |
1284 | qemu_del_timer(epctx->kick_timer); | |
1285 | } | |
1286 | t->running_retry = 0; | |
1287 | } | |
1288 | if (t->trbs) { | |
1289 | g_free(t->trbs); | |
1290 | } | |
1291 | ||
1292 | t->trbs = NULL; | |
1293 | t->trb_count = t->trb_alloced = 0; | |
1294 | ||
1295 | return killed; | |
1296 | } | |
1297 | ||
62c6ae04 HM |
1298 | static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, |
1299 | unsigned int epid) | |
1300 | { | |
1301 | XHCISlot *slot; | |
1302 | XHCIEPContext *epctx; | |
1303 | int i, xferi, killed = 0; | |
f79738b0 | 1304 | USBEndpoint *ep = NULL; |
91062ae0 | 1305 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1306 | assert(epid >= 1 && epid <= 31); |
1307 | ||
1308 | DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); | |
1309 | ||
1310 | slot = &xhci->slots[slotid-1]; | |
1311 | ||
1312 | if (!slot->eps[epid-1]) { | |
1313 | return 0; | |
1314 | } | |
1315 | ||
1316 | epctx = slot->eps[epid-1]; | |
1317 | ||
1318 | xferi = epctx->next_xfer; | |
1319 | for (i = 0; i < TD_QUEUE; i++) { | |
f79738b0 HG |
1320 | if (epctx->transfers[xferi].packet.ep) { |
1321 | ep = epctx->transfers[xferi].packet.ep; | |
1322 | } | |
3151f209 | 1323 | killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi]); |
0cb41e2c | 1324 | epctx->transfers[xferi].packet.ep = NULL; |
62c6ae04 HM |
1325 | xferi = (xferi + 1) % TD_QUEUE; |
1326 | } | |
f79738b0 HG |
1327 | if (ep) { |
1328 | usb_device_ep_stopped(ep->dev, ep); | |
1329 | } | |
62c6ae04 HM |
1330 | return killed; |
1331 | } | |
1332 | ||
1333 | static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, | |
1334 | unsigned int epid) | |
1335 | { | |
1336 | XHCISlot *slot; | |
1337 | XHCIEPContext *epctx; | |
1338 | ||
c1f6b493 | 1339 | trace_usb_xhci_ep_disable(slotid, epid); |
91062ae0 | 1340 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1341 | assert(epid >= 1 && epid <= 31); |
1342 | ||
62c6ae04 HM |
1343 | slot = &xhci->slots[slotid-1]; |
1344 | ||
1345 | if (!slot->eps[epid-1]) { | |
1346 | DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); | |
1347 | return CC_SUCCESS; | |
1348 | } | |
1349 | ||
1350 | xhci_ep_nuke_xfers(xhci, slotid, epid); | |
1351 | ||
1352 | epctx = slot->eps[epid-1]; | |
1353 | ||
024426ac GH |
1354 | if (epctx->nr_pstreams) { |
1355 | xhci_free_streams(epctx); | |
1356 | } | |
1357 | ||
1358 | xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); | |
62c6ae04 | 1359 | |
3d139684 | 1360 | qemu_free_timer(epctx->kick_timer); |
62c6ae04 HM |
1361 | g_free(epctx); |
1362 | slot->eps[epid-1] = NULL; | |
1363 | ||
1364 | return CC_SUCCESS; | |
1365 | } | |
1366 | ||
1367 | static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, | |
1368 | unsigned int epid) | |
1369 | { | |
1370 | XHCISlot *slot; | |
1371 | XHCIEPContext *epctx; | |
1372 | ||
c1f6b493 | 1373 | trace_usb_xhci_ep_stop(slotid, epid); |
91062ae0 | 1374 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1375 | |
1376 | if (epid < 1 || epid > 31) { | |
1377 | fprintf(stderr, "xhci: bad ep %d\n", epid); | |
1378 | return CC_TRB_ERROR; | |
1379 | } | |
1380 | ||
1381 | slot = &xhci->slots[slotid-1]; | |
1382 | ||
1383 | if (!slot->eps[epid-1]) { | |
1384 | DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); | |
1385 | return CC_EP_NOT_ENABLED_ERROR; | |
1386 | } | |
1387 | ||
1388 | if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { | |
1389 | fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, " | |
1390 | "data might be lost\n"); | |
1391 | } | |
1392 | ||
1393 | epctx = slot->eps[epid-1]; | |
1394 | ||
024426ac GH |
1395 | xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); |
1396 | ||
1397 | if (epctx->nr_pstreams) { | |
1398 | xhci_reset_streams(epctx); | |
1399 | } | |
62c6ae04 HM |
1400 | |
1401 | return CC_SUCCESS; | |
1402 | } | |
1403 | ||
1404 | static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, | |
1405 | unsigned int epid) | |
1406 | { | |
1407 | XHCISlot *slot; | |
1408 | XHCIEPContext *epctx; | |
1409 | USBDevice *dev; | |
1410 | ||
c1f6b493 | 1411 | trace_usb_xhci_ep_reset(slotid, epid); |
91062ae0 | 1412 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 | 1413 | |
62c6ae04 HM |
1414 | if (epid < 1 || epid > 31) { |
1415 | fprintf(stderr, "xhci: bad ep %d\n", epid); | |
1416 | return CC_TRB_ERROR; | |
1417 | } | |
1418 | ||
1419 | slot = &xhci->slots[slotid-1]; | |
1420 | ||
1421 | if (!slot->eps[epid-1]) { | |
1422 | DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); | |
1423 | return CC_EP_NOT_ENABLED_ERROR; | |
1424 | } | |
1425 | ||
1426 | epctx = slot->eps[epid-1]; | |
1427 | ||
1428 | if (epctx->state != EP_HALTED) { | |
1429 | fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n", | |
1430 | epid, epctx->state); | |
1431 | return CC_CONTEXT_STATE_ERROR; | |
1432 | } | |
1433 | ||
1434 | if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) { | |
1435 | fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, " | |
1436 | "data might be lost\n"); | |
1437 | } | |
1438 | ||
1439 | uint8_t ep = epid>>1; | |
1440 | ||
1441 | if (epid & 1) { | |
1442 | ep |= 0x80; | |
1443 | } | |
1444 | ||
ccaf87a0 | 1445 | dev = xhci->slots[slotid-1].uport->dev; |
62c6ae04 HM |
1446 | if (!dev) { |
1447 | return CC_USB_TRANSACTION_ERROR; | |
1448 | } | |
1449 | ||
024426ac GH |
1450 | xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); |
1451 | ||
1452 | if (epctx->nr_pstreams) { | |
1453 | xhci_reset_streams(epctx); | |
1454 | } | |
62c6ae04 HM |
1455 | |
1456 | return CC_SUCCESS; | |
1457 | } | |
1458 | ||
1459 | static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, | |
024426ac GH |
1460 | unsigned int epid, unsigned int streamid, |
1461 | uint64_t pdequeue) | |
62c6ae04 HM |
1462 | { |
1463 | XHCISlot *slot; | |
1464 | XHCIEPContext *epctx; | |
024426ac | 1465 | XHCIStreamContext *sctx; |
59a70ccd | 1466 | dma_addr_t dequeue; |
62c6ae04 | 1467 | |
91062ae0 | 1468 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
1469 | |
1470 | if (epid < 1 || epid > 31) { | |
1471 | fprintf(stderr, "xhci: bad ep %d\n", epid); | |
1472 | return CC_TRB_ERROR; | |
1473 | } | |
1474 | ||
024426ac | 1475 | trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); |
62c6ae04 HM |
1476 | dequeue = xhci_mask64(pdequeue); |
1477 | ||
1478 | slot = &xhci->slots[slotid-1]; | |
1479 | ||
1480 | if (!slot->eps[epid-1]) { | |
1481 | DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); | |
1482 | return CC_EP_NOT_ENABLED_ERROR; | |
1483 | } | |
1484 | ||
1485 | epctx = slot->eps[epid-1]; | |
1486 | ||
62c6ae04 HM |
1487 | if (epctx->state != EP_STOPPED) { |
1488 | fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid); | |
1489 | return CC_CONTEXT_STATE_ERROR; | |
1490 | } | |
1491 | ||
024426ac GH |
1492 | if (epctx->nr_pstreams) { |
1493 | uint32_t err; | |
1494 | sctx = xhci_find_stream(epctx, streamid, &err); | |
1495 | if (sctx == NULL) { | |
1496 | return err; | |
1497 | } | |
1498 | xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); | |
1499 | sctx->ring.ccs = dequeue & 1; | |
1500 | } else { | |
1501 | sctx = NULL; | |
1502 | xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); | |
1503 | epctx->ring.ccs = dequeue & 1; | |
1504 | } | |
62c6ae04 | 1505 | |
024426ac | 1506 | xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); |
62c6ae04 HM |
1507 | |
1508 | return CC_SUCCESS; | |
1509 | } | |
1510 | ||
a6fb2ddb | 1511 | static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) |
62c6ae04 | 1512 | { |
62c6ae04 | 1513 | XHCIState *xhci = xfer->xhci; |
d5a15814 | 1514 | int i; |
62c6ae04 | 1515 | |
a6fb2ddb | 1516 | xfer->int_req = false; |
d5a15814 | 1517 | pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count); |
62c6ae04 HM |
1518 | for (i = 0; i < xfer->trb_count; i++) { |
1519 | XHCITRB *trb = &xfer->trbs[i]; | |
59a70ccd | 1520 | dma_addr_t addr; |
62c6ae04 HM |
1521 | unsigned int chunk = 0; |
1522 | ||
a6fb2ddb HG |
1523 | if (trb->control & TRB_TR_IOC) { |
1524 | xfer->int_req = true; | |
1525 | } | |
1526 | ||
62c6ae04 HM |
1527 | switch (TRB_TYPE(*trb)) { |
1528 | case TR_DATA: | |
1529 | if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { | |
1530 | fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n"); | |
d5a15814 | 1531 | goto err; |
62c6ae04 HM |
1532 | } |
1533 | /* fallthrough */ | |
1534 | case TR_NORMAL: | |
1535 | case TR_ISOCH: | |
1536 | addr = xhci_mask64(trb->parameter); | |
d5a15814 GH |
1537 | chunk = trb->status & 0x1ffff; |
1538 | if (trb->control & TRB_TR_IDT) { | |
1539 | if (chunk > 8 || in_xfer) { | |
1540 | fprintf(stderr, "xhci: invalid immediate data TRB\n"); | |
1541 | goto err; | |
1542 | } | |
1543 | qemu_sglist_add(&xfer->sgl, trb->addr, chunk); | |
1544 | } else { | |
1545 | qemu_sglist_add(&xfer->sgl, addr, chunk); | |
1546 | } | |
1547 | break; | |
1548 | } | |
1549 | } | |
1550 | ||
d5a15814 GH |
1551 | return 0; |
1552 | ||
1553 | err: | |
1554 | qemu_sglist_destroy(&xfer->sgl); | |
1555 | xhci_die(xhci); | |
1556 | return -1; | |
1557 | } | |
1558 | ||
1559 | static void xhci_xfer_unmap(XHCITransfer *xfer) | |
1560 | { | |
1561 | usb_packet_unmap(&xfer->packet, &xfer->sgl); | |
1562 | qemu_sglist_destroy(&xfer->sgl); | |
1563 | } | |
1564 | ||
1565 | static void xhci_xfer_report(XHCITransfer *xfer) | |
1566 | { | |
1567 | uint32_t edtla = 0; | |
1568 | unsigned int left; | |
1569 | bool reported = 0; | |
1570 | bool shortpkt = 0; | |
1571 | XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; | |
1572 | XHCIState *xhci = xfer->xhci; | |
1573 | int i; | |
1574 | ||
9b8251c5 | 1575 | left = xfer->packet.actual_length; |
d5a15814 GH |
1576 | |
1577 | for (i = 0; i < xfer->trb_count; i++) { | |
1578 | XHCITRB *trb = &xfer->trbs[i]; | |
1579 | unsigned int chunk = 0; | |
1580 | ||
1581 | switch (TRB_TYPE(*trb)) { | |
1582 | case TR_DATA: | |
1583 | case TR_NORMAL: | |
1584 | case TR_ISOCH: | |
62c6ae04 HM |
1585 | chunk = trb->status & 0x1ffff; |
1586 | if (chunk > left) { | |
1587 | chunk = left; | |
d5a15814 GH |
1588 | if (xfer->status == CC_SUCCESS) { |
1589 | shortpkt = 1; | |
62c6ae04 HM |
1590 | } |
1591 | } | |
1592 | left -= chunk; | |
62c6ae04 | 1593 | edtla += chunk; |
62c6ae04 HM |
1594 | break; |
1595 | case TR_STATUS: | |
1596 | reported = 0; | |
1597 | shortpkt = 0; | |
1598 | break; | |
1599 | } | |
1600 | ||
d5a15814 GH |
1601 | if (!reported && ((trb->control & TRB_TR_IOC) || |
1602 | (shortpkt && (trb->control & TRB_TR_ISP)) || | |
9b8251c5 | 1603 | (xfer->status != CC_SUCCESS && left == 0))) { |
62c6ae04 HM |
1604 | event.slotid = xfer->slotid; |
1605 | event.epid = xfer->epid; | |
1606 | event.length = (trb->status & 0x1ffff) - chunk; | |
1607 | event.flags = 0; | |
1608 | event.ptr = trb->addr; | |
1609 | if (xfer->status == CC_SUCCESS) { | |
1610 | event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; | |
1611 | } else { | |
1612 | event.ccode = xfer->status; | |
1613 | } | |
1614 | if (TRB_TYPE(*trb) == TR_EVDATA) { | |
1615 | event.ptr = trb->parameter; | |
1616 | event.flags |= TRB_EV_ED; | |
1617 | event.length = edtla & 0xffffff; | |
1618 | DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); | |
1619 | edtla = 0; | |
1620 | } | |
2d1de850 | 1621 | xhci_event(xhci, &event, TRB_INTR(*trb)); |
62c6ae04 | 1622 | reported = 1; |
d5a15814 GH |
1623 | if (xfer->status != CC_SUCCESS) { |
1624 | return; | |
1625 | } | |
62c6ae04 HM |
1626 | } |
1627 | } | |
62c6ae04 HM |
1628 | } |
1629 | ||
1630 | static void xhci_stall_ep(XHCITransfer *xfer) | |
1631 | { | |
1632 | XHCIState *xhci = xfer->xhci; | |
1633 | XHCISlot *slot = &xhci->slots[xfer->slotid-1]; | |
1634 | XHCIEPContext *epctx = slot->eps[xfer->epid-1]; | |
024426ac GH |
1635 | uint32_t err; |
1636 | XHCIStreamContext *sctx; | |
62c6ae04 | 1637 | |
024426ac GH |
1638 | if (epctx->nr_pstreams) { |
1639 | sctx = xhci_find_stream(epctx, xfer->streamid, &err); | |
1640 | if (sctx == NULL) { | |
1641 | return; | |
1642 | } | |
1643 | sctx->ring.dequeue = xfer->trbs[0].addr; | |
1644 | sctx->ring.ccs = xfer->trbs[0].ccs; | |
1645 | xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); | |
1646 | } else { | |
1647 | epctx->ring.dequeue = xfer->trbs[0].addr; | |
1648 | epctx->ring.ccs = xfer->trbs[0].ccs; | |
1649 | xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); | |
1650 | } | |
62c6ae04 HM |
1651 | } |
1652 | ||
1653 | static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, | |
1654 | XHCIEPContext *epctx); | |
1655 | ||
5c08106f GH |
1656 | static int xhci_setup_packet(XHCITransfer *xfer) |
1657 | { | |
1658 | XHCIState *xhci = xfer->xhci; | |
5c08106f | 1659 | USBDevice *dev; |
079d0b7f GH |
1660 | USBEndpoint *ep; |
1661 | int dir; | |
1662 | ||
1663 | dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; | |
5c08106f GH |
1664 | |
1665 | if (xfer->packet.ep) { | |
1666 | ep = xfer->packet.ep; | |
1667 | dev = ep->dev; | |
1668 | } else { | |
ccaf87a0 GH |
1669 | if (!xhci->slots[xfer->slotid-1].uport) { |
1670 | fprintf(stderr, "xhci: slot %d has no device\n", | |
1671 | xfer->slotid); | |
5c08106f GH |
1672 | return -1; |
1673 | } | |
ccaf87a0 | 1674 | dev = xhci->slots[xfer->slotid-1].uport->dev; |
5c08106f GH |
1675 | ep = usb_ep_get(dev, dir, xfer->epid >> 1); |
1676 | } | |
1677 | ||
a6fb2ddb | 1678 | xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ |
024426ac | 1679 | usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, |
8550a02d | 1680 | xfer->trbs[0].addr, false, xfer->int_req); |
a6fb2ddb | 1681 | usb_packet_map(&xfer->packet, &xfer->sgl); |
62c6ae04 | 1682 | DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", |
079d0b7f | 1683 | xfer->packet.pid, dev->addr, ep->nr); |
62c6ae04 HM |
1684 | return 0; |
1685 | } | |
1686 | ||
9a77a0f5 | 1687 | static int xhci_complete_packet(XHCITransfer *xfer) |
62c6ae04 | 1688 | { |
9a77a0f5 | 1689 | if (xfer->packet.status == USB_RET_ASYNC) { |
97df650b | 1690 | trace_usb_xhci_xfer_async(xfer); |
7c605a23 GH |
1691 | xfer->running_async = 1; |
1692 | xfer->running_retry = 0; | |
1693 | xfer->complete = 0; | |
1694 | xfer->cancelled = 0; | |
1695 | return 0; | |
9a77a0f5 | 1696 | } else if (xfer->packet.status == USB_RET_NAK) { |
97df650b | 1697 | trace_usb_xhci_xfer_nak(xfer); |
7c605a23 GH |
1698 | xfer->running_async = 0; |
1699 | xfer->running_retry = 1; | |
62c6ae04 HM |
1700 | xfer->complete = 0; |
1701 | xfer->cancelled = 0; | |
1702 | return 0; | |
1703 | } else { | |
7c605a23 GH |
1704 | xfer->running_async = 0; |
1705 | xfer->running_retry = 0; | |
62c6ae04 | 1706 | xfer->complete = 1; |
d5a15814 | 1707 | xhci_xfer_unmap(xfer); |
62c6ae04 HM |
1708 | } |
1709 | ||
9a77a0f5 HG |
1710 | if (xfer->packet.status == USB_RET_SUCCESS) { |
1711 | trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); | |
d5a15814 GH |
1712 | xfer->status = CC_SUCCESS; |
1713 | xhci_xfer_report(xfer); | |
62c6ae04 HM |
1714 | return 0; |
1715 | } | |
1716 | ||
1717 | /* error */ | |
9a77a0f5 HG |
1718 | trace_usb_xhci_xfer_error(xfer, xfer->packet.status); |
1719 | switch (xfer->packet.status) { | |
62c6ae04 HM |
1720 | case USB_RET_NODEV: |
1721 | xfer->status = CC_USB_TRANSACTION_ERROR; | |
d5a15814 | 1722 | xhci_xfer_report(xfer); |
62c6ae04 HM |
1723 | xhci_stall_ep(xfer); |
1724 | break; | |
1725 | case USB_RET_STALL: | |
1726 | xfer->status = CC_STALL_ERROR; | |
d5a15814 | 1727 | xhci_xfer_report(xfer); |
62c6ae04 HM |
1728 | xhci_stall_ep(xfer); |
1729 | break; | |
4e906d56 GH |
1730 | case USB_RET_BABBLE: |
1731 | xfer->status = CC_BABBLE_DETECTED; | |
1732 | xhci_xfer_report(xfer); | |
1733 | xhci_stall_ep(xfer); | |
1734 | break; | |
62c6ae04 | 1735 | default: |
9a77a0f5 HG |
1736 | fprintf(stderr, "%s: FIXME: status = %d\n", __func__, |
1737 | xfer->packet.status); | |
024426ac | 1738 | FIXME("unhandled USB_RET_*"); |
62c6ae04 HM |
1739 | } |
1740 | return 0; | |
1741 | } | |
1742 | ||
1743 | static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) | |
1744 | { | |
1745 | XHCITRB *trb_setup, *trb_status; | |
2850ca9e | 1746 | uint8_t bmRequestType; |
62c6ae04 | 1747 | |
62c6ae04 HM |
1748 | trb_setup = &xfer->trbs[0]; |
1749 | trb_status = &xfer->trbs[xfer->trb_count-1]; | |
1750 | ||
024426ac | 1751 | trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); |
97df650b | 1752 | |
62c6ae04 HM |
1753 | /* at most one Event Data TRB allowed after STATUS */ |
1754 | if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { | |
1755 | trb_status--; | |
1756 | } | |
1757 | ||
1758 | /* do some sanity checks */ | |
1759 | if (TRB_TYPE(*trb_setup) != TR_SETUP) { | |
1760 | fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n", | |
1761 | TRB_TYPE(*trb_setup)); | |
1762 | return -1; | |
1763 | } | |
1764 | if (TRB_TYPE(*trb_status) != TR_STATUS) { | |
1765 | fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n", | |
1766 | TRB_TYPE(*trb_status)); | |
1767 | return -1; | |
1768 | } | |
1769 | if (!(trb_setup->control & TRB_TR_IDT)) { | |
1770 | fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n"); | |
1771 | return -1; | |
1772 | } | |
1773 | if ((trb_setup->status & 0x1ffff) != 8) { | |
1774 | fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n", | |
1775 | (trb_setup->status & 0x1ffff)); | |
1776 | return -1; | |
1777 | } | |
1778 | ||
1779 | bmRequestType = trb_setup->parameter; | |
62c6ae04 | 1780 | |
62c6ae04 HM |
1781 | xfer->in_xfer = bmRequestType & USB_DIR_IN; |
1782 | xfer->iso_xfer = false; | |
1783 | ||
5c08106f GH |
1784 | if (xhci_setup_packet(xfer) < 0) { |
1785 | return -1; | |
1786 | } | |
2850ca9e | 1787 | xfer->packet.parameter = trb_setup->parameter; |
2850ca9e | 1788 | |
9a77a0f5 | 1789 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
62c6ae04 | 1790 | |
9a77a0f5 | 1791 | xhci_complete_packet(xfer); |
7c605a23 | 1792 | if (!xfer->running_async && !xfer->running_retry) { |
024426ac | 1793 | xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0); |
62c6ae04 HM |
1794 | } |
1795 | return 0; | |
1796 | } | |
1797 | ||
3d139684 GH |
1798 | static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, |
1799 | XHCIEPContext *epctx, uint64_t mfindex) | |
1800 | { | |
1801 | if (xfer->trbs[0].control & TRB_TR_SIA) { | |
1802 | uint64_t asap = ((mfindex + epctx->interval - 1) & | |
1803 | ~(epctx->interval-1)); | |
1804 | if (asap >= epctx->mfindex_last && | |
1805 | asap <= epctx->mfindex_last + epctx->interval * 4) { | |
1806 | xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; | |
1807 | } else { | |
1808 | xfer->mfindex_kick = asap; | |
1809 | } | |
1810 | } else { | |
1811 | xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) | |
1812 | & TRB_TR_FRAMEID_MASK; | |
1813 | xfer->mfindex_kick |= mfindex & ~0x3fff; | |
1814 | if (xfer->mfindex_kick < mfindex) { | |
1815 | xfer->mfindex_kick += 0x4000; | |
1816 | } | |
1817 | } | |
1818 | } | |
1819 | ||
1820 | static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer, | |
1821 | XHCIEPContext *epctx, uint64_t mfindex) | |
1822 | { | |
1823 | if (xfer->mfindex_kick > mfindex) { | |
1824 | qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) + | |
1825 | (xfer->mfindex_kick - mfindex) * 125000); | |
1826 | xfer->running_retry = 1; | |
1827 | } else { | |
1828 | epctx->mfindex_last = xfer->mfindex_kick; | |
1829 | qemu_del_timer(epctx->kick_timer); | |
1830 | xfer->running_retry = 0; | |
1831 | } | |
1832 | } | |
1833 | ||
1834 | ||
62c6ae04 HM |
1835 | static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) |
1836 | { | |
3d139684 | 1837 | uint64_t mfindex; |
62c6ae04 HM |
1838 | |
1839 | DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); | |
62c6ae04 HM |
1840 | |
1841 | xfer->in_xfer = epctx->type>>2; | |
62c6ae04 | 1842 | |
62c6ae04 HM |
1843 | switch(epctx->type) { |
1844 | case ET_INTR_OUT: | |
1845 | case ET_INTR_IN: | |
1846 | case ET_BULK_OUT: | |
1847 | case ET_BULK_IN: | |
3d139684 GH |
1848 | xfer->pkts = 0; |
1849 | xfer->iso_xfer = false; | |
62c6ae04 HM |
1850 | break; |
1851 | case ET_ISO_OUT: | |
1852 | case ET_ISO_IN: | |
3d139684 GH |
1853 | xfer->pkts = 1; |
1854 | xfer->iso_xfer = true; | |
1855 | mfindex = xhci_mfindex_get(xhci); | |
1856 | xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); | |
1857 | xhci_check_iso_kick(xhci, xfer, epctx, mfindex); | |
1858 | if (xfer->running_retry) { | |
1859 | return -1; | |
1860 | } | |
62c6ae04 HM |
1861 | break; |
1862 | default: | |
079d0b7f GH |
1863 | fprintf(stderr, "xhci: unknown or unhandled EP " |
1864 | "(type %d, in %d, ep %02x)\n", | |
1865 | epctx->type, xfer->in_xfer, xfer->epid); | |
62c6ae04 HM |
1866 | return -1; |
1867 | } | |
1868 | ||
5c08106f GH |
1869 | if (xhci_setup_packet(xfer) < 0) { |
1870 | return -1; | |
1871 | } | |
9a77a0f5 | 1872 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
62c6ae04 | 1873 | |
9a77a0f5 | 1874 | xhci_complete_packet(xfer); |
7c605a23 | 1875 | if (!xfer->running_async && !xfer->running_retry) { |
024426ac | 1876 | xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid); |
62c6ae04 HM |
1877 | } |
1878 | return 0; | |
1879 | } | |
1880 | ||
1881 | static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) | |
1882 | { | |
024426ac | 1883 | trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid); |
331e9406 | 1884 | return xhci_submit(xhci, xfer, epctx); |
62c6ae04 HM |
1885 | } |
1886 | ||
024426ac GH |
1887 | static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, |
1888 | unsigned int epid, unsigned int streamid) | |
62c6ae04 | 1889 | { |
024426ac | 1890 | XHCIStreamContext *stctx; |
62c6ae04 | 1891 | XHCIEPContext *epctx; |
024426ac | 1892 | XHCIRing *ring; |
36dfe324 | 1893 | USBEndpoint *ep = NULL; |
3d139684 | 1894 | uint64_t mfindex; |
62c6ae04 HM |
1895 | int length; |
1896 | int i; | |
1897 | ||
024426ac | 1898 | trace_usb_xhci_ep_kick(slotid, epid, streamid); |
91062ae0 | 1899 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 | 1900 | assert(epid >= 1 && epid <= 31); |
62c6ae04 HM |
1901 | |
1902 | if (!xhci->slots[slotid-1].enabled) { | |
1903 | fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid); | |
1904 | return; | |
1905 | } | |
1906 | epctx = xhci->slots[slotid-1].eps[epid-1]; | |
1907 | if (!epctx) { | |
1908 | fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n", | |
1909 | epid, slotid); | |
1910 | return; | |
1911 | } | |
1912 | ||
7c605a23 | 1913 | if (epctx->retry) { |
7c605a23 | 1914 | XHCITransfer *xfer = epctx->retry; |
7c605a23 | 1915 | |
97df650b | 1916 | trace_usb_xhci_xfer_retry(xfer); |
7c605a23 | 1917 | assert(xfer->running_retry); |
3d139684 GH |
1918 | if (xfer->iso_xfer) { |
1919 | /* retry delayed iso transfer */ | |
1920 | mfindex = xhci_mfindex_get(xhci); | |
1921 | xhci_check_iso_kick(xhci, xfer, epctx, mfindex); | |
1922 | if (xfer->running_retry) { | |
1923 | return; | |
1924 | } | |
1925 | if (xhci_setup_packet(xfer) < 0) { | |
1926 | return; | |
1927 | } | |
9a77a0f5 HG |
1928 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
1929 | assert(xfer->packet.status != USB_RET_NAK); | |
1930 | xhci_complete_packet(xfer); | |
3d139684 GH |
1931 | } else { |
1932 | /* retry nak'ed transfer */ | |
1933 | if (xhci_setup_packet(xfer) < 0) { | |
1934 | return; | |
1935 | } | |
9a77a0f5 HG |
1936 | usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); |
1937 | if (xfer->packet.status == USB_RET_NAK) { | |
3d139684 GH |
1938 | return; |
1939 | } | |
9a77a0f5 | 1940 | xhci_complete_packet(xfer); |
7c605a23 | 1941 | } |
7c605a23 GH |
1942 | assert(!xfer->running_retry); |
1943 | epctx->retry = NULL; | |
1944 | } | |
1945 | ||
62c6ae04 HM |
1946 | if (epctx->state == EP_HALTED) { |
1947 | DPRINTF("xhci: ep halted, not running schedule\n"); | |
1948 | return; | |
1949 | } | |
1950 | ||
024426ac GH |
1951 | |
1952 | if (epctx->nr_pstreams) { | |
1953 | uint32_t err; | |
1954 | stctx = xhci_find_stream(epctx, streamid, &err); | |
1955 | if (stctx == NULL) { | |
1956 | return; | |
1957 | } | |
1958 | ring = &stctx->ring; | |
1959 | xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); | |
1960 | } else { | |
1961 | ring = &epctx->ring; | |
1962 | streamid = 0; | |
1963 | xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); | |
1964 | } | |
7d04c2b7 | 1965 | assert(ring->dequeue != 0); |
62c6ae04 HM |
1966 | |
1967 | while (1) { | |
1968 | XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer]; | |
331e9406 | 1969 | if (xfer->running_async || xfer->running_retry) { |
62c6ae04 HM |
1970 | break; |
1971 | } | |
024426ac | 1972 | length = xhci_ring_chain_length(xhci, ring); |
62c6ae04 | 1973 | if (length < 0) { |
62c6ae04 HM |
1974 | break; |
1975 | } else if (length == 0) { | |
1976 | break; | |
1977 | } | |
62c6ae04 HM |
1978 | if (xfer->trbs && xfer->trb_alloced < length) { |
1979 | xfer->trb_count = 0; | |
1980 | xfer->trb_alloced = 0; | |
1981 | g_free(xfer->trbs); | |
1982 | xfer->trbs = NULL; | |
1983 | } | |
1984 | if (!xfer->trbs) { | |
1985 | xfer->trbs = g_malloc(sizeof(XHCITRB) * length); | |
1986 | xfer->trb_alloced = length; | |
1987 | } | |
1988 | xfer->trb_count = length; | |
1989 | ||
1990 | for (i = 0; i < length; i++) { | |
024426ac | 1991 | assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL)); |
62c6ae04 HM |
1992 | } |
1993 | xfer->xhci = xhci; | |
1994 | xfer->epid = epid; | |
1995 | xfer->slotid = slotid; | |
024426ac | 1996 | xfer->streamid = streamid; |
62c6ae04 HM |
1997 | |
1998 | if (epid == 1) { | |
1999 | if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) { | |
2000 | epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; | |
36dfe324 | 2001 | ep = xfer->packet.ep; |
62c6ae04 HM |
2002 | } else { |
2003 | fprintf(stderr, "xhci: error firing CTL transfer\n"); | |
2004 | } | |
2005 | } else { | |
2006 | if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) { | |
2007 | epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE; | |
36dfe324 | 2008 | ep = xfer->packet.ep; |
62c6ae04 | 2009 | } else { |
3d139684 GH |
2010 | if (!xfer->iso_xfer) { |
2011 | fprintf(stderr, "xhci: error firing data transfer\n"); | |
2012 | } | |
62c6ae04 HM |
2013 | } |
2014 | } | |
2015 | ||
3c4866e0 | 2016 | if (epctx->state == EP_HALTED) { |
3c4866e0 GH |
2017 | break; |
2018 | } | |
7c605a23 GH |
2019 | if (xfer->running_retry) { |
2020 | DPRINTF("xhci: xfer nacked, stopping schedule\n"); | |
2021 | epctx->retry = xfer; | |
2022 | break; | |
2023 | } | |
62c6ae04 | 2024 | } |
36dfe324 HG |
2025 | if (ep) { |
2026 | usb_device_flush_ep_queue(ep->dev, ep); | |
2027 | } | |
62c6ae04 HM |
2028 | } |
2029 | ||
2030 | static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) | |
2031 | { | |
348f1037 | 2032 | trace_usb_xhci_slot_enable(slotid); |
91062ae0 | 2033 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 | 2034 | xhci->slots[slotid-1].enabled = 1; |
ccaf87a0 | 2035 | xhci->slots[slotid-1].uport = NULL; |
62c6ae04 HM |
2036 | memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); |
2037 | ||
2038 | return CC_SUCCESS; | |
2039 | } | |
2040 | ||
2041 | static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) | |
2042 | { | |
2043 | int i; | |
2044 | ||
348f1037 | 2045 | trace_usb_xhci_slot_disable(slotid); |
91062ae0 | 2046 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2047 | |
2048 | for (i = 1; i <= 31; i++) { | |
2049 | if (xhci->slots[slotid-1].eps[i-1]) { | |
2050 | xhci_disable_ep(xhci, slotid, i); | |
2051 | } | |
2052 | } | |
2053 | ||
2054 | xhci->slots[slotid-1].enabled = 0; | |
4034e693 | 2055 | xhci->slots[slotid-1].addressed = 0; |
62c6ae04 HM |
2056 | return CC_SUCCESS; |
2057 | } | |
2058 | ||
ccaf87a0 GH |
2059 | static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) |
2060 | { | |
2061 | USBPort *uport; | |
2062 | char path[32]; | |
2063 | int i, pos, port; | |
2064 | ||
2065 | port = (slot_ctx[1]>>16) & 0xFF; | |
2066 | port = xhci->ports[port-1].uport->index+1; | |
2067 | pos = snprintf(path, sizeof(path), "%d", port); | |
2068 | for (i = 0; i < 5; i++) { | |
2069 | port = (slot_ctx[0] >> 4*i) & 0x0f; | |
2070 | if (!port) { | |
2071 | break; | |
2072 | } | |
2073 | pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); | |
2074 | } | |
2075 | ||
2076 | QTAILQ_FOREACH(uport, &xhci->bus.used, next) { | |
2077 | if (strcmp(uport->path, path) == 0) { | |
2078 | return uport; | |
2079 | } | |
2080 | } | |
2081 | return NULL; | |
2082 | } | |
2083 | ||
62c6ae04 HM |
2084 | static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, |
2085 | uint64_t pictx, bool bsr) | |
2086 | { | |
2087 | XHCISlot *slot; | |
ccaf87a0 | 2088 | USBPort *uport; |
62c6ae04 | 2089 | USBDevice *dev; |
59a70ccd | 2090 | dma_addr_t ictx, octx, dcbaap; |
62c6ae04 HM |
2091 | uint64_t poctx; |
2092 | uint32_t ictl_ctx[2]; | |
2093 | uint32_t slot_ctx[4]; | |
2094 | uint32_t ep0_ctx[5]; | |
62c6ae04 HM |
2095 | int i; |
2096 | TRBCCode res; | |
2097 | ||
348f1037 | 2098 | trace_usb_xhci_slot_address(slotid); |
91062ae0 | 2099 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2100 | |
2101 | dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); | |
616b5d53 | 2102 | poctx = ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid); |
62c6ae04 | 2103 | ictx = xhci_mask64(pictx); |
616b5d53 | 2104 | octx = xhci_mask64(poctx); |
62c6ae04 | 2105 | |
59a70ccd DG |
2106 | DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
2107 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); | |
62c6ae04 | 2108 | |
616b5d53 | 2109 | xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); |
62c6ae04 HM |
2110 | |
2111 | if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { | |
2112 | fprintf(stderr, "xhci: invalid input context control %08x %08x\n", | |
2113 | ictl_ctx[0], ictl_ctx[1]); | |
2114 | return CC_TRB_ERROR; | |
2115 | } | |
2116 | ||
616b5d53 DG |
2117 | xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); |
2118 | xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); | |
62c6ae04 HM |
2119 | |
2120 | DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", | |
2121 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2122 | ||
2123 | DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", | |
2124 | ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); | |
2125 | ||
ccaf87a0 GH |
2126 | uport = xhci_lookup_uport(xhci, slot_ctx); |
2127 | if (uport == NULL) { | |
2128 | fprintf(stderr, "xhci: port not found\n"); | |
62c6ae04 | 2129 | return CC_TRB_ERROR; |
ccaf87a0 GH |
2130 | } |
2131 | ||
2132 | dev = uport->dev; | |
2133 | if (!dev) { | |
2134 | fprintf(stderr, "xhci: port %s not connected\n", uport->path); | |
62c6ae04 HM |
2135 | return CC_USB_TRANSACTION_ERROR; |
2136 | } | |
2137 | ||
91062ae0 | 2138 | for (i = 0; i < xhci->numslots; i++) { |
0bc85da6 GH |
2139 | if (i == slotid-1) { |
2140 | continue; | |
2141 | } | |
ccaf87a0 GH |
2142 | if (xhci->slots[i].uport == uport) { |
2143 | fprintf(stderr, "xhci: port %s already assigned to slot %d\n", | |
2144 | uport->path, i+1); | |
62c6ae04 HM |
2145 | return CC_TRB_ERROR; |
2146 | } | |
2147 | } | |
2148 | ||
2149 | slot = &xhci->slots[slotid-1]; | |
ccaf87a0 | 2150 | slot->uport = uport; |
62c6ae04 HM |
2151 | slot->ctx = octx; |
2152 | ||
2153 | if (bsr) { | |
2154 | slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; | |
2155 | } else { | |
a820b575 | 2156 | USBPacket p; |
a6718874 GH |
2157 | uint8_t buf[1]; |
2158 | ||
af203be3 | 2159 | slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; |
0bc85da6 | 2160 | usb_device_reset(dev); |
a6718874 GH |
2161 | memset(&p, 0, sizeof(p)); |
2162 | usb_packet_addbuf(&p, buf, sizeof(buf)); | |
a820b575 | 2163 | usb_packet_setup(&p, USB_TOKEN_OUT, |
8550a02d | 2164 | usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, |
a820b575 GH |
2165 | 0, false, false); |
2166 | usb_device_handle_control(dev, &p, | |
62c6ae04 | 2167 | DeviceOutRequest | USB_REQ_SET_ADDRESS, |
af203be3 | 2168 | slotid, 0, 0, NULL); |
a820b575 | 2169 | assert(p.status != USB_RET_ASYNC); |
62c6ae04 HM |
2170 | } |
2171 | ||
2172 | res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); | |
2173 | ||
2174 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2175 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2176 | DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", | |
2177 | ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); | |
2178 | ||
616b5d53 DG |
2179 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
2180 | xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); | |
62c6ae04 | 2181 | |
4034e693 | 2182 | xhci->slots[slotid-1].addressed = 1; |
62c6ae04 HM |
2183 | return res; |
2184 | } | |
2185 | ||
2186 | ||
2187 | static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, | |
2188 | uint64_t pictx, bool dc) | |
2189 | { | |
59a70ccd | 2190 | dma_addr_t ictx, octx; |
62c6ae04 HM |
2191 | uint32_t ictl_ctx[2]; |
2192 | uint32_t slot_ctx[4]; | |
2193 | uint32_t islot_ctx[4]; | |
2194 | uint32_t ep_ctx[5]; | |
2195 | int i; | |
2196 | TRBCCode res; | |
2197 | ||
348f1037 | 2198 | trace_usb_xhci_slot_configure(slotid); |
91062ae0 | 2199 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2200 | |
2201 | ictx = xhci_mask64(pictx); | |
2202 | octx = xhci->slots[slotid-1].ctx; | |
2203 | ||
59a70ccd DG |
2204 | DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
2205 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); | |
62c6ae04 HM |
2206 | |
2207 | if (dc) { | |
2208 | for (i = 2; i <= 31; i++) { | |
2209 | if (xhci->slots[slotid-1].eps[i-1]) { | |
2210 | xhci_disable_ep(xhci, slotid, i); | |
2211 | } | |
2212 | } | |
2213 | ||
616b5d53 | 2214 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2215 | slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); |
2216 | slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; | |
2217 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2218 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
616b5d53 | 2219 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2220 | |
2221 | return CC_SUCCESS; | |
2222 | } | |
2223 | ||
616b5d53 | 2224 | xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); |
62c6ae04 HM |
2225 | |
2226 | if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { | |
2227 | fprintf(stderr, "xhci: invalid input context control %08x %08x\n", | |
2228 | ictl_ctx[0], ictl_ctx[1]); | |
2229 | return CC_TRB_ERROR; | |
2230 | } | |
2231 | ||
616b5d53 DG |
2232 | xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); |
2233 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); | |
62c6ae04 HM |
2234 | |
2235 | if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { | |
2236 | fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]); | |
2237 | return CC_CONTEXT_STATE_ERROR; | |
2238 | } | |
2239 | ||
2240 | for (i = 2; i <= 31; i++) { | |
2241 | if (ictl_ctx[0] & (1<<i)) { | |
2242 | xhci_disable_ep(xhci, slotid, i); | |
2243 | } | |
2244 | if (ictl_ctx[1] & (1<<i)) { | |
616b5d53 | 2245 | xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); |
62c6ae04 HM |
2246 | DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", |
2247 | i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], | |
2248 | ep_ctx[3], ep_ctx[4]); | |
2249 | xhci_disable_ep(xhci, slotid, i); | |
2250 | res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); | |
2251 | if (res != CC_SUCCESS) { | |
2252 | return res; | |
2253 | } | |
2254 | DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", | |
2255 | i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], | |
2256 | ep_ctx[3], ep_ctx[4]); | |
616b5d53 | 2257 | xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); |
62c6ae04 HM |
2258 | } |
2259 | } | |
2260 | ||
2261 | slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); | |
2262 | slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; | |
2263 | slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); | |
2264 | slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << | |
2265 | SLOT_CONTEXT_ENTRIES_SHIFT); | |
2266 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2267 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2268 | ||
616b5d53 | 2269 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2270 | |
2271 | return CC_SUCCESS; | |
2272 | } | |
2273 | ||
2274 | ||
2275 | static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, | |
2276 | uint64_t pictx) | |
2277 | { | |
59a70ccd | 2278 | dma_addr_t ictx, octx; |
62c6ae04 HM |
2279 | uint32_t ictl_ctx[2]; |
2280 | uint32_t iep0_ctx[5]; | |
2281 | uint32_t ep0_ctx[5]; | |
2282 | uint32_t islot_ctx[4]; | |
2283 | uint32_t slot_ctx[4]; | |
2284 | ||
348f1037 | 2285 | trace_usb_xhci_slot_evaluate(slotid); |
91062ae0 | 2286 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2287 | |
2288 | ictx = xhci_mask64(pictx); | |
2289 | octx = xhci->slots[slotid-1].ctx; | |
2290 | ||
59a70ccd DG |
2291 | DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); |
2292 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); | |
62c6ae04 | 2293 | |
616b5d53 | 2294 | xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); |
62c6ae04 HM |
2295 | |
2296 | if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { | |
2297 | fprintf(stderr, "xhci: invalid input context control %08x %08x\n", | |
2298 | ictl_ctx[0], ictl_ctx[1]); | |
2299 | return CC_TRB_ERROR; | |
2300 | } | |
2301 | ||
2302 | if (ictl_ctx[1] & 0x1) { | |
616b5d53 | 2303 | xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); |
62c6ae04 HM |
2304 | |
2305 | DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", | |
2306 | islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); | |
2307 | ||
616b5d53 | 2308 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2309 | |
2310 | slot_ctx[1] &= ~0xFFFF; /* max exit latency */ | |
2311 | slot_ctx[1] |= islot_ctx[1] & 0xFFFF; | |
2312 | slot_ctx[2] &= ~0xFF00000; /* interrupter target */ | |
2313 | slot_ctx[2] |= islot_ctx[2] & 0xFF000000; | |
2314 | ||
2315 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2316 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
2317 | ||
616b5d53 | 2318 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2319 | } |
2320 | ||
2321 | if (ictl_ctx[1] & 0x2) { | |
616b5d53 | 2322 | xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); |
62c6ae04 HM |
2323 | |
2324 | DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", | |
2325 | iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], | |
2326 | iep0_ctx[3], iep0_ctx[4]); | |
2327 | ||
616b5d53 | 2328 | xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
62c6ae04 HM |
2329 | |
2330 | ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ | |
2331 | ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; | |
2332 | ||
2333 | DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", | |
2334 | ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); | |
2335 | ||
616b5d53 | 2336 | xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); |
62c6ae04 HM |
2337 | } |
2338 | ||
2339 | return CC_SUCCESS; | |
2340 | } | |
2341 | ||
2342 | static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) | |
2343 | { | |
2344 | uint32_t slot_ctx[4]; | |
59a70ccd | 2345 | dma_addr_t octx; |
62c6ae04 HM |
2346 | int i; |
2347 | ||
348f1037 | 2348 | trace_usb_xhci_slot_reset(slotid); |
91062ae0 | 2349 | assert(slotid >= 1 && slotid <= xhci->numslots); |
62c6ae04 HM |
2350 | |
2351 | octx = xhci->slots[slotid-1].ctx; | |
2352 | ||
59a70ccd | 2353 | DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); |
62c6ae04 HM |
2354 | |
2355 | for (i = 2; i <= 31; i++) { | |
2356 | if (xhci->slots[slotid-1].eps[i-1]) { | |
2357 | xhci_disable_ep(xhci, slotid, i); | |
2358 | } | |
2359 | } | |
2360 | ||
616b5d53 | 2361 | xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2362 | slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); |
2363 | slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; | |
2364 | DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", | |
2365 | slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); | |
616b5d53 | 2366 | xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); |
62c6ae04 HM |
2367 | |
2368 | return CC_SUCCESS; | |
2369 | } | |
2370 | ||
2371 | static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) | |
2372 | { | |
2373 | unsigned int slotid; | |
2374 | slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; | |
91062ae0 | 2375 | if (slotid < 1 || slotid > xhci->numslots) { |
62c6ae04 HM |
2376 | fprintf(stderr, "xhci: bad slot id %d\n", slotid); |
2377 | event->ccode = CC_TRB_ERROR; | |
2378 | return 0; | |
2379 | } else if (!xhci->slots[slotid-1].enabled) { | |
2380 | fprintf(stderr, "xhci: slot id %d not enabled\n", slotid); | |
2381 | event->ccode = CC_SLOT_NOT_ENABLED_ERROR; | |
2382 | return 0; | |
2383 | } | |
2384 | return slotid; | |
2385 | } | |
2386 | ||
81251841 GH |
2387 | /* cleanup slot state on usb device detach */ |
2388 | static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) | |
2389 | { | |
0cb41e2c | 2390 | int slot, ep; |
81251841 GH |
2391 | |
2392 | for (slot = 0; slot < xhci->numslots; slot++) { | |
2393 | if (xhci->slots[slot].uport == uport) { | |
2394 | break; | |
2395 | } | |
2396 | } | |
2397 | if (slot == xhci->numslots) { | |
2398 | return; | |
2399 | } | |
2400 | ||
0cb41e2c GH |
2401 | for (ep = 0; ep < 31; ep++) { |
2402 | if (xhci->slots[slot].eps[ep]) { | |
2403 | xhci_ep_nuke_xfers(xhci, slot+1, ep+1); | |
2404 | } | |
2405 | } | |
81251841 GH |
2406 | xhci->slots[slot].uport = NULL; |
2407 | } | |
2408 | ||
62c6ae04 HM |
2409 | static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) |
2410 | { | |
59a70ccd | 2411 | dma_addr_t ctx; |
0846e635 | 2412 | uint8_t bw_ctx[xhci->numports+1]; |
62c6ae04 HM |
2413 | |
2414 | DPRINTF("xhci_get_port_bandwidth()\n"); | |
2415 | ||
2416 | ctx = xhci_mask64(pctx); | |
2417 | ||
59a70ccd | 2418 | DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); |
62c6ae04 HM |
2419 | |
2420 | /* TODO: actually implement real values here */ | |
2421 | bw_ctx[0] = 0; | |
0846e635 | 2422 | memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ |
59a70ccd | 2423 | pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx)); |
62c6ae04 HM |
2424 | |
2425 | return CC_SUCCESS; | |
2426 | } | |
2427 | ||
2428 | static uint32_t rotl(uint32_t v, unsigned count) | |
2429 | { | |
2430 | count &= 31; | |
2431 | return (v << count) | (v >> (32 - count)); | |
2432 | } | |
2433 | ||
2434 | ||
2435 | static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) | |
2436 | { | |
2437 | uint32_t val; | |
2438 | val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); | |
2439 | val += rotl(lo + 0x49434878, hi & 0x1F); | |
2440 | val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); | |
2441 | return ~val; | |
2442 | } | |
2443 | ||
59a70ccd | 2444 | static void xhci_via_challenge(XHCIState *xhci, uint64_t addr) |
62c6ae04 HM |
2445 | { |
2446 | uint32_t buf[8]; | |
2447 | uint32_t obuf[8]; | |
59a70ccd | 2448 | dma_addr_t paddr = xhci_mask64(addr); |
62c6ae04 | 2449 | |
59a70ccd | 2450 | pci_dma_read(&xhci->pci_dev, paddr, &buf, 32); |
62c6ae04 HM |
2451 | |
2452 | memcpy(obuf, buf, sizeof(obuf)); | |
2453 | ||
2454 | if ((buf[0] & 0xff) == 2) { | |
2455 | obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3]; | |
2456 | obuf[0] |= (buf[2] * buf[3]) & 0xff; | |
2457 | obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3]; | |
2458 | obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3]; | |
2459 | obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3]; | |
2460 | obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3]; | |
2461 | obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3]; | |
2462 | obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956; | |
2463 | obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593; | |
2464 | } | |
2465 | ||
59a70ccd | 2466 | pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32); |
62c6ae04 HM |
2467 | } |
2468 | ||
2469 | static void xhci_process_commands(XHCIState *xhci) | |
2470 | { | |
2471 | XHCITRB trb; | |
2472 | TRBType type; | |
2473 | XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; | |
59a70ccd | 2474 | dma_addr_t addr; |
62c6ae04 HM |
2475 | unsigned int i, slotid = 0; |
2476 | ||
2477 | DPRINTF("xhci_process_commands()\n"); | |
2478 | if (!xhci_running(xhci)) { | |
2479 | DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); | |
2480 | return; | |
2481 | } | |
2482 | ||
2483 | xhci->crcr_low |= CRCR_CRR; | |
2484 | ||
2485 | while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { | |
2486 | event.ptr = addr; | |
2487 | switch (type) { | |
2488 | case CR_ENABLE_SLOT: | |
91062ae0 | 2489 | for (i = 0; i < xhci->numslots; i++) { |
62c6ae04 HM |
2490 | if (!xhci->slots[i].enabled) { |
2491 | break; | |
2492 | } | |
2493 | } | |
91062ae0 | 2494 | if (i >= xhci->numslots) { |
62c6ae04 HM |
2495 | fprintf(stderr, "xhci: no device slots available\n"); |
2496 | event.ccode = CC_NO_SLOTS_ERROR; | |
2497 | } else { | |
2498 | slotid = i+1; | |
2499 | event.ccode = xhci_enable_slot(xhci, slotid); | |
2500 | } | |
2501 | break; | |
2502 | case CR_DISABLE_SLOT: | |
2503 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2504 | if (slotid) { | |
2505 | event.ccode = xhci_disable_slot(xhci, slotid); | |
2506 | } | |
2507 | break; | |
2508 | case CR_ADDRESS_DEVICE: | |
2509 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2510 | if (slotid) { | |
2511 | event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, | |
2512 | trb.control & TRB_CR_BSR); | |
2513 | } | |
2514 | break; | |
2515 | case CR_CONFIGURE_ENDPOINT: | |
2516 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2517 | if (slotid) { | |
2518 | event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, | |
2519 | trb.control & TRB_CR_DC); | |
2520 | } | |
2521 | break; | |
2522 | case CR_EVALUATE_CONTEXT: | |
2523 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2524 | if (slotid) { | |
2525 | event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); | |
2526 | } | |
2527 | break; | |
2528 | case CR_STOP_ENDPOINT: | |
2529 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2530 | if (slotid) { | |
2531 | unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) | |
2532 | & TRB_CR_EPID_MASK; | |
2533 | event.ccode = xhci_stop_ep(xhci, slotid, epid); | |
2534 | } | |
2535 | break; | |
2536 | case CR_RESET_ENDPOINT: | |
2537 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2538 | if (slotid) { | |
2539 | unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) | |
2540 | & TRB_CR_EPID_MASK; | |
2541 | event.ccode = xhci_reset_ep(xhci, slotid, epid); | |
2542 | } | |
2543 | break; | |
2544 | case CR_SET_TR_DEQUEUE: | |
2545 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2546 | if (slotid) { | |
2547 | unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) | |
2548 | & TRB_CR_EPID_MASK; | |
024426ac GH |
2549 | unsigned int streamid = (trb.status >> 16) & 0xffff; |
2550 | event.ccode = xhci_set_ep_dequeue(xhci, slotid, | |
2551 | epid, streamid, | |
62c6ae04 HM |
2552 | trb.parameter); |
2553 | } | |
2554 | break; | |
2555 | case CR_RESET_DEVICE: | |
2556 | slotid = xhci_get_slot(xhci, &event, &trb); | |
2557 | if (slotid) { | |
2558 | event.ccode = xhci_reset_slot(xhci, slotid); | |
2559 | } | |
2560 | break; | |
2561 | case CR_GET_PORT_BANDWIDTH: | |
2562 | event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); | |
2563 | break; | |
2564 | case CR_VENDOR_VIA_CHALLENGE_RESPONSE: | |
59a70ccd | 2565 | xhci_via_challenge(xhci, trb.parameter); |
62c6ae04 HM |
2566 | break; |
2567 | case CR_VENDOR_NEC_FIRMWARE_REVISION: | |
2568 | event.type = 48; /* NEC reply */ | |
2569 | event.length = 0x3025; | |
2570 | break; | |
2571 | case CR_VENDOR_NEC_CHALLENGE_RESPONSE: | |
2572 | { | |
2573 | uint32_t chi = trb.parameter >> 32; | |
2574 | uint32_t clo = trb.parameter; | |
2575 | uint32_t val = xhci_nec_challenge(chi, clo); | |
2576 | event.length = val & 0xFFFF; | |
2577 | event.epid = val >> 16; | |
2578 | slotid = val >> 24; | |
2579 | event.type = 48; /* NEC reply */ | |
2580 | } | |
2581 | break; | |
2582 | default: | |
0ab966cf | 2583 | trace_usb_xhci_unimplemented("command", type); |
62c6ae04 HM |
2584 | event.ccode = CC_TRB_ERROR; |
2585 | break; | |
2586 | } | |
2587 | event.slotid = slotid; | |
2d1de850 | 2588 | xhci_event(xhci, &event, 0); |
62c6ae04 HM |
2589 | } |
2590 | } | |
2591 | ||
6a32f80f GH |
2592 | static bool xhci_port_have_device(XHCIPort *port) |
2593 | { | |
2594 | if (!port->uport->dev || !port->uport->dev->attached) { | |
2595 | return false; /* no device present */ | |
2596 | } | |
2597 | if (!((1 << port->uport->dev->speed) & port->speedmask)) { | |
2598 | return false; /* speed mismatch */ | |
2599 | } | |
2600 | return true; | |
2601 | } | |
2602 | ||
f705a362 GH |
2603 | static void xhci_port_notify(XHCIPort *port, uint32_t bits) |
2604 | { | |
2605 | XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, | |
2606 | port->portnr << 24 }; | |
2607 | ||
2608 | if ((port->portsc & bits) == bits) { | |
2609 | return; | |
2610 | } | |
bdfce20d | 2611 | trace_usb_xhci_port_notify(port->portnr, bits); |
f705a362 GH |
2612 | port->portsc |= bits; |
2613 | if (!xhci_running(port->xhci)) { | |
2614 | return; | |
2615 | } | |
2616 | xhci_event(port->xhci, &ev, 0); | |
2617 | } | |
2618 | ||
f3214027 | 2619 | static void xhci_port_update(XHCIPort *port, int is_detach) |
62c6ae04 | 2620 | { |
b62b0828 GH |
2621 | uint32_t pls = PLS_RX_DETECT; |
2622 | ||
62c6ae04 | 2623 | port->portsc = PORTSC_PP; |
6a32f80f | 2624 | if (!is_detach && xhci_port_have_device(port)) { |
62c6ae04 | 2625 | port->portsc |= PORTSC_CCS; |
0846e635 | 2626 | switch (port->uport->dev->speed) { |
62c6ae04 HM |
2627 | case USB_SPEED_LOW: |
2628 | port->portsc |= PORTSC_SPEED_LOW; | |
b62b0828 | 2629 | pls = PLS_POLLING; |
62c6ae04 HM |
2630 | break; |
2631 | case USB_SPEED_FULL: | |
2632 | port->portsc |= PORTSC_SPEED_FULL; | |
b62b0828 | 2633 | pls = PLS_POLLING; |
62c6ae04 HM |
2634 | break; |
2635 | case USB_SPEED_HIGH: | |
2636 | port->portsc |= PORTSC_SPEED_HIGH; | |
b62b0828 | 2637 | pls = PLS_POLLING; |
62c6ae04 | 2638 | break; |
0846e635 GH |
2639 | case USB_SPEED_SUPER: |
2640 | port->portsc |= PORTSC_SPEED_SUPER; | |
b62b0828 GH |
2641 | port->portsc |= PORTSC_PED; |
2642 | pls = PLS_U0; | |
0846e635 | 2643 | break; |
62c6ae04 HM |
2644 | } |
2645 | } | |
b62b0828 | 2646 | set_field(&port->portsc, pls, PORTSC_PLS); |
4f47f0f8 | 2647 | trace_usb_xhci_port_link(port->portnr, pls); |
f705a362 | 2648 | xhci_port_notify(port, PORTSC_CSC); |
62c6ae04 HM |
2649 | } |
2650 | ||
40030130 GH |
2651 | static void xhci_port_reset(XHCIPort *port) |
2652 | { | |
4f47f0f8 GH |
2653 | trace_usb_xhci_port_reset(port->portnr); |
2654 | ||
b62b0828 GH |
2655 | if (!xhci_port_have_device(port)) { |
2656 | return; | |
2657 | } | |
2658 | ||
40030130 | 2659 | usb_device_reset(port->uport->dev); |
b62b0828 GH |
2660 | |
2661 | switch (port->uport->dev->speed) { | |
2662 | case USB_SPEED_LOW: | |
2663 | case USB_SPEED_FULL: | |
2664 | case USB_SPEED_HIGH: | |
2665 | set_field(&port->portsc, PLS_U0, PORTSC_PLS); | |
4f47f0f8 | 2666 | trace_usb_xhci_port_link(port->portnr, PLS_U0); |
b62b0828 GH |
2667 | port->portsc |= PORTSC_PED; |
2668 | break; | |
2669 | } | |
2670 | ||
2671 | port->portsc &= ~PORTSC_PR; | |
2672 | xhci_port_notify(port, PORTSC_PRC); | |
40030130 GH |
2673 | } |
2674 | ||
64619739 | 2675 | static void xhci_reset(DeviceState *dev) |
62c6ae04 | 2676 | { |
64619739 | 2677 | XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); |
62c6ae04 HM |
2678 | int i; |
2679 | ||
2d754a10 | 2680 | trace_usb_xhci_reset(); |
62c6ae04 HM |
2681 | if (!(xhci->usbsts & USBSTS_HCH)) { |
2682 | fprintf(stderr, "xhci: reset while running!\n"); | |
2683 | } | |
2684 | ||
2685 | xhci->usbcmd = 0; | |
2686 | xhci->usbsts = USBSTS_HCH; | |
2687 | xhci->dnctrl = 0; | |
2688 | xhci->crcr_low = 0; | |
2689 | xhci->crcr_high = 0; | |
2690 | xhci->dcbaap_low = 0; | |
2691 | xhci->dcbaap_high = 0; | |
2692 | xhci->config = 0; | |
62c6ae04 | 2693 | |
91062ae0 | 2694 | for (i = 0; i < xhci->numslots; i++) { |
62c6ae04 HM |
2695 | xhci_disable_slot(xhci, i+1); |
2696 | } | |
2697 | ||
0846e635 | 2698 | for (i = 0; i < xhci->numports; i++) { |
f3214027 | 2699 | xhci_port_update(xhci->ports + i, 0); |
62c6ae04 HM |
2700 | } |
2701 | ||
91062ae0 | 2702 | for (i = 0; i < xhci->numintrs; i++) { |
962d11e1 GH |
2703 | xhci->intr[i].iman = 0; |
2704 | xhci->intr[i].imod = 0; | |
2705 | xhci->intr[i].erstsz = 0; | |
2706 | xhci->intr[i].erstba_low = 0; | |
2707 | xhci->intr[i].erstba_high = 0; | |
2708 | xhci->intr[i].erdp_low = 0; | |
2709 | xhci->intr[i].erdp_high = 0; | |
2710 | xhci->intr[i].msix_used = 0; | |
62c6ae04 | 2711 | |
962d11e1 GH |
2712 | xhci->intr[i].er_ep_idx = 0; |
2713 | xhci->intr[i].er_pcs = 1; | |
2714 | xhci->intr[i].er_full = 0; | |
2715 | xhci->intr[i].ev_buffer_put = 0; | |
2716 | xhci->intr[i].ev_buffer_get = 0; | |
2717 | } | |
01546fa6 GH |
2718 | |
2719 | xhci->mfindex_start = qemu_get_clock_ns(vm_clock); | |
2720 | xhci_mfwrap_update(xhci); | |
62c6ae04 HM |
2721 | } |
2722 | ||
a8170e5e | 2723 | static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) |
62c6ae04 | 2724 | { |
1b067564 | 2725 | XHCIState *xhci = ptr; |
2d754a10 | 2726 | uint32_t ret; |
62c6ae04 HM |
2727 | |
2728 | switch (reg) { | |
2729 | case 0x00: /* HCIVERSION, CAPLENGTH */ | |
2d754a10 GH |
2730 | ret = 0x01000000 | LEN_CAP; |
2731 | break; | |
62c6ae04 | 2732 | case 0x04: /* HCSPARAMS 1 */ |
0846e635 | 2733 | ret = ((xhci->numports_2+xhci->numports_3)<<24) |
91062ae0 | 2734 | | (xhci->numintrs<<8) | xhci->numslots; |
2d754a10 | 2735 | break; |
62c6ae04 | 2736 | case 0x08: /* HCSPARAMS 2 */ |
2d754a10 GH |
2737 | ret = 0x0000000f; |
2738 | break; | |
62c6ae04 | 2739 | case 0x0c: /* HCSPARAMS 3 */ |
2d754a10 GH |
2740 | ret = 0x00000000; |
2741 | break; | |
62c6ae04 | 2742 | case 0x10: /* HCCPARAMS */ |
2d754a10 | 2743 | if (sizeof(dma_addr_t) == 4) { |
024426ac | 2744 | ret = 0x00087000; |
2d754a10 | 2745 | } else { |
024426ac | 2746 | ret = 0x00087001; |
2d754a10 GH |
2747 | } |
2748 | break; | |
62c6ae04 | 2749 | case 0x14: /* DBOFF */ |
2d754a10 GH |
2750 | ret = OFF_DOORBELL; |
2751 | break; | |
62c6ae04 | 2752 | case 0x18: /* RTSOFF */ |
2d754a10 GH |
2753 | ret = OFF_RUNTIME; |
2754 | break; | |
62c6ae04 HM |
2755 | |
2756 | /* extended capabilities */ | |
2757 | case 0x20: /* Supported Protocol:00 */ | |
2d754a10 GH |
2758 | ret = 0x02000402; /* USB 2.0 */ |
2759 | break; | |
62c6ae04 | 2760 | case 0x24: /* Supported Protocol:04 */ |
0ebfb144 | 2761 | ret = 0x20425355; /* "USB " */ |
2d754a10 | 2762 | break; |
62c6ae04 | 2763 | case 0x28: /* Supported Protocol:08 */ |
0846e635 | 2764 | ret = 0x00000001 | (xhci->numports_2<<8); |
2d754a10 | 2765 | break; |
62c6ae04 | 2766 | case 0x2c: /* Supported Protocol:0c */ |
2d754a10 GH |
2767 | ret = 0x00000000; /* reserved */ |
2768 | break; | |
62c6ae04 | 2769 | case 0x30: /* Supported Protocol:00 */ |
2d754a10 GH |
2770 | ret = 0x03000002; /* USB 3.0 */ |
2771 | break; | |
62c6ae04 | 2772 | case 0x34: /* Supported Protocol:04 */ |
0ebfb144 | 2773 | ret = 0x20425355; /* "USB " */ |
2d754a10 | 2774 | break; |
62c6ae04 | 2775 | case 0x38: /* Supported Protocol:08 */ |
0846e635 | 2776 | ret = 0x00000000 | (xhci->numports_2+1) | (xhci->numports_3<<8); |
2d754a10 | 2777 | break; |
62c6ae04 | 2778 | case 0x3c: /* Supported Protocol:0c */ |
2d754a10 GH |
2779 | ret = 0x00000000; /* reserved */ |
2780 | break; | |
62c6ae04 | 2781 | default: |
0ab966cf | 2782 | trace_usb_xhci_unimplemented("cap read", reg); |
2d754a10 | 2783 | ret = 0; |
62c6ae04 | 2784 | } |
2d754a10 GH |
2785 | |
2786 | trace_usb_xhci_cap_read(reg, ret); | |
2787 | return ret; | |
62c6ae04 HM |
2788 | } |
2789 | ||
a8170e5e | 2790 | static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) |
62c6ae04 | 2791 | { |
1d8a4e69 | 2792 | XHCIPort *port = ptr; |
2d754a10 GH |
2793 | uint32_t ret; |
2794 | ||
1d8a4e69 | 2795 | switch (reg) { |
62c6ae04 | 2796 | case 0x00: /* PORTSC */ |
1d8a4e69 | 2797 | ret = port->portsc; |
2d754a10 | 2798 | break; |
62c6ae04 HM |
2799 | case 0x04: /* PORTPMSC */ |
2800 | case 0x08: /* PORTLI */ | |
2d754a10 GH |
2801 | ret = 0; |
2802 | break; | |
62c6ae04 HM |
2803 | case 0x0c: /* reserved */ |
2804 | default: | |
0ab966cf | 2805 | trace_usb_xhci_unimplemented("port read", reg); |
2d754a10 | 2806 | ret = 0; |
62c6ae04 | 2807 | } |
2d754a10 | 2808 | |
1d8a4e69 | 2809 | trace_usb_xhci_port_read(port->portnr, reg, ret); |
2d754a10 | 2810 | return ret; |
62c6ae04 HM |
2811 | } |
2812 | ||
a8170e5e | 2813 | static void xhci_port_write(void *ptr, hwaddr reg, |
1d8a4e69 | 2814 | uint64_t val, unsigned size) |
62c6ae04 | 2815 | { |
1d8a4e69 | 2816 | XHCIPort *port = ptr; |
bdfce20d | 2817 | uint32_t portsc, notify; |
62c6ae04 | 2818 | |
1d8a4e69 | 2819 | trace_usb_xhci_port_write(port->portnr, reg, val); |
2d754a10 | 2820 | |
1d8a4e69 | 2821 | switch (reg) { |
62c6ae04 | 2822 | case 0x00: /* PORTSC */ |
bdfce20d GH |
2823 | /* write-1-to-start bits */ |
2824 | if (val & PORTSC_PR) { | |
2825 | xhci_port_reset(port); | |
2826 | break; | |
2827 | } | |
2828 | ||
1d8a4e69 | 2829 | portsc = port->portsc; |
bdfce20d | 2830 | notify = 0; |
62c6ae04 HM |
2831 | /* write-1-to-clear bits*/ |
2832 | portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| | |
2833 | PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); | |
2834 | if (val & PORTSC_LWS) { | |
2835 | /* overwrite PLS only when LWS=1 */ | |
bdfce20d GH |
2836 | uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); |
2837 | uint32_t new_pls = get_field(val, PORTSC_PLS); | |
2838 | switch (new_pls) { | |
2839 | case PLS_U0: | |
2840 | if (old_pls != PLS_U0) { | |
2841 | set_field(&portsc, new_pls, PORTSC_PLS); | |
2842 | trace_usb_xhci_port_link(port->portnr, new_pls); | |
2843 | notify = PORTSC_PLC; | |
2844 | } | |
2845 | break; | |
2846 | case PLS_U3: | |
2847 | if (old_pls < PLS_U3) { | |
2848 | set_field(&portsc, new_pls, PORTSC_PLS); | |
2849 | trace_usb_xhci_port_link(port->portnr, new_pls); | |
2850 | } | |
2851 | break; | |
2852 | case PLS_RESUME: | |
2853 | /* windows does this for some reason, don't spam stderr */ | |
2854 | break; | |
2855 | default: | |
2856 | fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n", | |
2857 | __func__, old_pls, new_pls); | |
2858 | break; | |
2859 | } | |
62c6ae04 HM |
2860 | } |
2861 | /* read/write bits */ | |
2862 | portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); | |
2863 | portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); | |
40030130 | 2864 | port->portsc = portsc; |
bdfce20d GH |
2865 | if (notify) { |
2866 | xhci_port_notify(port, notify); | |
62c6ae04 | 2867 | } |
62c6ae04 HM |
2868 | break; |
2869 | case 0x04: /* PORTPMSC */ | |
2870 | case 0x08: /* PORTLI */ | |
2871 | default: | |
0ab966cf | 2872 | trace_usb_xhci_unimplemented("port write", reg); |
62c6ae04 HM |
2873 | } |
2874 | } | |
2875 | ||
a8170e5e | 2876 | static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) |
62c6ae04 | 2877 | { |
1b067564 | 2878 | XHCIState *xhci = ptr; |
2d754a10 | 2879 | uint32_t ret; |
62c6ae04 | 2880 | |
62c6ae04 HM |
2881 | switch (reg) { |
2882 | case 0x00: /* USBCMD */ | |
2d754a10 GH |
2883 | ret = xhci->usbcmd; |
2884 | break; | |
62c6ae04 | 2885 | case 0x04: /* USBSTS */ |
2d754a10 GH |
2886 | ret = xhci->usbsts; |
2887 | break; | |
62c6ae04 | 2888 | case 0x08: /* PAGESIZE */ |
2d754a10 GH |
2889 | ret = 1; /* 4KiB */ |
2890 | break; | |
62c6ae04 | 2891 | case 0x14: /* DNCTRL */ |
2d754a10 GH |
2892 | ret = xhci->dnctrl; |
2893 | break; | |
62c6ae04 | 2894 | case 0x18: /* CRCR low */ |
2d754a10 GH |
2895 | ret = xhci->crcr_low & ~0xe; |
2896 | break; | |
62c6ae04 | 2897 | case 0x1c: /* CRCR high */ |
2d754a10 GH |
2898 | ret = xhci->crcr_high; |
2899 | break; | |
62c6ae04 | 2900 | case 0x30: /* DCBAAP low */ |
2d754a10 GH |
2901 | ret = xhci->dcbaap_low; |
2902 | break; | |
62c6ae04 | 2903 | case 0x34: /* DCBAAP high */ |
2d754a10 GH |
2904 | ret = xhci->dcbaap_high; |
2905 | break; | |
62c6ae04 | 2906 | case 0x38: /* CONFIG */ |
2d754a10 GH |
2907 | ret = xhci->config; |
2908 | break; | |
62c6ae04 | 2909 | default: |
0ab966cf | 2910 | trace_usb_xhci_unimplemented("oper read", reg); |
2d754a10 | 2911 | ret = 0; |
62c6ae04 | 2912 | } |
2d754a10 GH |
2913 | |
2914 | trace_usb_xhci_oper_read(reg, ret); | |
2915 | return ret; | |
62c6ae04 HM |
2916 | } |
2917 | ||
a8170e5e | 2918 | static void xhci_oper_write(void *ptr, hwaddr reg, |
1b067564 | 2919 | uint64_t val, unsigned size) |
62c6ae04 | 2920 | { |
1b067564 GH |
2921 | XHCIState *xhci = ptr; |
2922 | ||
2d754a10 GH |
2923 | trace_usb_xhci_oper_write(reg, val); |
2924 | ||
62c6ae04 HM |
2925 | switch (reg) { |
2926 | case 0x00: /* USBCMD */ | |
2927 | if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { | |
2928 | xhci_run(xhci); | |
2929 | } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { | |
2930 | xhci_stop(xhci); | |
2931 | } | |
2932 | xhci->usbcmd = val & 0xc0f; | |
01546fa6 | 2933 | xhci_mfwrap_update(xhci); |
62c6ae04 | 2934 | if (val & USBCMD_HCRST) { |
64619739 | 2935 | xhci_reset(&xhci->pci_dev.qdev); |
62c6ae04 | 2936 | } |
4c4abe7c | 2937 | xhci_intx_update(xhci); |
62c6ae04 HM |
2938 | break; |
2939 | ||
2940 | case 0x04: /* USBSTS */ | |
2941 | /* these bits are write-1-to-clear */ | |
2942 | xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); | |
4c4abe7c | 2943 | xhci_intx_update(xhci); |
62c6ae04 HM |
2944 | break; |
2945 | ||
2946 | case 0x14: /* DNCTRL */ | |
2947 | xhci->dnctrl = val & 0xffff; | |
2948 | break; | |
2949 | case 0x18: /* CRCR low */ | |
2950 | xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); | |
2951 | break; | |
2952 | case 0x1c: /* CRCR high */ | |
2953 | xhci->crcr_high = val; | |
2954 | if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { | |
2955 | XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; | |
2956 | xhci->crcr_low &= ~CRCR_CRR; | |
2d1de850 | 2957 | xhci_event(xhci, &event, 0); |
62c6ae04 HM |
2958 | DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); |
2959 | } else { | |
59a70ccd | 2960 | dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); |
62c6ae04 HM |
2961 | xhci_ring_init(xhci, &xhci->cmd_ring, base); |
2962 | } | |
2963 | xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); | |
2964 | break; | |
2965 | case 0x30: /* DCBAAP low */ | |
2966 | xhci->dcbaap_low = val & 0xffffffc0; | |
2967 | break; | |
2968 | case 0x34: /* DCBAAP high */ | |
2969 | xhci->dcbaap_high = val; | |
2970 | break; | |
2971 | case 0x38: /* CONFIG */ | |
2972 | xhci->config = val & 0xff; | |
2973 | break; | |
2974 | default: | |
0ab966cf | 2975 | trace_usb_xhci_unimplemented("oper write", reg); |
62c6ae04 HM |
2976 | } |
2977 | } | |
2978 | ||
a8170e5e | 2979 | static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, |
1b067564 | 2980 | unsigned size) |
62c6ae04 | 2981 | { |
1b067564 | 2982 | XHCIState *xhci = ptr; |
43d9d604 | 2983 | uint32_t ret = 0; |
62c6ae04 | 2984 | |
43d9d604 GH |
2985 | if (reg < 0x20) { |
2986 | switch (reg) { | |
2987 | case 0x00: /* MFINDEX */ | |
2988 | ret = xhci_mfindex_get(xhci) & 0x3fff; | |
2989 | break; | |
2990 | default: | |
0ab966cf | 2991 | trace_usb_xhci_unimplemented("runtime read", reg); |
43d9d604 GH |
2992 | break; |
2993 | } | |
2994 | } else { | |
2995 | int v = (reg - 0x20) / 0x20; | |
2996 | XHCIInterrupter *intr = &xhci->intr[v]; | |
2997 | switch (reg & 0x1f) { | |
2998 | case 0x00: /* IMAN */ | |
2999 | ret = intr->iman; | |
3000 | break; | |
3001 | case 0x04: /* IMOD */ | |
3002 | ret = intr->imod; | |
3003 | break; | |
3004 | case 0x08: /* ERSTSZ */ | |
3005 | ret = intr->erstsz; | |
3006 | break; | |
3007 | case 0x10: /* ERSTBA low */ | |
3008 | ret = intr->erstba_low; | |
3009 | break; | |
3010 | case 0x14: /* ERSTBA high */ | |
3011 | ret = intr->erstba_high; | |
3012 | break; | |
3013 | case 0x18: /* ERDP low */ | |
3014 | ret = intr->erdp_low; | |
3015 | break; | |
3016 | case 0x1c: /* ERDP high */ | |
3017 | ret = intr->erdp_high; | |
3018 | break; | |
3019 | } | |
62c6ae04 | 3020 | } |
2d754a10 GH |
3021 | |
3022 | trace_usb_xhci_runtime_read(reg, ret); | |
3023 | return ret; | |
62c6ae04 HM |
3024 | } |
3025 | ||
a8170e5e | 3026 | static void xhci_runtime_write(void *ptr, hwaddr reg, |
1b067564 | 3027 | uint64_t val, unsigned size) |
62c6ae04 | 3028 | { |
1b067564 | 3029 | XHCIState *xhci = ptr; |
43d9d604 GH |
3030 | int v = (reg - 0x20) / 0x20; |
3031 | XHCIInterrupter *intr = &xhci->intr[v]; | |
8e9f18b6 | 3032 | trace_usb_xhci_runtime_write(reg, val); |
62c6ae04 | 3033 | |
43d9d604 | 3034 | if (reg < 0x20) { |
0ab966cf | 3035 | trace_usb_xhci_unimplemented("runtime write", reg); |
43d9d604 GH |
3036 | return; |
3037 | } | |
3038 | ||
3039 | switch (reg & 0x1f) { | |
3040 | case 0x00: /* IMAN */ | |
62c6ae04 | 3041 | if (val & IMAN_IP) { |
962d11e1 | 3042 | intr->iman &= ~IMAN_IP; |
62c6ae04 | 3043 | } |
962d11e1 GH |
3044 | intr->iman &= ~IMAN_IE; |
3045 | intr->iman |= val & IMAN_IE; | |
43d9d604 GH |
3046 | if (v == 0) { |
3047 | xhci_intx_update(xhci); | |
3048 | } | |
3049 | xhci_msix_update(xhci, v); | |
62c6ae04 | 3050 | break; |
43d9d604 | 3051 | case 0x04: /* IMOD */ |
962d11e1 | 3052 | intr->imod = val; |
62c6ae04 | 3053 | break; |
43d9d604 | 3054 | case 0x08: /* ERSTSZ */ |
962d11e1 | 3055 | intr->erstsz = val & 0xffff; |
62c6ae04 | 3056 | break; |
43d9d604 | 3057 | case 0x10: /* ERSTBA low */ |
62c6ae04 | 3058 | /* XXX NEC driver bug: it doesn't align this to 64 bytes |
962d11e1 GH |
3059 | intr->erstba_low = val & 0xffffffc0; */ |
3060 | intr->erstba_low = val & 0xfffffff0; | |
62c6ae04 | 3061 | break; |
43d9d604 | 3062 | case 0x14: /* ERSTBA high */ |
962d11e1 | 3063 | intr->erstba_high = val; |
43d9d604 | 3064 | xhci_er_reset(xhci, v); |
62c6ae04 | 3065 | break; |
43d9d604 | 3066 | case 0x18: /* ERDP low */ |
62c6ae04 | 3067 | if (val & ERDP_EHB) { |
962d11e1 | 3068 | intr->erdp_low &= ~ERDP_EHB; |
62c6ae04 | 3069 | } |
962d11e1 | 3070 | intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); |
62c6ae04 | 3071 | break; |
43d9d604 | 3072 | case 0x1c: /* ERDP high */ |
962d11e1 | 3073 | intr->erdp_high = val; |
43d9d604 | 3074 | xhci_events_update(xhci, v); |
62c6ae04 HM |
3075 | break; |
3076 | default: | |
0ab966cf | 3077 | trace_usb_xhci_unimplemented("oper write", reg); |
62c6ae04 HM |
3078 | } |
3079 | } | |
3080 | ||
a8170e5e | 3081 | static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, |
1b067564 | 3082 | unsigned size) |
62c6ae04 | 3083 | { |
62c6ae04 | 3084 | /* doorbells always read as 0 */ |
2d754a10 | 3085 | trace_usb_xhci_doorbell_read(reg, 0); |
62c6ae04 HM |
3086 | return 0; |
3087 | } | |
3088 | ||
a8170e5e | 3089 | static void xhci_doorbell_write(void *ptr, hwaddr reg, |
1b067564 | 3090 | uint64_t val, unsigned size) |
62c6ae04 | 3091 | { |
1b067564 | 3092 | XHCIState *xhci = ptr; |
024426ac | 3093 | unsigned int epid, streamid; |
1b067564 | 3094 | |
2d754a10 | 3095 | trace_usb_xhci_doorbell_write(reg, val); |
62c6ae04 HM |
3096 | |
3097 | if (!xhci_running(xhci)) { | |
3098 | fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n"); | |
3099 | return; | |
3100 | } | |
3101 | ||
3102 | reg >>= 2; | |
3103 | ||
3104 | if (reg == 0) { | |
3105 | if (val == 0) { | |
3106 | xhci_process_commands(xhci); | |
3107 | } else { | |
1b067564 GH |
3108 | fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", |
3109 | (uint32_t)val); | |
62c6ae04 HM |
3110 | } |
3111 | } else { | |
024426ac GH |
3112 | epid = val & 0xff; |
3113 | streamid = (val >> 16) & 0xffff; | |
91062ae0 | 3114 | if (reg > xhci->numslots) { |
1b067564 | 3115 | fprintf(stderr, "xhci: bad doorbell %d\n", (int)reg); |
024426ac | 3116 | } else if (epid > 31) { |
1b067564 GH |
3117 | fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", |
3118 | (int)reg, (uint32_t)val); | |
62c6ae04 | 3119 | } else { |
024426ac | 3120 | xhci_kick_ep(xhci, reg, epid, streamid); |
62c6ae04 HM |
3121 | } |
3122 | } | |
3123 | } | |
3124 | ||
6d3bc22e GH |
3125 | static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, |
3126 | unsigned width) | |
3127 | { | |
3128 | /* nothing */ | |
3129 | } | |
3130 | ||
1b067564 GH |
3131 | static const MemoryRegionOps xhci_cap_ops = { |
3132 | .read = xhci_cap_read, | |
6d3bc22e | 3133 | .write = xhci_cap_write, |
6ee021d4 | 3134 | .valid.min_access_size = 1, |
1b067564 | 3135 | .valid.max_access_size = 4, |
6ee021d4 GH |
3136 | .impl.min_access_size = 4, |
3137 | .impl.max_access_size = 4, | |
1b067564 GH |
3138 | .endianness = DEVICE_LITTLE_ENDIAN, |
3139 | }; | |
62c6ae04 | 3140 | |
1b067564 GH |
3141 | static const MemoryRegionOps xhci_oper_ops = { |
3142 | .read = xhci_oper_read, | |
3143 | .write = xhci_oper_write, | |
3144 | .valid.min_access_size = 4, | |
3145 | .valid.max_access_size = 4, | |
3146 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3147 | }; | |
62c6ae04 | 3148 | |
1d8a4e69 GH |
3149 | static const MemoryRegionOps xhci_port_ops = { |
3150 | .read = xhci_port_read, | |
3151 | .write = xhci_port_write, | |
3152 | .valid.min_access_size = 4, | |
3153 | .valid.max_access_size = 4, | |
3154 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3155 | }; | |
3156 | ||
1b067564 GH |
3157 | static const MemoryRegionOps xhci_runtime_ops = { |
3158 | .read = xhci_runtime_read, | |
3159 | .write = xhci_runtime_write, | |
3160 | .valid.min_access_size = 4, | |
3161 | .valid.max_access_size = 4, | |
3162 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3163 | }; | |
62c6ae04 | 3164 | |
1b067564 GH |
3165 | static const MemoryRegionOps xhci_doorbell_ops = { |
3166 | .read = xhci_doorbell_read, | |
3167 | .write = xhci_doorbell_write, | |
62c6ae04 HM |
3168 | .valid.min_access_size = 4, |
3169 | .valid.max_access_size = 4, | |
3170 | .endianness = DEVICE_LITTLE_ENDIAN, | |
3171 | }; | |
3172 | ||
3173 | static void xhci_attach(USBPort *usbport) | |
3174 | { | |
3175 | XHCIState *xhci = usbport->opaque; | |
0846e635 | 3176 | XHCIPort *port = xhci_lookup_port(xhci, usbport); |
62c6ae04 | 3177 | |
f3214027 | 3178 | xhci_port_update(port, 0); |
62c6ae04 HM |
3179 | } |
3180 | ||
3181 | static void xhci_detach(USBPort *usbport) | |
3182 | { | |
3183 | XHCIState *xhci = usbport->opaque; | |
0846e635 | 3184 | XHCIPort *port = xhci_lookup_port(xhci, usbport); |
62c6ae04 | 3185 | |
f3dcf638 | 3186 | xhci_detach_slot(xhci, usbport); |
f3214027 | 3187 | xhci_port_update(port, 1); |
62c6ae04 HM |
3188 | } |
3189 | ||
8c735e43 GH |
3190 | static void xhci_wakeup(USBPort *usbport) |
3191 | { | |
3192 | XHCIState *xhci = usbport->opaque; | |
0846e635 | 3193 | XHCIPort *port = xhci_lookup_port(xhci, usbport); |
8c735e43 | 3194 | |
85e05d82 | 3195 | if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { |
8c735e43 GH |
3196 | return; |
3197 | } | |
85e05d82 | 3198 | set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); |
f705a362 | 3199 | xhci_port_notify(port, PORTSC_PLC); |
8c735e43 GH |
3200 | } |
3201 | ||
62c6ae04 HM |
3202 | static void xhci_complete(USBPort *port, USBPacket *packet) |
3203 | { | |
3204 | XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); | |
3205 | ||
9a77a0f5 | 3206 | if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { |
0cae7b1a HG |
3207 | xhci_ep_nuke_one_xfer(xfer); |
3208 | return; | |
3209 | } | |
9a77a0f5 | 3210 | xhci_complete_packet(xfer); |
024426ac | 3211 | xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid); |
62c6ae04 HM |
3212 | } |
3213 | ||
ccaf87a0 | 3214 | static void xhci_child_detach(USBPort *uport, USBDevice *child) |
62c6ae04 | 3215 | { |
ccaf87a0 GH |
3216 | USBBus *bus = usb_bus_from_device(child); |
3217 | XHCIState *xhci = container_of(bus, XHCIState, bus); | |
ccaf87a0 | 3218 | |
81251841 | 3219 | xhci_detach_slot(xhci, uport); |
62c6ae04 HM |
3220 | } |
3221 | ||
1d8a4e69 | 3222 | static USBPortOps xhci_uport_ops = { |
62c6ae04 HM |
3223 | .attach = xhci_attach, |
3224 | .detach = xhci_detach, | |
8c735e43 | 3225 | .wakeup = xhci_wakeup, |
62c6ae04 HM |
3226 | .complete = xhci_complete, |
3227 | .child_detach = xhci_child_detach, | |
3228 | }; | |
3229 | ||
7c605a23 GH |
3230 | static int xhci_find_epid(USBEndpoint *ep) |
3231 | { | |
3232 | if (ep->nr == 0) { | |
3233 | return 1; | |
3234 | } | |
3235 | if (ep->pid == USB_TOKEN_IN) { | |
3236 | return ep->nr * 2 + 1; | |
3237 | } else { | |
3238 | return ep->nr * 2; | |
3239 | } | |
3240 | } | |
3241 | ||
8550a02d GH |
3242 | static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, |
3243 | unsigned int stream) | |
7c605a23 GH |
3244 | { |
3245 | XHCIState *xhci = container_of(bus, XHCIState, bus); | |
3246 | int slotid; | |
3247 | ||
3248 | DPRINTF("%s\n", __func__); | |
af203be3 | 3249 | slotid = ep->dev->addr; |
7c605a23 GH |
3250 | if (slotid == 0 || !xhci->slots[slotid-1].enabled) { |
3251 | DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); | |
3252 | return; | |
3253 | } | |
024426ac | 3254 | xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); |
7c605a23 GH |
3255 | } |
3256 | ||
62c6ae04 | 3257 | static USBBusOps xhci_bus_ops = { |
7c605a23 | 3258 | .wakeup_endpoint = xhci_wakeup_endpoint, |
62c6ae04 HM |
3259 | }; |
3260 | ||
3261 | static void usb_xhci_init(XHCIState *xhci, DeviceState *dev) | |
3262 | { | |
0846e635 GH |
3263 | XHCIPort *port; |
3264 | int i, usbports, speedmask; | |
62c6ae04 HM |
3265 | |
3266 | xhci->usbsts = USBSTS_HCH; | |
3267 | ||
0846e635 GH |
3268 | if (xhci->numports_2 > MAXPORTS_2) { |
3269 | xhci->numports_2 = MAXPORTS_2; | |
3270 | } | |
3271 | if (xhci->numports_3 > MAXPORTS_3) { | |
3272 | xhci->numports_3 = MAXPORTS_3; | |
3273 | } | |
3274 | usbports = MAX(xhci->numports_2, xhci->numports_3); | |
3275 | xhci->numports = xhci->numports_2 + xhci->numports_3; | |
3276 | ||
62c6ae04 HM |
3277 | usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev); |
3278 | ||
0846e635 GH |
3279 | for (i = 0; i < usbports; i++) { |
3280 | speedmask = 0; | |
3281 | if (i < xhci->numports_2) { | |
3282 | port = &xhci->ports[i]; | |
3283 | port->portnr = i + 1; | |
3284 | port->uport = &xhci->uports[i]; | |
3285 | port->speedmask = | |
3286 | USB_SPEED_MASK_LOW | | |
3287 | USB_SPEED_MASK_FULL | | |
3288 | USB_SPEED_MASK_HIGH; | |
1d8a4e69 | 3289 | snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); |
0846e635 GH |
3290 | speedmask |= port->speedmask; |
3291 | } | |
3292 | if (i < xhci->numports_3) { | |
3293 | port = &xhci->ports[i + xhci->numports_2]; | |
3294 | port->portnr = i + 1 + xhci->numports_2; | |
3295 | port->uport = &xhci->uports[i]; | |
3296 | port->speedmask = USB_SPEED_MASK_SUPER; | |
1d8a4e69 | 3297 | snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); |
0846e635 GH |
3298 | speedmask |= port->speedmask; |
3299 | } | |
3300 | usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, | |
1d8a4e69 | 3301 | &xhci_uport_ops, speedmask); |
62c6ae04 | 3302 | } |
62c6ae04 HM |
3303 | } |
3304 | ||
3305 | static int usb_xhci_initfn(struct PCIDevice *dev) | |
3306 | { | |
1d8a4e69 | 3307 | int i, ret; |
62c6ae04 HM |
3308 | |
3309 | XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev); | |
3310 | ||
3311 | xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */ | |
3312 | xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ | |
3313 | xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10; | |
3314 | xhci->pci_dev.config[0x60] = 0x30; /* release number */ | |
3315 | ||
3316 | usb_xhci_init(xhci, &dev->qdev); | |
3317 | ||
91062ae0 GH |
3318 | if (xhci->numintrs > MAXINTRS) { |
3319 | xhci->numintrs = MAXINTRS; | |
3320 | } | |
c94a7c69 GH |
3321 | while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ |
3322 | xhci->numintrs++; | |
3323 | } | |
91062ae0 GH |
3324 | if (xhci->numintrs < 1) { |
3325 | xhci->numintrs = 1; | |
3326 | } | |
3327 | if (xhci->numslots > MAXSLOTS) { | |
3328 | xhci->numslots = MAXSLOTS; | |
3329 | } | |
3330 | if (xhci->numslots < 1) { | |
3331 | xhci->numslots = 1; | |
3332 | } | |
3333 | ||
01546fa6 GH |
3334 | xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci); |
3335 | ||
62c6ae04 HM |
3336 | xhci->irq = xhci->pci_dev.irq[0]; |
3337 | ||
1b067564 GH |
3338 | memory_region_init(&xhci->mem, "xhci", LEN_REGS); |
3339 | memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci, | |
3340 | "capabilities", LEN_CAP); | |
3341 | memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci, | |
1d8a4e69 | 3342 | "operational", 0x400); |
1b067564 GH |
3343 | memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci, |
3344 | "runtime", LEN_RUNTIME); | |
3345 | memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci, | |
3346 | "doorbell", LEN_DOORBELL); | |
3347 | ||
3348 | memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); | |
3349 | memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); | |
3350 | memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); | |
3351 | memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); | |
3352 | ||
1d8a4e69 GH |
3353 | for (i = 0; i < xhci->numports; i++) { |
3354 | XHCIPort *port = &xhci->ports[i]; | |
3355 | uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; | |
3356 | port->xhci = xhci; | |
3357 | memory_region_init_io(&port->mem, &xhci_port_ops, port, | |
3358 | port->name, 0x10); | |
3359 | memory_region_add_subregion(&xhci->mem, offset, &port->mem); | |
3360 | } | |
3361 | ||
62c6ae04 HM |
3362 | pci_register_bar(&xhci->pci_dev, 0, |
3363 | PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, | |
3364 | &xhci->mem); | |
3365 | ||
6214e73c | 3366 | ret = pcie_endpoint_cap_init(&xhci->pci_dev, 0xa0); |
62c6ae04 HM |
3367 | assert(ret >= 0); |
3368 | ||
c5e9b02d | 3369 | if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) { |
91062ae0 | 3370 | msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false); |
62c6ae04 | 3371 | } |
4c47f800 | 3372 | if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) { |
91062ae0 | 3373 | msix_init(&xhci->pci_dev, xhci->numintrs, |
4c47f800 GH |
3374 | &xhci->mem, 0, OFF_MSIX_TABLE, |
3375 | &xhci->mem, 0, OFF_MSIX_PBA, | |
3376 | 0x90); | |
3377 | } | |
62c6ae04 HM |
3378 | |
3379 | return 0; | |
3380 | } | |
3381 | ||
62c6ae04 HM |
3382 | static const VMStateDescription vmstate_xhci = { |
3383 | .name = "xhci", | |
3384 | .unmigratable = 1, | |
3385 | }; | |
3386 | ||
39bffca2 | 3387 | static Property xhci_properties[] = { |
91062ae0 GH |
3388 | DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true), |
3389 | DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true), | |
3390 | DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), | |
3391 | DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), | |
3392 | DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), | |
3393 | DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), | |
39bffca2 AL |
3394 | DEFINE_PROP_END_OF_LIST(), |
3395 | }; | |
3396 | ||
40021f08 AL |
3397 | static void xhci_class_init(ObjectClass *klass, void *data) |
3398 | { | |
3399 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
39bffca2 | 3400 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 | 3401 | |
39bffca2 AL |
3402 | dc->vmsd = &vmstate_xhci; |
3403 | dc->props = xhci_properties; | |
64619739 | 3404 | dc->reset = xhci_reset; |
40021f08 AL |
3405 | k->init = usb_xhci_initfn; |
3406 | k->vendor_id = PCI_VENDOR_ID_NEC; | |
3407 | k->device_id = PCI_DEVICE_ID_NEC_UPD720200; | |
3408 | k->class_id = PCI_CLASS_SERIAL_USB; | |
3409 | k->revision = 0x03; | |
3410 | k->is_express = 1; | |
6c2d1c32 | 3411 | k->no_hotplug = 1; |
40021f08 AL |
3412 | } |
3413 | ||
8c43a6f0 | 3414 | static const TypeInfo xhci_info = { |
39bffca2 AL |
3415 | .name = "nec-usb-xhci", |
3416 | .parent = TYPE_PCI_DEVICE, | |
3417 | .instance_size = sizeof(XHCIState), | |
3418 | .class_init = xhci_class_init, | |
62c6ae04 HM |
3419 | }; |
3420 | ||
83f7d43a | 3421 | static void xhci_register_types(void) |
62c6ae04 | 3422 | { |
39bffca2 | 3423 | type_register_static(&xhci_info); |
62c6ae04 | 3424 | } |
83f7d43a AF |
3425 | |
3426 | type_init(xhci_register_types) |