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94527ead GH |
1 | /* |
2 | * QEMU USB EHCI Emulation | |
3 | * | |
4 | * Copyright(c) 2008 Emutex Ltd. (address@hidden) | |
5 | * | |
6 | * EHCI project was started by Mark Burkley, with contributions by | |
7 | * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf, | |
8 | * Jan Kiszka and Vincent Palatin contributed bugfixes. | |
9 | * | |
10 | * | |
11 | * This library is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU Lesser General Public | |
13 | * License as published by the Free Software Foundation; either | |
14 | * version 2 of the License, or(at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
19 | * Lesser General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
23 | * | |
24 | * TODO: | |
25 | * o Downstream port handoff | |
26 | */ | |
27 | ||
28 | #include "hw.h" | |
29 | #include "qemu-timer.h" | |
30 | #include "usb.h" | |
31 | #include "pci.h" | |
32 | #include "monitor.h" | |
439a97cc | 33 | #include "trace.h" |
94527ead GH |
34 | |
35 | #define EHCI_DEBUG 0 | |
94527ead | 36 | |
26d53979 | 37 | #if EHCI_DEBUG |
94527ead GH |
38 | #define DPRINTF printf |
39 | #else | |
40 | #define DPRINTF(...) | |
41 | #endif | |
42 | ||
94527ead GH |
43 | /* internal processing - reset HC to try and recover */ |
44 | #define USB_RET_PROCERR (-99) | |
45 | ||
46 | #define MMIO_SIZE 0x1000 | |
47 | ||
48 | /* Capability Registers Base Address - section 2.2 */ | |
49 | #define CAPREGBASE 0x0000 | |
50 | #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved | |
51 | #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # | |
52 | #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params | |
53 | #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params | |
54 | #define EECP HCCPARAMS + 1 | |
55 | #define HCSPPORTROUTE1 CAPREGBASE + 0x000c | |
56 | #define HCSPPORTROUTE2 CAPREGBASE + 0x0010 | |
57 | ||
58 | #define OPREGBASE 0x0020 // Operational Registers Base Address | |
59 | ||
60 | #define USBCMD OPREGBASE + 0x0000 | |
61 | #define USBCMD_RUNSTOP (1 << 0) // run / Stop | |
62 | #define USBCMD_HCRESET (1 << 1) // HC Reset | |
63 | #define USBCMD_FLS (3 << 2) // Frame List Size | |
64 | #define USBCMD_FLS_SH 2 // Frame List Size Shift | |
65 | #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable | |
66 | #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable | |
67 | #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell | |
68 | #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset | |
69 | #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count | |
70 | #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable | |
71 | #define USBCMD_ITC (0x7f << 16) // Int Threshold Control | |
72 | #define USBCMD_ITC_SH 16 // Int Threshold Control Shift | |
73 | ||
74 | #define USBSTS OPREGBASE + 0x0004 | |
75 | #define USBSTS_RO_MASK 0x0000003f | |
76 | #define USBSTS_INT (1 << 0) // USB Interrupt | |
77 | #define USBSTS_ERRINT (1 << 1) // Error Interrupt | |
78 | #define USBSTS_PCD (1 << 2) // Port Change Detect | |
79 | #define USBSTS_FLR (1 << 3) // Frame List Rollover | |
80 | #define USBSTS_HSE (1 << 4) // Host System Error | |
81 | #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance | |
82 | #define USBSTS_HALT (1 << 12) // HC Halted | |
83 | #define USBSTS_REC (1 << 13) // Reclamation | |
84 | #define USBSTS_PSS (1 << 14) // Periodic Schedule Status | |
85 | #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status | |
86 | ||
87 | /* | |
88 | * Interrupt enable bits correspond to the interrupt active bits in USBSTS | |
89 | * so no need to redefine here. | |
90 | */ | |
91 | #define USBINTR OPREGBASE + 0x0008 | |
92 | #define USBINTR_MASK 0x0000003f | |
93 | ||
94 | #define FRINDEX OPREGBASE + 0x000c | |
95 | #define CTRLDSSEGMENT OPREGBASE + 0x0010 | |
96 | #define PERIODICLISTBASE OPREGBASE + 0x0014 | |
97 | #define ASYNCLISTADDR OPREGBASE + 0x0018 | |
98 | #define ASYNCLISTADDR_MASK 0xffffffe0 | |
99 | ||
100 | #define CONFIGFLAG OPREGBASE + 0x0040 | |
101 | ||
102 | #define PORTSC (OPREGBASE + 0x0044) | |
103 | #define PORTSC_BEGIN PORTSC | |
104 | #define PORTSC_END (PORTSC + 4 * NB_PORTS) | |
105 | /* | |
c44fd61c | 106 | * Bits that are reserved or are read-only are masked out of values |
94527ead GH |
107 | * written to us by software |
108 | */ | |
c44fd61c | 109 | #define PORTSC_RO_MASK 0x007021c4 |
94527ead GH |
110 | #define PORTSC_RWC_MASK 0x0000002a |
111 | #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable | |
112 | #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable | |
113 | #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable | |
114 | #define PORTSC_PTC (15 << 16) // Port Test Control | |
115 | #define PORTSC_PTC_SH 16 // Port Test Control shift | |
116 | #define PORTSC_PIC (3 << 14) // Port Indicator Control | |
117 | #define PORTSC_PIC_SH 14 // Port Indicator Control Shift | |
118 | #define PORTSC_POWNER (1 << 13) // Port Owner | |
119 | #define PORTSC_PPOWER (1 << 12) // Port Power | |
120 | #define PORTSC_LINESTAT (3 << 10) // Port Line Status | |
121 | #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift | |
122 | #define PORTSC_PRESET (1 << 8) // Port Reset | |
123 | #define PORTSC_SUSPEND (1 << 7) // Port Suspend | |
124 | #define PORTSC_FPRES (1 << 6) // Force Port Resume | |
125 | #define PORTSC_OCC (1 << 5) // Over Current Change | |
126 | #define PORTSC_OCA (1 << 4) // Over Current Active | |
127 | #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change | |
128 | #define PORTSC_PED (1 << 2) // Port Enable/Disable | |
129 | #define PORTSC_CSC (1 << 1) // Connect Status Change | |
130 | #define PORTSC_CONNECT (1 << 0) // Current Connect Status | |
131 | ||
132 | #define FRAME_TIMER_FREQ 1000 | |
adddecb1 | 133 | #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) |
94527ead GH |
134 | |
135 | #define NB_MAXINTRATE 8 // Max rate at which controller issues ints | |
136 | #define NB_PORTS 4 // Number of downstream ports | |
137 | #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction | |
138 | #define MAX_ITERATIONS 20 // Max number of QH before we break the loop | |
139 | #define MAX_QH 100 // Max allowable queue heads in a chain | |
140 | ||
141 | /* Internal periodic / asynchronous schedule state machine states | |
142 | */ | |
143 | typedef enum { | |
144 | EST_INACTIVE = 1000, | |
145 | EST_ACTIVE, | |
146 | EST_EXECUTING, | |
147 | EST_SLEEPING, | |
148 | /* The following states are internal to the state machine function | |
149 | */ | |
150 | EST_WAITLISTHEAD, | |
151 | EST_FETCHENTRY, | |
152 | EST_FETCHQH, | |
153 | EST_FETCHITD, | |
154 | EST_ADVANCEQUEUE, | |
155 | EST_FETCHQTD, | |
156 | EST_EXECUTE, | |
157 | EST_WRITEBACK, | |
158 | EST_HORIZONTALQH | |
159 | } EHCI_STATES; | |
160 | ||
161 | /* macros for accessing fields within next link pointer entry */ | |
162 | #define NLPTR_GET(x) ((x) & 0xffffffe0) | |
163 | #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) | |
164 | #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid | |
165 | ||
166 | /* link pointer types */ | |
167 | #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor | |
168 | #define NLPTR_TYPE_QH 1 // queue head | |
169 | #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor | |
170 | #define NLPTR_TYPE_FSTN 3 // frame span traversal node | |
171 | ||
172 | ||
173 | /* EHCI spec version 1.0 Section 3.3 | |
174 | */ | |
175 | typedef struct EHCIitd { | |
176 | uint32_t next; | |
177 | ||
178 | uint32_t transact[8]; | |
179 | #define ITD_XACT_ACTIVE (1 << 31) | |
180 | #define ITD_XACT_DBERROR (1 << 30) | |
181 | #define ITD_XACT_BABBLE (1 << 29) | |
182 | #define ITD_XACT_XACTERR (1 << 28) | |
183 | #define ITD_XACT_LENGTH_MASK 0x0fff0000 | |
184 | #define ITD_XACT_LENGTH_SH 16 | |
185 | #define ITD_XACT_IOC (1 << 15) | |
186 | #define ITD_XACT_PGSEL_MASK 0x00007000 | |
187 | #define ITD_XACT_PGSEL_SH 12 | |
188 | #define ITD_XACT_OFFSET_MASK 0x00000fff | |
189 | ||
190 | uint32_t bufptr[7]; | |
191 | #define ITD_BUFPTR_MASK 0xfffff000 | |
192 | #define ITD_BUFPTR_SH 12 | |
193 | #define ITD_BUFPTR_EP_MASK 0x00000f00 | |
194 | #define ITD_BUFPTR_EP_SH 8 | |
195 | #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f | |
196 | #define ITD_BUFPTR_DEVADDR_SH 0 | |
197 | #define ITD_BUFPTR_DIRECTION (1 << 11) | |
198 | #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff | |
199 | #define ITD_BUFPTR_MAXPKT_SH 0 | |
200 | #define ITD_BUFPTR_MULT_MASK 0x00000003 | |
e654887f | 201 | #define ITD_BUFPTR_MULT_SH 0 |
94527ead GH |
202 | } EHCIitd; |
203 | ||
204 | /* EHCI spec version 1.0 Section 3.4 | |
205 | */ | |
206 | typedef struct EHCIsitd { | |
207 | uint32_t next; // Standard next link pointer | |
208 | uint32_t epchar; | |
209 | #define SITD_EPCHAR_IO (1 << 31) | |
210 | #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 | |
211 | #define SITD_EPCHAR_PORTNUM_SH 24 | |
212 | #define SITD_EPCHAR_HUBADD_MASK 0x007f0000 | |
213 | #define SITD_EPCHAR_HUBADDR_SH 16 | |
214 | #define SITD_EPCHAR_EPNUM_MASK 0x00000f00 | |
215 | #define SITD_EPCHAR_EPNUM_SH 8 | |
216 | #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f | |
217 | ||
218 | uint32_t uframe; | |
219 | #define SITD_UFRAME_CMASK_MASK 0x0000ff00 | |
220 | #define SITD_UFRAME_CMASK_SH 8 | |
221 | #define SITD_UFRAME_SMASK_MASK 0x000000ff | |
222 | ||
223 | uint32_t results; | |
224 | #define SITD_RESULTS_IOC (1 << 31) | |
225 | #define SITD_RESULTS_PGSEL (1 << 30) | |
226 | #define SITD_RESULTS_TBYTES_MASK 0x03ff0000 | |
227 | #define SITD_RESULTS_TYBYTES_SH 16 | |
228 | #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 | |
229 | #define SITD_RESULTS_CPROGMASK_SH 8 | |
230 | #define SITD_RESULTS_ACTIVE (1 << 7) | |
231 | #define SITD_RESULTS_ERR (1 << 6) | |
232 | #define SITD_RESULTS_DBERR (1 << 5) | |
233 | #define SITD_RESULTS_BABBLE (1 << 4) | |
234 | #define SITD_RESULTS_XACTERR (1 << 3) | |
235 | #define SITD_RESULTS_MISSEDUF (1 << 2) | |
236 | #define SITD_RESULTS_SPLITXSTATE (1 << 1) | |
237 | ||
238 | uint32_t bufptr[2]; | |
239 | #define SITD_BUFPTR_MASK 0xfffff000 | |
240 | #define SITD_BUFPTR_CURROFF_MASK 0x00000fff | |
241 | #define SITD_BUFPTR_TPOS_MASK 0x00000018 | |
242 | #define SITD_BUFPTR_TPOS_SH 3 | |
243 | #define SITD_BUFPTR_TCNT_MASK 0x00000007 | |
244 | ||
245 | uint32_t backptr; // Standard next link pointer | |
246 | } EHCIsitd; | |
247 | ||
248 | /* EHCI spec version 1.0 Section 3.5 | |
249 | */ | |
250 | typedef struct EHCIqtd { | |
251 | uint32_t next; // Standard next link pointer | |
252 | uint32_t altnext; // Standard next link pointer | |
253 | uint32_t token; | |
254 | #define QTD_TOKEN_DTOGGLE (1 << 31) | |
255 | #define QTD_TOKEN_TBYTES_MASK 0x7fff0000 | |
256 | #define QTD_TOKEN_TBYTES_SH 16 | |
257 | #define QTD_TOKEN_IOC (1 << 15) | |
258 | #define QTD_TOKEN_CPAGE_MASK 0x00007000 | |
259 | #define QTD_TOKEN_CPAGE_SH 12 | |
260 | #define QTD_TOKEN_CERR_MASK 0x00000c00 | |
261 | #define QTD_TOKEN_CERR_SH 10 | |
262 | #define QTD_TOKEN_PID_MASK 0x00000300 | |
263 | #define QTD_TOKEN_PID_SH 8 | |
264 | #define QTD_TOKEN_ACTIVE (1 << 7) | |
265 | #define QTD_TOKEN_HALT (1 << 6) | |
266 | #define QTD_TOKEN_DBERR (1 << 5) | |
267 | #define QTD_TOKEN_BABBLE (1 << 4) | |
268 | #define QTD_TOKEN_XACTERR (1 << 3) | |
269 | #define QTD_TOKEN_MISSEDUF (1 << 2) | |
270 | #define QTD_TOKEN_SPLITXSTATE (1 << 1) | |
271 | #define QTD_TOKEN_PING (1 << 0) | |
272 | ||
273 | uint32_t bufptr[5]; // Standard buffer pointer | |
274 | #define QTD_BUFPTR_MASK 0xfffff000 | |
275 | } EHCIqtd; | |
276 | ||
277 | /* EHCI spec version 1.0 Section 3.6 | |
278 | */ | |
279 | typedef struct EHCIqh { | |
280 | uint32_t next; // Standard next link pointer | |
281 | ||
282 | /* endpoint characteristics */ | |
283 | uint32_t epchar; | |
284 | #define QH_EPCHAR_RL_MASK 0xf0000000 | |
285 | #define QH_EPCHAR_RL_SH 28 | |
286 | #define QH_EPCHAR_C (1 << 27) | |
287 | #define QH_EPCHAR_MPLEN_MASK 0x07FF0000 | |
288 | #define QH_EPCHAR_MPLEN_SH 16 | |
289 | #define QH_EPCHAR_H (1 << 15) | |
290 | #define QH_EPCHAR_DTC (1 << 14) | |
291 | #define QH_EPCHAR_EPS_MASK 0x00003000 | |
292 | #define QH_EPCHAR_EPS_SH 12 | |
293 | #define EHCI_QH_EPS_FULL 0 | |
294 | #define EHCI_QH_EPS_LOW 1 | |
295 | #define EHCI_QH_EPS_HIGH 2 | |
296 | #define EHCI_QH_EPS_RESERVED 3 | |
297 | ||
298 | #define QH_EPCHAR_EP_MASK 0x00000f00 | |
299 | #define QH_EPCHAR_EP_SH 8 | |
300 | #define QH_EPCHAR_I (1 << 7) | |
301 | #define QH_EPCHAR_DEVADDR_MASK 0x0000007f | |
302 | #define QH_EPCHAR_DEVADDR_SH 0 | |
303 | ||
304 | /* endpoint capabilities */ | |
305 | uint32_t epcap; | |
306 | #define QH_EPCAP_MULT_MASK 0xc0000000 | |
307 | #define QH_EPCAP_MULT_SH 30 | |
308 | #define QH_EPCAP_PORTNUM_MASK 0x3f800000 | |
309 | #define QH_EPCAP_PORTNUM_SH 23 | |
310 | #define QH_EPCAP_HUBADDR_MASK 0x007f0000 | |
311 | #define QH_EPCAP_HUBADDR_SH 16 | |
312 | #define QH_EPCAP_CMASK_MASK 0x0000ff00 | |
313 | #define QH_EPCAP_CMASK_SH 8 | |
314 | #define QH_EPCAP_SMASK_MASK 0x000000ff | |
315 | #define QH_EPCAP_SMASK_SH 0 | |
316 | ||
317 | uint32_t current_qtd; // Standard next link pointer | |
318 | uint32_t next_qtd; // Standard next link pointer | |
319 | uint32_t altnext_qtd; | |
320 | #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e | |
321 | #define QH_ALTNEXT_NAKCNT_SH 1 | |
322 | ||
323 | uint32_t token; // Same as QTD token | |
324 | uint32_t bufptr[5]; // Standard buffer pointer | |
325 | #define BUFPTR_CPROGMASK_MASK 0x000000ff | |
326 | #define BUFPTR_FRAMETAG_MASK 0x0000001f | |
327 | #define BUFPTR_SBYTES_MASK 0x00000fe0 | |
328 | #define BUFPTR_SBYTES_SH 5 | |
329 | } EHCIqh; | |
330 | ||
331 | /* EHCI spec version 1.0 Section 3.7 | |
332 | */ | |
333 | typedef struct EHCIfstn { | |
334 | uint32_t next; // Standard next link pointer | |
335 | uint32_t backptr; // Standard next link pointer | |
336 | } EHCIfstn; | |
337 | ||
0122f472 GH |
338 | typedef struct EHCIQueue EHCIQueue; |
339 | typedef struct EHCIState EHCIState; | |
340 | ||
341 | enum async_state { | |
342 | EHCI_ASYNC_NONE = 0, | |
343 | EHCI_ASYNC_INFLIGHT, | |
344 | EHCI_ASYNC_FINISHED, | |
345 | }; | |
346 | ||
347 | struct EHCIQueue { | |
348 | EHCIState *ehci; | |
8ac6d699 GH |
349 | QTAILQ_ENTRY(EHCIQueue) next; |
350 | bool async_schedule; | |
adddecb1 GH |
351 | uint32_t seen; |
352 | uint64_t ts; | |
0122f472 GH |
353 | |
354 | /* cached data from guest - needs to be flushed | |
355 | * when guest removes an entry (doorbell, handshake sequence) | |
356 | */ | |
357 | EHCIqh qh; // copy of current QH (being worked on) | |
358 | uint32_t qhaddr; // address QH read from | |
359 | EHCIqtd qtd; // copy of current QTD (being worked on) | |
360 | uint32_t qtdaddr; // address QTD read from | |
361 | ||
362 | USBPacket packet; | |
363 | uint8_t buffer[BUFF_SIZE]; | |
364 | int pid; | |
365 | uint32_t tbytes; | |
366 | enum async_state async; | |
367 | int usb_status; | |
368 | }; | |
369 | ||
370 | struct EHCIState { | |
94527ead | 371 | PCIDevice dev; |
0122f472 | 372 | USBBus bus; |
94527ead GH |
373 | qemu_irq irq; |
374 | target_phys_addr_t mem_base; | |
375 | int mem; | |
16a2dee6 GH |
376 | |
377 | /* properties */ | |
378 | uint32_t freq; | |
379 | uint32_t maxframes; | |
380 | ||
94527ead GH |
381 | /* |
382 | * EHCI spec version 1.0 Section 2.3 | |
383 | * Host Controller Operational Registers | |
384 | */ | |
385 | union { | |
386 | uint8_t mmio[MMIO_SIZE]; | |
387 | struct { | |
388 | uint8_t cap[OPREGBASE]; | |
389 | uint32_t usbcmd; | |
390 | uint32_t usbsts; | |
391 | uint32_t usbintr; | |
392 | uint32_t frindex; | |
393 | uint32_t ctrldssegment; | |
394 | uint32_t periodiclistbase; | |
395 | uint32_t asynclistaddr; | |
396 | uint32_t notused[9]; | |
397 | uint32_t configflag; | |
398 | uint32_t portsc[NB_PORTS]; | |
399 | }; | |
400 | }; | |
0122f472 | 401 | |
94527ead GH |
402 | /* |
403 | * Internal states, shadow registers, etc | |
404 | */ | |
405 | uint32_t sofv; | |
406 | QEMUTimer *frame_timer; | |
407 | int attach_poll_counter; | |
408 | int astate; // Current state in asynchronous schedule | |
409 | int pstate; // Current state in periodic schedule | |
410 | USBPort ports[NB_PORTS]; | |
94527ead | 411 | uint32_t usbsts_pending; |
8ac6d699 | 412 | QTAILQ_HEAD(, EHCIQueue) queues; |
94527ead | 413 | |
0122f472 GH |
414 | uint32_t a_fetch_addr; // which address to look at next |
415 | uint32_t p_fetch_addr; // which address to look at next | |
94527ead | 416 | |
0122f472 GH |
417 | USBPacket ipacket; |
418 | uint8_t ibuffer[BUFF_SIZE]; | |
94527ead | 419 | int isoch_pause; |
0122f472 | 420 | |
adddecb1 | 421 | uint64_t last_run_ns; |
0122f472 | 422 | }; |
94527ead GH |
423 | |
424 | #define SET_LAST_RUN_CLOCK(s) \ | |
adddecb1 | 425 | (s)->last_run_ns = qemu_get_clock_ns(vm_clock); |
94527ead GH |
426 | |
427 | /* nifty macros from Arnon's EHCI version */ | |
428 | #define get_field(data, field) \ | |
429 | (((data) & field##_MASK) >> field##_SH) | |
430 | ||
431 | #define set_field(data, newval, field) do { \ | |
432 | uint32_t val = *data; \ | |
433 | val &= ~ field##_MASK; \ | |
434 | val |= ((newval) << field##_SH) & field##_MASK; \ | |
435 | *data = val; \ | |
436 | } while(0) | |
437 | ||
26d53979 GH |
438 | static const char *ehci_state_names[] = { |
439 | [ EST_INACTIVE ] = "INACTIVE", | |
440 | [ EST_ACTIVE ] = "ACTIVE", | |
441 | [ EST_EXECUTING ] = "EXECUTING", | |
442 | [ EST_SLEEPING ] = "SLEEPING", | |
443 | [ EST_WAITLISTHEAD ] = "WAITLISTHEAD", | |
444 | [ EST_FETCHENTRY ] = "FETCH ENTRY", | |
445 | [ EST_FETCHQH ] = "FETCH QH", | |
446 | [ EST_FETCHITD ] = "FETCH ITD", | |
447 | [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE", | |
448 | [ EST_FETCHQTD ] = "FETCH QTD", | |
449 | [ EST_EXECUTE ] = "EXECUTE", | |
450 | [ EST_WRITEBACK ] = "WRITEBACK", | |
451 | [ EST_HORIZONTALQH ] = "HORIZONTALQH", | |
452 | }; | |
453 | ||
454 | static const char *ehci_mmio_names[] = { | |
455 | [ CAPLENGTH ] = "CAPLENGTH", | |
456 | [ HCIVERSION ] = "HCIVERSION", | |
457 | [ HCSPARAMS ] = "HCSPARAMS", | |
458 | [ HCCPARAMS ] = "HCCPARAMS", | |
459 | [ USBCMD ] = "USBCMD", | |
460 | [ USBSTS ] = "USBSTS", | |
461 | [ USBINTR ] = "USBINTR", | |
462 | [ FRINDEX ] = "FRINDEX", | |
463 | [ PERIODICLISTBASE ] = "P-LIST BASE", | |
464 | [ ASYNCLISTADDR ] = "A-LIST ADDR", | |
465 | [ PORTSC_BEGIN ] = "PORTSC #0", | |
466 | [ PORTSC_BEGIN + 4] = "PORTSC #1", | |
467 | [ PORTSC_BEGIN + 8] = "PORTSC #2", | |
468 | [ PORTSC_BEGIN + 12] = "PORTSC #3", | |
469 | [ CONFIGFLAG ] = "CONFIGFLAG", | |
470 | }; | |
94527ead | 471 | |
26d53979 | 472 | static const char *nr2str(const char **n, size_t len, uint32_t nr) |
94527ead | 473 | { |
26d53979 GH |
474 | if (nr < len && n[nr] != NULL) { |
475 | return n[nr]; | |
94527ead | 476 | } else { |
26d53979 | 477 | return "unknown"; |
94527ead GH |
478 | } |
479 | } | |
94527ead | 480 | |
26d53979 GH |
481 | static const char *state2str(uint32_t state) |
482 | { | |
483 | return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state); | |
484 | } | |
485 | ||
486 | static const char *addr2str(target_phys_addr_t addr) | |
487 | { | |
488 | return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); | |
489 | } | |
490 | ||
439a97cc GH |
491 | static void ehci_trace_usbsts(uint32_t mask, int state) |
492 | { | |
493 | /* interrupts */ | |
494 | if (mask & USBSTS_INT) { | |
495 | trace_usb_ehci_usbsts("INT", state); | |
496 | } | |
497 | if (mask & USBSTS_ERRINT) { | |
498 | trace_usb_ehci_usbsts("ERRINT", state); | |
499 | } | |
500 | if (mask & USBSTS_PCD) { | |
501 | trace_usb_ehci_usbsts("PCD", state); | |
502 | } | |
503 | if (mask & USBSTS_FLR) { | |
504 | trace_usb_ehci_usbsts("FLR", state); | |
505 | } | |
506 | if (mask & USBSTS_HSE) { | |
507 | trace_usb_ehci_usbsts("HSE", state); | |
508 | } | |
509 | if (mask & USBSTS_IAA) { | |
510 | trace_usb_ehci_usbsts("IAA", state); | |
511 | } | |
512 | ||
513 | /* status */ | |
514 | if (mask & USBSTS_HALT) { | |
515 | trace_usb_ehci_usbsts("HALT", state); | |
516 | } | |
517 | if (mask & USBSTS_REC) { | |
518 | trace_usb_ehci_usbsts("REC", state); | |
519 | } | |
520 | if (mask & USBSTS_PSS) { | |
521 | trace_usb_ehci_usbsts("PSS", state); | |
522 | } | |
523 | if (mask & USBSTS_ASS) { | |
524 | trace_usb_ehci_usbsts("ASS", state); | |
525 | } | |
526 | } | |
527 | ||
528 | static inline void ehci_set_usbsts(EHCIState *s, int mask) | |
529 | { | |
530 | if ((s->usbsts & mask) == mask) { | |
531 | return; | |
532 | } | |
533 | ehci_trace_usbsts(mask, 1); | |
534 | s->usbsts |= mask; | |
535 | } | |
536 | ||
537 | static inline void ehci_clear_usbsts(EHCIState *s, int mask) | |
538 | { | |
539 | if ((s->usbsts & mask) == 0) { | |
540 | return; | |
541 | } | |
542 | ehci_trace_usbsts(mask, 0); | |
543 | s->usbsts &= ~mask; | |
544 | } | |
94527ead GH |
545 | |
546 | static inline void ehci_set_interrupt(EHCIState *s, int intr) | |
547 | { | |
548 | int level = 0; | |
549 | ||
550 | // TODO honour interrupt threshold requests | |
551 | ||
439a97cc | 552 | ehci_set_usbsts(s, intr); |
94527ead GH |
553 | |
554 | if ((s->usbsts & USBINTR_MASK) & s->usbintr) { | |
555 | level = 1; | |
556 | } | |
557 | ||
558 | qemu_set_irq(s->irq, level); | |
559 | } | |
560 | ||
561 | static inline void ehci_record_interrupt(EHCIState *s, int intr) | |
562 | { | |
563 | s->usbsts_pending |= intr; | |
564 | } | |
565 | ||
566 | static inline void ehci_commit_interrupt(EHCIState *s) | |
567 | { | |
568 | if (!s->usbsts_pending) { | |
569 | return; | |
570 | } | |
571 | ehci_set_interrupt(s, s->usbsts_pending); | |
572 | s->usbsts_pending = 0; | |
573 | } | |
574 | ||
26d53979 GH |
575 | static void ehci_set_state(EHCIState *s, int async, int state) |
576 | { | |
577 | if (async) { | |
578 | trace_usb_ehci_state("async", state2str(state)); | |
579 | s->astate = state; | |
580 | } else { | |
581 | trace_usb_ehci_state("periodic", state2str(state)); | |
582 | s->pstate = state; | |
583 | } | |
584 | } | |
585 | ||
586 | static int ehci_get_state(EHCIState *s, int async) | |
587 | { | |
588 | return async ? s->astate : s->pstate; | |
589 | } | |
590 | ||
0122f472 GH |
591 | static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr) |
592 | { | |
593 | if (async) { | |
594 | s->a_fetch_addr = addr; | |
595 | } else { | |
596 | s->p_fetch_addr = addr; | |
597 | } | |
598 | } | |
599 | ||
600 | static int ehci_get_fetch_addr(EHCIState *s, int async) | |
601 | { | |
602 | return async ? s->a_fetch_addr : s->p_fetch_addr; | |
603 | } | |
604 | ||
8ac6d699 | 605 | static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh) |
26d53979 | 606 | { |
025b168c GH |
607 | /* need three here due to argument count limits */ |
608 | trace_usb_ehci_qh_ptrs(q, addr, qh->next, | |
609 | qh->current_qtd, qh->next_qtd, qh->altnext_qtd); | |
610 | trace_usb_ehci_qh_fields(addr, | |
611 | get_field(qh->epchar, QH_EPCHAR_RL), | |
612 | get_field(qh->epchar, QH_EPCHAR_MPLEN), | |
613 | get_field(qh->epchar, QH_EPCHAR_EPS), | |
614 | get_field(qh->epchar, QH_EPCHAR_EP), | |
615 | get_field(qh->epchar, QH_EPCHAR_DEVADDR)); | |
616 | trace_usb_ehci_qh_bits(addr, | |
617 | (bool)(qh->epchar & QH_EPCHAR_C), | |
618 | (bool)(qh->epchar & QH_EPCHAR_H), | |
619 | (bool)(qh->epchar & QH_EPCHAR_DTC), | |
620 | (bool)(qh->epchar & QH_EPCHAR_I)); | |
26d53979 GH |
621 | } |
622 | ||
8ac6d699 | 623 | static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd) |
26d53979 | 624 | { |
025b168c GH |
625 | /* need three here due to argument count limits */ |
626 | trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext); | |
627 | trace_usb_ehci_qtd_fields(addr, | |
628 | get_field(qtd->token, QTD_TOKEN_TBYTES), | |
629 | get_field(qtd->token, QTD_TOKEN_CPAGE), | |
630 | get_field(qtd->token, QTD_TOKEN_CERR), | |
631 | get_field(qtd->token, QTD_TOKEN_PID)); | |
632 | trace_usb_ehci_qtd_bits(addr, | |
633 | (bool)(qtd->token & QTD_TOKEN_IOC), | |
634 | (bool)(qtd->token & QTD_TOKEN_ACTIVE), | |
635 | (bool)(qtd->token & QTD_TOKEN_HALT), | |
636 | (bool)(qtd->token & QTD_TOKEN_BABBLE), | |
637 | (bool)(qtd->token & QTD_TOKEN_XACTERR)); | |
26d53979 GH |
638 | } |
639 | ||
640 | static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd) | |
641 | { | |
e654887f GH |
642 | trace_usb_ehci_itd(addr, itd->next, |
643 | get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT), | |
644 | get_field(itd->bufptr[2], ITD_BUFPTR_MULT), | |
645 | get_field(itd->bufptr[0], ITD_BUFPTR_EP), | |
646 | get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR)); | |
26d53979 GH |
647 | } |
648 | ||
8ac6d699 GH |
649 | /* queue management */ |
650 | ||
651 | static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async) | |
652 | { | |
653 | EHCIQueue *q; | |
654 | ||
655 | q = qemu_mallocz(sizeof(*q)); | |
656 | q->ehci = ehci; | |
657 | q->async_schedule = async; | |
658 | QTAILQ_INSERT_HEAD(&ehci->queues, q, next); | |
659 | trace_usb_ehci_queue_action(q, "alloc"); | |
660 | return q; | |
661 | } | |
662 | ||
663 | static void ehci_free_queue(EHCIQueue *q) | |
664 | { | |
665 | trace_usb_ehci_queue_action(q, "free"); | |
666 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
667 | usb_cancel_packet(&q->packet); | |
668 | } | |
669 | QTAILQ_REMOVE(&q->ehci->queues, q, next); | |
670 | qemu_free(q); | |
671 | } | |
672 | ||
673 | static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr) | |
674 | { | |
675 | EHCIQueue *q; | |
676 | ||
677 | QTAILQ_FOREACH(q, &ehci->queues, next) { | |
678 | if (addr == q->qhaddr) { | |
679 | return q; | |
680 | } | |
681 | } | |
682 | return NULL; | |
683 | } | |
684 | ||
685 | static void ehci_queues_rip_unused(EHCIState *ehci) | |
686 | { | |
687 | EHCIQueue *q, *tmp; | |
688 | ||
689 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
690 | if (q->seen) { | |
691 | q->seen = 0; | |
adddecb1 | 692 | q->ts = ehci->last_run_ns; |
8ac6d699 GH |
693 | continue; |
694 | } | |
adddecb1 | 695 | if (ehci->last_run_ns < q->ts + 250000000) { |
8ac6d699 GH |
696 | /* allow 0.25 sec idle */ |
697 | continue; | |
698 | } | |
699 | ehci_free_queue(q); | |
700 | } | |
701 | } | |
702 | ||
07771f6f GH |
703 | static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev) |
704 | { | |
705 | EHCIQueue *q, *tmp; | |
706 | ||
707 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
708 | if (q->packet.owner != dev) { | |
709 | continue; | |
710 | } | |
711 | ehci_free_queue(q); | |
712 | } | |
713 | } | |
714 | ||
8ac6d699 GH |
715 | static void ehci_queues_rip_all(EHCIState *ehci) |
716 | { | |
717 | EHCIQueue *q, *tmp; | |
718 | ||
719 | QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) { | |
720 | ehci_free_queue(q); | |
721 | } | |
722 | } | |
723 | ||
94527ead GH |
724 | /* Attach or detach a device on root hub */ |
725 | ||
726 | static void ehci_attach(USBPort *port) | |
727 | { | |
728 | EHCIState *s = port->opaque; | |
729 | uint32_t *portsc = &s->portsc[port->index]; | |
730 | ||
dcbd0b5c | 731 | trace_usb_ehci_port_attach(port->index, port->dev->product_desc); |
94527ead GH |
732 | |
733 | *portsc |= PORTSC_CONNECT; | |
734 | *portsc |= PORTSC_CSC; | |
735 | ||
736 | /* | |
737 | * If a high speed device is attached then we own this port(indicated | |
738 | * by zero in the PORTSC_POWNER bit field) so set the status bit | |
739 | * and set an interrupt if enabled. | |
740 | */ | |
741 | if ( !(*portsc & PORTSC_POWNER)) { | |
742 | ehci_set_interrupt(s, USBSTS_PCD); | |
743 | } | |
744 | } | |
745 | ||
746 | static void ehci_detach(USBPort *port) | |
747 | { | |
748 | EHCIState *s = port->opaque; | |
749 | uint32_t *portsc = &s->portsc[port->index]; | |
750 | ||
dcbd0b5c | 751 | trace_usb_ehci_port_detach(port->index); |
94527ead | 752 | |
4706ab6c HG |
753 | ehci_queues_rip_device(s, port->dev); |
754 | ||
94527ead GH |
755 | *portsc &= ~PORTSC_CONNECT; |
756 | *portsc |= PORTSC_CSC; | |
757 | ||
758 | /* | |
759 | * If a high speed device is attached then we own this port(indicated | |
760 | * by zero in the PORTSC_POWNER bit field) so set the status bit | |
761 | * and set an interrupt if enabled. | |
762 | */ | |
763 | if ( !(*portsc & PORTSC_POWNER)) { | |
764 | ehci_set_interrupt(s, USBSTS_PCD); | |
765 | } | |
766 | } | |
767 | ||
4706ab6c HG |
768 | static void ehci_child_detach(USBPort *port, USBDevice *child) |
769 | { | |
770 | EHCIState *s = port->opaque; | |
771 | ||
772 | ehci_queues_rip_device(s, child); | |
773 | } | |
774 | ||
94527ead GH |
775 | /* 4.1 host controller initialization */ |
776 | static void ehci_reset(void *opaque) | |
777 | { | |
778 | EHCIState *s = opaque; | |
94527ead GH |
779 | int i; |
780 | ||
439a97cc | 781 | trace_usb_ehci_reset(); |
94527ead GH |
782 | |
783 | memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE); | |
784 | ||
785 | s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH; | |
786 | s->usbsts = USBSTS_HALT; | |
787 | ||
788 | s->astate = EST_INACTIVE; | |
789 | s->pstate = EST_INACTIVE; | |
94527ead GH |
790 | s->isoch_pause = -1; |
791 | s->attach_poll_counter = 0; | |
792 | ||
793 | for(i = 0; i < NB_PORTS; i++) { | |
794 | s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER; | |
795 | ||
796 | if (s->ports[i].dev) { | |
797 | usb_attach(&s->ports[i], s->ports[i].dev); | |
798 | } | |
799 | } | |
8ac6d699 | 800 | ehci_queues_rip_all(s); |
94527ead GH |
801 | } |
802 | ||
803 | static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr) | |
804 | { | |
805 | EHCIState *s = ptr; | |
806 | uint32_t val; | |
807 | ||
808 | val = s->mmio[addr]; | |
809 | ||
810 | return val; | |
811 | } | |
812 | ||
813 | static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr) | |
814 | { | |
815 | EHCIState *s = ptr; | |
816 | uint32_t val; | |
817 | ||
818 | val = s->mmio[addr] | (s->mmio[addr+1] << 8); | |
819 | ||
820 | return val; | |
821 | } | |
822 | ||
823 | static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr) | |
824 | { | |
825 | EHCIState *s = ptr; | |
826 | uint32_t val; | |
827 | ||
828 | val = s->mmio[addr] | (s->mmio[addr+1] << 8) | | |
829 | (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24); | |
830 | ||
439a97cc | 831 | trace_usb_ehci_mmio_readl(addr, addr2str(addr), val); |
94527ead GH |
832 | return val; |
833 | } | |
834 | ||
835 | static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val) | |
836 | { | |
837 | fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n"); | |
838 | exit(1); | |
839 | } | |
840 | ||
841 | static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val) | |
842 | { | |
843 | fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n"); | |
844 | exit(1); | |
845 | } | |
846 | ||
847 | static void handle_port_status_write(EHCIState *s, int port, uint32_t val) | |
848 | { | |
849 | uint32_t *portsc = &s->portsc[port]; | |
850 | int rwc; | |
851 | USBDevice *dev = s->ports[port].dev; | |
852 | ||
94527ead GH |
853 | rwc = val & PORTSC_RWC_MASK; |
854 | val &= PORTSC_RO_MASK; | |
855 | ||
856 | // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC); | |
857 | ||
858 | *portsc &= ~rwc; | |
859 | ||
860 | if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 861 | trace_usb_ehci_port_reset(port, 1); |
94527ead GH |
862 | } |
863 | ||
864 | if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { | |
dcbd0b5c | 865 | trace_usb_ehci_port_reset(port, 0); |
94527ead | 866 | if (dev) { |
fbf9db64 | 867 | usb_attach(&s->ports[port], dev); |
94527ead | 868 | usb_send_msg(dev, USB_MSG_RESET); |
94527ead GH |
869 | *portsc &= ~PORTSC_CSC; |
870 | } | |
871 | ||
872 | /* Table 2.16 Set the enable bit(and enable bit change) to indicate | |
873 | * to SW that this port has a high speed device attached | |
874 | * | |
875 | * TODO - when to disable? | |
876 | */ | |
877 | val |= PORTSC_PED; | |
878 | val |= PORTSC_PEDC; | |
879 | } | |
880 | ||
881 | *portsc &= ~PORTSC_RO_MASK; | |
882 | *portsc |= val; | |
94527ead GH |
883 | } |
884 | ||
885 | static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) | |
886 | { | |
887 | EHCIState *s = ptr; | |
c4f8e211 GH |
888 | uint32_t *mmio = (uint32_t *)(&s->mmio[addr]); |
889 | uint32_t old = *mmio; | |
94527ead | 890 | int i; |
439a97cc | 891 | |
c4f8e211 | 892 | trace_usb_ehci_mmio_writel(addr, addr2str(addr), val); |
94527ead GH |
893 | |
894 | /* Only aligned reads are allowed on OHCI */ | |
895 | if (addr & 3) { | |
896 | fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x" | |
897 | TARGET_FMT_plx "\n", addr); | |
898 | return; | |
899 | } | |
900 | ||
901 | if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) { | |
902 | handle_port_status_write(s, (addr-PORTSC)/4, val); | |
c4f8e211 | 903 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); |
94527ead GH |
904 | return; |
905 | } | |
906 | ||
907 | if (addr < OPREGBASE) { | |
908 | fprintf(stderr, "usb-ehci: write attempt to read-only register" | |
909 | TARGET_FMT_plx "\n", addr); | |
910 | return; | |
911 | } | |
912 | ||
913 | ||
914 | /* Do any register specific pre-write processing here. */ | |
94527ead GH |
915 | switch(addr) { |
916 | case USBCMD: | |
94527ead | 917 | if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) { |
94527ead GH |
918 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
919 | SET_LAST_RUN_CLOCK(s); | |
439a97cc | 920 | ehci_clear_usbsts(s, USBSTS_HALT); |
94527ead GH |
921 | } |
922 | ||
923 | if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
94527ead GH |
924 | qemu_del_timer(s->frame_timer); |
925 | // TODO - should finish out some stuff before setting halt | |
439a97cc | 926 | ehci_set_usbsts(s, USBSTS_HALT); |
94527ead GH |
927 | } |
928 | ||
929 | if (val & USBCMD_HCRESET) { | |
94527ead GH |
930 | ehci_reset(s); |
931 | val &= ~USBCMD_HCRESET; | |
932 | } | |
933 | ||
934 | /* not supporting dynamic frame list size at the moment */ | |
935 | if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) { | |
936 | fprintf(stderr, "attempt to set frame list size -- value %d\n", | |
937 | val & USBCMD_FLS); | |
938 | val &= ~USBCMD_FLS; | |
939 | } | |
94527ead GH |
940 | break; |
941 | ||
94527ead GH |
942 | case USBSTS: |
943 | val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO | |
439a97cc GH |
944 | ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC |
945 | val = s->usbsts; | |
94527ead GH |
946 | ehci_set_interrupt(s, 0); |
947 | break; | |
948 | ||
94527ead GH |
949 | case USBINTR: |
950 | val &= USBINTR_MASK; | |
94527ead GH |
951 | break; |
952 | ||
953 | case FRINDEX: | |
954 | s->sofv = val >> 3; | |
94527ead GH |
955 | break; |
956 | ||
957 | case CONFIGFLAG: | |
94527ead GH |
958 | val &= 0x1; |
959 | if (val) { | |
960 | for(i = 0; i < NB_PORTS; i++) | |
961 | s->portsc[i] &= ~PORTSC_POWNER; | |
962 | } | |
963 | break; | |
964 | ||
965 | case PERIODICLISTBASE: | |
966 | if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
967 | fprintf(stderr, | |
968 | "ehci: PERIODIC list base register set while periodic schedule\n" | |
969 | " is enabled and HC is enabled\n"); | |
970 | } | |
94527ead GH |
971 | break; |
972 | ||
973 | case ASYNCLISTADDR: | |
974 | if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) { | |
975 | fprintf(stderr, | |
976 | "ehci: ASYNC list address register set while async schedule\n" | |
977 | " is enabled and HC is enabled\n"); | |
978 | } | |
94527ead GH |
979 | break; |
980 | } | |
981 | ||
c4f8e211 GH |
982 | *mmio = val; |
983 | trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old); | |
94527ead GH |
984 | } |
985 | ||
986 | ||
987 | // TODO : Put in common header file, duplication from usb-ohci.c | |
988 | ||
989 | /* Get an array of dwords from main memory */ | |
990 | static inline int get_dwords(uint32_t addr, uint32_t *buf, int num) | |
991 | { | |
992 | int i; | |
993 | ||
994 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
995 | cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0); | |
996 | *buf = le32_to_cpu(*buf); | |
997 | } | |
998 | ||
999 | return 1; | |
1000 | } | |
1001 | ||
1002 | /* Put an array of dwords in to main memory */ | |
1003 | static inline int put_dwords(uint32_t addr, uint32_t *buf, int num) | |
1004 | { | |
1005 | int i; | |
1006 | ||
1007 | for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { | |
1008 | uint32_t tmp = cpu_to_le32(*buf); | |
1009 | cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1); | |
1010 | } | |
1011 | ||
1012 | return 1; | |
1013 | } | |
1014 | ||
1015 | // 4.10.2 | |
1016 | ||
0122f472 | 1017 | static int ehci_qh_do_overlay(EHCIQueue *q) |
94527ead GH |
1018 | { |
1019 | int i; | |
1020 | int dtoggle; | |
1021 | int ping; | |
1022 | int eps; | |
1023 | int reload; | |
1024 | ||
1025 | // remember values in fields to preserve in qh after overlay | |
1026 | ||
0122f472 GH |
1027 | dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE; |
1028 | ping = q->qh.token & QTD_TOKEN_PING; | |
94527ead | 1029 | |
0122f472 GH |
1030 | q->qh.current_qtd = q->qtdaddr; |
1031 | q->qh.next_qtd = q->qtd.next; | |
1032 | q->qh.altnext_qtd = q->qtd.altnext; | |
1033 | q->qh.token = q->qtd.token; | |
94527ead GH |
1034 | |
1035 | ||
0122f472 | 1036 | eps = get_field(q->qh.epchar, QH_EPCHAR_EPS); |
94527ead | 1037 | if (eps == EHCI_QH_EPS_HIGH) { |
0122f472 GH |
1038 | q->qh.token &= ~QTD_TOKEN_PING; |
1039 | q->qh.token |= ping; | |
94527ead GH |
1040 | } |
1041 | ||
0122f472 GH |
1042 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1043 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); | |
94527ead GH |
1044 | |
1045 | for (i = 0; i < 5; i++) { | |
0122f472 | 1046 | q->qh.bufptr[i] = q->qtd.bufptr[i]; |
94527ead GH |
1047 | } |
1048 | ||
0122f472 | 1049 | if (!(q->qh.epchar & QH_EPCHAR_DTC)) { |
94527ead | 1050 | // preserve QH DT bit |
0122f472 GH |
1051 | q->qh.token &= ~QTD_TOKEN_DTOGGLE; |
1052 | q->qh.token |= dtoggle; | |
94527ead GH |
1053 | } |
1054 | ||
0122f472 GH |
1055 | q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK; |
1056 | q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK; | |
94527ead | 1057 | |
0122f472 | 1058 | put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); |
94527ead GH |
1059 | |
1060 | return 0; | |
1061 | } | |
1062 | ||
0122f472 | 1063 | static int ehci_buffer_rw(EHCIQueue *q, int bytes, int rw) |
94527ead GH |
1064 | { |
1065 | int bufpos = 0; | |
1066 | int cpage, offset; | |
1067 | uint32_t head; | |
1068 | uint32_t tail; | |
1069 | ||
1070 | ||
1071 | if (!bytes) { | |
1072 | return 0; | |
1073 | } | |
1074 | ||
0122f472 | 1075 | cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE); |
94527ead GH |
1076 | if (cpage > 4) { |
1077 | fprintf(stderr, "cpage out of range (%d)\n", cpage); | |
1078 | return USB_RET_PROCERR; | |
1079 | } | |
1080 | ||
0122f472 | 1081 | offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK; |
94527ead GH |
1082 | |
1083 | do { | |
1084 | /* start and end of this page */ | |
0122f472 | 1085 | head = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK; |
94527ead GH |
1086 | tail = head + ~QTD_BUFPTR_MASK + 1; |
1087 | /* add offset into page */ | |
1088 | head |= offset; | |
1089 | ||
1090 | if (bytes <= (tail - head)) { | |
1091 | tail = head + bytes; | |
1092 | } | |
1093 | ||
f2c88dc1 | 1094 | trace_usb_ehci_data(rw, cpage, offset, head, tail-head, bufpos); |
0122f472 | 1095 | cpu_physical_memory_rw(head, q->buffer + bufpos, tail - head, rw); |
94527ead GH |
1096 | |
1097 | bufpos += (tail - head); | |
ba7cb5a8 | 1098 | offset += (tail - head); |
94527ead GH |
1099 | bytes -= (tail - head); |
1100 | ||
1101 | if (bytes > 0) { | |
1102 | cpage++; | |
1103 | offset = 0; | |
1104 | } | |
1105 | } while (bytes > 0); | |
1106 | ||
1107 | /* save cpage */ | |
0122f472 | 1108 | set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE); |
94527ead GH |
1109 | |
1110 | /* save offset into cpage */ | |
ba7cb5a8 | 1111 | q->qh.bufptr[0] &= QTD_BUFPTR_MASK; |
0122f472 | 1112 | q->qh.bufptr[0] |= offset; |
94527ead GH |
1113 | |
1114 | return 0; | |
1115 | } | |
1116 | ||
d47e59b8 | 1117 | static void ehci_async_complete_packet(USBPort *port, USBPacket *packet) |
94527ead | 1118 | { |
0122f472 | 1119 | EHCIQueue *q = container_of(packet, EHCIQueue, packet); |
94527ead | 1120 | |
8ac6d699 GH |
1121 | trace_usb_ehci_queue_action(q, "wakeup"); |
1122 | assert(q->async == EHCI_ASYNC_INFLIGHT); | |
0122f472 GH |
1123 | q->async = EHCI_ASYNC_FINISHED; |
1124 | q->usb_status = packet->len; | |
94527ead GH |
1125 | } |
1126 | ||
0122f472 | 1127 | static void ehci_execute_complete(EHCIQueue *q) |
94527ead GH |
1128 | { |
1129 | int c_err, reload; | |
1130 | ||
8ac6d699 | 1131 | assert(q->async != EHCI_ASYNC_INFLIGHT); |
0122f472 | 1132 | q->async = EHCI_ASYNC_NONE; |
94527ead GH |
1133 | |
1134 | DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n", | |
0122f472 | 1135 | q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status); |
94527ead | 1136 | |
0122f472 | 1137 | if (q->usb_status < 0) { |
94527ead GH |
1138 | err: |
1139 | /* TO-DO: put this is in a function that can be invoked below as well */ | |
0122f472 | 1140 | c_err = get_field(q->qh.token, QTD_TOKEN_CERR); |
94527ead | 1141 | c_err--; |
0122f472 | 1142 | set_field(&q->qh.token, c_err, QTD_TOKEN_CERR); |
94527ead | 1143 | |
0122f472 | 1144 | switch(q->usb_status) { |
94527ead | 1145 | case USB_RET_NODEV: |
d2bd525f GH |
1146 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR); |
1147 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1148 | break; |
1149 | case USB_RET_STALL: | |
0122f472 GH |
1150 | q->qh.token |= QTD_TOKEN_HALT; |
1151 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); | |
94527ead GH |
1152 | break; |
1153 | case USB_RET_NAK: | |
1154 | /* 4.10.3 */ | |
0122f472 GH |
1155 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1156 | if ((q->pid == USB_TOKEN_IN) && reload) { | |
1157 | int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
94527ead | 1158 | nakcnt--; |
0122f472 | 1159 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); |
94527ead | 1160 | } else if (!reload) { |
0122f472 | 1161 | return; |
94527ead GH |
1162 | } |
1163 | break; | |
1164 | case USB_RET_BABBLE: | |
d2bd525f | 1165 | q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE); |
0122f472 | 1166 | ehci_record_interrupt(q->ehci, USBSTS_ERRINT); |
94527ead GH |
1167 | break; |
1168 | default: | |
0122f472 GH |
1169 | /* should not be triggerable */ |
1170 | fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status); | |
1171 | assert(0); | |
94527ead GH |
1172 | break; |
1173 | } | |
1174 | } else { | |
1175 | // DPRINTF("Short packet condition\n"); | |
1176 | // TODO check 4.12 for splits | |
1177 | ||
0122f472 GH |
1178 | if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) { |
1179 | q->usb_status = USB_RET_BABBLE; | |
94527ead GH |
1180 | goto err; |
1181 | } | |
1182 | ||
0122f472 GH |
1183 | if (q->tbytes && q->pid == USB_TOKEN_IN) { |
1184 | if (ehci_buffer_rw(q, q->usb_status, 1) != 0) { | |
1185 | q->usb_status = USB_RET_PROCERR; | |
1186 | return; | |
94527ead | 1187 | } |
0122f472 | 1188 | q->tbytes -= q->usb_status; |
94527ead | 1189 | } else { |
0122f472 | 1190 | q->tbytes = 0; |
94527ead GH |
1191 | } |
1192 | ||
0122f472 GH |
1193 | DPRINTF("updating tbytes to %d\n", q->tbytes); |
1194 | set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES); | |
94527ead GH |
1195 | } |
1196 | ||
0122f472 GH |
1197 | q->qh.token ^= QTD_TOKEN_DTOGGLE; |
1198 | q->qh.token &= ~QTD_TOKEN_ACTIVE; | |
94527ead | 1199 | |
0122f472 GH |
1200 | if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) { |
1201 | ehci_record_interrupt(q->ehci, USBSTS_INT); | |
94527ead | 1202 | } |
94527ead GH |
1203 | } |
1204 | ||
1205 | // 4.10.3 | |
1206 | ||
0122f472 | 1207 | static int ehci_execute(EHCIQueue *q) |
94527ead GH |
1208 | { |
1209 | USBPort *port; | |
1210 | USBDevice *dev; | |
1211 | int ret; | |
1212 | int i; | |
1213 | int endp; | |
1214 | int devadr; | |
1215 | ||
0122f472 | 1216 | if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) { |
94527ead GH |
1217 | fprintf(stderr, "Attempting to execute inactive QH\n"); |
1218 | return USB_RET_PROCERR; | |
1219 | } | |
1220 | ||
0122f472 GH |
1221 | q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH; |
1222 | if (q->tbytes > BUFF_SIZE) { | |
94527ead GH |
1223 | fprintf(stderr, "Request for more bytes than allowed\n"); |
1224 | return USB_RET_PROCERR; | |
1225 | } | |
1226 | ||
0122f472 GH |
1227 | q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH; |
1228 | switch(q->pid) { | |
1229 | case 0: q->pid = USB_TOKEN_OUT; break; | |
1230 | case 1: q->pid = USB_TOKEN_IN; break; | |
1231 | case 2: q->pid = USB_TOKEN_SETUP; break; | |
94527ead GH |
1232 | default: fprintf(stderr, "bad token\n"); break; |
1233 | } | |
1234 | ||
0122f472 GH |
1235 | if ((q->tbytes && q->pid != USB_TOKEN_IN) && |
1236 | (ehci_buffer_rw(q, q->tbytes, 0) != 0)) { | |
94527ead GH |
1237 | return USB_RET_PROCERR; |
1238 | } | |
1239 | ||
0122f472 GH |
1240 | endp = get_field(q->qh.epchar, QH_EPCHAR_EP); |
1241 | devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR); | |
94527ead GH |
1242 | |
1243 | ret = USB_RET_NODEV; | |
1244 | ||
1245 | // TO-DO: associating device with ehci port | |
1246 | for(i = 0; i < NB_PORTS; i++) { | |
0122f472 | 1247 | port = &q->ehci->ports[i]; |
94527ead GH |
1248 | dev = port->dev; |
1249 | ||
1250 | // TODO sometime we will also need to check if we are the port owner | |
1251 | ||
0122f472 | 1252 | if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) { |
94527ead | 1253 | DPRINTF("Port %d, no exec, not connected(%08X)\n", |
0122f472 | 1254 | i, q->ehci->portsc[i]); |
94527ead GH |
1255 | continue; |
1256 | } | |
1257 | ||
0122f472 GH |
1258 | q->packet.pid = q->pid; |
1259 | q->packet.devaddr = devadr; | |
1260 | q->packet.devep = endp; | |
1261 | q->packet.data = q->buffer; | |
1262 | q->packet.len = q->tbytes; | |
94527ead | 1263 | |
0122f472 | 1264 | ret = usb_handle_packet(dev, &q->packet); |
94527ead GH |
1265 | |
1266 | DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n", | |
0122f472 GH |
1267 | q->qhaddr, q->qh.next, q->qtdaddr, q->pid, |
1268 | q->packet.len, q->tbytes, endp, ret); | |
94527ead GH |
1269 | |
1270 | if (ret != USB_RET_NODEV) { | |
1271 | break; | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | if (ret > BUFF_SIZE) { | |
1276 | fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n"); | |
1277 | return USB_RET_PROCERR; | |
1278 | } | |
1279 | ||
94527ead GH |
1280 | return ret; |
1281 | } | |
1282 | ||
1283 | /* 4.7.2 | |
1284 | */ | |
1285 | ||
1286 | static int ehci_process_itd(EHCIState *ehci, | |
1287 | EHCIitd *itd) | |
1288 | { | |
1289 | USBPort *port; | |
1290 | USBDevice *dev; | |
1291 | int ret; | |
e654887f GH |
1292 | uint32_t i, j, len, len1, len2, pid, dir, devaddr, endp; |
1293 | uint32_t pg, off, ptr1, ptr2, max, mult; | |
94527ead GH |
1294 | |
1295 | dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); | |
e654887f | 1296 | devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); |
94527ead | 1297 | endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP); |
e654887f GH |
1298 | max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); |
1299 | mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT); | |
94527ead GH |
1300 | |
1301 | for(i = 0; i < 8; i++) { | |
1302 | if (itd->transact[i] & ITD_XACT_ACTIVE) { | |
e654887f GH |
1303 | pg = get_field(itd->transact[i], ITD_XACT_PGSEL); |
1304 | off = itd->transact[i] & ITD_XACT_OFFSET_MASK; | |
1305 | ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK); | |
1306 | ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK); | |
1307 | len = get_field(itd->transact[i], ITD_XACT_LENGTH); | |
1308 | ||
1309 | if (len > max * mult) { | |
1310 | len = max * mult; | |
1311 | } | |
94527ead GH |
1312 | |
1313 | if (len > BUFF_SIZE) { | |
1314 | return USB_RET_PROCERR; | |
1315 | } | |
1316 | ||
e654887f GH |
1317 | if (off + len > 4096) { |
1318 | /* transfer crosses page border */ | |
1319 | len2 = off + len - 4096; | |
1320 | len1 = len - len2; | |
1321 | } else { | |
1322 | len1 = len; | |
1323 | len2 = 0; | |
1324 | } | |
94527ead GH |
1325 | |
1326 | if (!dir) { | |
94527ead | 1327 | pid = USB_TOKEN_OUT; |
e654887f GH |
1328 | trace_usb_ehci_data(0, pg, off, ptr1 + off, len1, 0); |
1329 | cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 0); | |
1330 | if (len2) { | |
1331 | trace_usb_ehci_data(0, pg+1, 0, ptr2, len2, len1); | |
1332 | cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 0); | |
1333 | } | |
1334 | } else { | |
94527ead | 1335 | pid = USB_TOKEN_IN; |
e654887f | 1336 | } |
94527ead GH |
1337 | |
1338 | ret = USB_RET_NODEV; | |
1339 | ||
1340 | for (j = 0; j < NB_PORTS; j++) { | |
1341 | port = &ehci->ports[j]; | |
1342 | dev = port->dev; | |
1343 | ||
1344 | // TODO sometime we will also need to check if we are the port owner | |
1345 | ||
1346 | if (!(ehci->portsc[j] &(PORTSC_CONNECT))) { | |
94527ead GH |
1347 | continue; |
1348 | } | |
1349 | ||
0122f472 | 1350 | ehci->ipacket.pid = pid; |
e654887f | 1351 | ehci->ipacket.devaddr = devaddr; |
0122f472 GH |
1352 | ehci->ipacket.devep = endp; |
1353 | ehci->ipacket.data = ehci->ibuffer; | |
1354 | ehci->ipacket.len = len; | |
94527ead | 1355 | |
0122f472 | 1356 | ret = usb_handle_packet(dev, &ehci->ipacket); |
94527ead GH |
1357 | |
1358 | if (ret != USB_RET_NODEV) { | |
1359 | break; | |
1360 | } | |
1361 | } | |
1362 | ||
e654887f | 1363 | #if 0 |
94527ead GH |
1364 | /* In isoch, there is no facility to indicate a NAK so let's |
1365 | * instead just complete a zero-byte transaction. Setting | |
1366 | * DBERR seems too draconian. | |
1367 | */ | |
1368 | ||
1369 | if (ret == USB_RET_NAK) { | |
1370 | if (ehci->isoch_pause > 0) { | |
1371 | DPRINTF("ISOCH: received a NAK but paused so returning\n"); | |
1372 | ehci->isoch_pause--; | |
1373 | return 0; | |
1374 | } else if (ehci->isoch_pause == -1) { | |
1375 | DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n"); | |
1376 | // Pause frindex for up to 50 msec waiting for data from | |
1377 | // remote | |
1378 | ehci->isoch_pause = 50; | |
1379 | return 0; | |
1380 | } else { | |
1381 | DPRINTF("ISOCH: isoch pause timeout! return 0\n"); | |
1382 | ret = 0; | |
1383 | } | |
1384 | } else { | |
1385 | DPRINTF("ISOCH: received ACK, clearing pause\n"); | |
1386 | ehci->isoch_pause = -1; | |
1387 | } | |
e654887f GH |
1388 | #else |
1389 | if (ret == USB_RET_NAK) { | |
1390 | ret = 0; | |
1391 | } | |
1392 | #endif | |
94527ead GH |
1393 | |
1394 | if (ret >= 0) { | |
e654887f GH |
1395 | if (!dir) { |
1396 | /* OUT */ | |
1397 | set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH); | |
1398 | } else { | |
1399 | /* IN */ | |
1400 | if (len1 > ret) { | |
1401 | len1 = ret; | |
1402 | } | |
1403 | if (len2 > ret - len1) { | |
1404 | len2 = ret - len1; | |
1405 | } | |
1406 | if (len1) { | |
1407 | trace_usb_ehci_data(1, pg, off, ptr1 + off, len1, 0); | |
1408 | cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 1); | |
1409 | } | |
1410 | if (len2) { | |
1411 | trace_usb_ehci_data(1, pg+1, 0, ptr2, len2, len1); | |
1412 | cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 1); | |
1413 | } | |
1414 | set_field(&itd->transact[i], ret, ITD_XACT_LENGTH); | |
1415 | } | |
94527ead GH |
1416 | |
1417 | if (itd->transact[i] & ITD_XACT_IOC) { | |
1418 | ehci_record_interrupt(ehci, USBSTS_INT); | |
1419 | } | |
1420 | } | |
e654887f | 1421 | itd->transact[i] &= ~ITD_XACT_ACTIVE; |
94527ead GH |
1422 | } |
1423 | } | |
1424 | return 0; | |
1425 | } | |
1426 | ||
1427 | /* This state is the entry point for asynchronous schedule | |
1428 | * processing. Entry here consitutes a EHCI start event state (4.8.5) | |
1429 | */ | |
26d53979 | 1430 | static int ehci_state_waitlisthead(EHCIState *ehci, int async) |
94527ead | 1431 | { |
0122f472 | 1432 | EHCIqh qh; |
94527ead GH |
1433 | int i = 0; |
1434 | int again = 0; | |
1435 | uint32_t entry = ehci->asynclistaddr; | |
1436 | ||
1437 | /* set reclamation flag at start event (4.8.6) */ | |
1438 | if (async) { | |
439a97cc | 1439 | ehci_set_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1440 | } |
1441 | ||
8ac6d699 GH |
1442 | ehci_queues_rip_unused(ehci); |
1443 | ||
94527ead GH |
1444 | /* Find the head of the list (4.9.1.1) */ |
1445 | for(i = 0; i < MAX_QH; i++) { | |
0122f472 | 1446 | get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2); |
8ac6d699 | 1447 | ehci_trace_qh(NULL, NLPTR_GET(entry), &qh); |
94527ead | 1448 | |
0122f472 | 1449 | if (qh.epchar & QH_EPCHAR_H) { |
94527ead GH |
1450 | if (async) { |
1451 | entry |= (NLPTR_TYPE_QH << 1); | |
1452 | } | |
1453 | ||
0122f472 | 1454 | ehci_set_fetch_addr(ehci, async, entry); |
26d53979 | 1455 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1456 | again = 1; |
1457 | goto out; | |
1458 | } | |
1459 | ||
0122f472 | 1460 | entry = qh.next; |
94527ead | 1461 | if (entry == ehci->asynclistaddr) { |
94527ead GH |
1462 | break; |
1463 | } | |
1464 | } | |
1465 | ||
1466 | /* no head found for list. */ | |
1467 | ||
26d53979 | 1468 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1469 | |
1470 | out: | |
1471 | return again; | |
1472 | } | |
1473 | ||
1474 | ||
1475 | /* This state is the entry point for periodic schedule processing as | |
1476 | * well as being a continuation state for async processing. | |
1477 | */ | |
26d53979 | 1478 | static int ehci_state_fetchentry(EHCIState *ehci, int async) |
94527ead GH |
1479 | { |
1480 | int again = 0; | |
0122f472 | 1481 | uint32_t entry = ehci_get_fetch_addr(ehci, async); |
94527ead | 1482 | |
94527ead GH |
1483 | if (entry < 0x1000) { |
1484 | DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry); | |
26d53979 | 1485 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1486 | goto out; |
1487 | } | |
1488 | ||
1489 | /* section 4.8, only QH in async schedule */ | |
1490 | if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) { | |
1491 | fprintf(stderr, "non queue head request in async schedule\n"); | |
1492 | return -1; | |
1493 | } | |
1494 | ||
1495 | switch (NLPTR_TYPE_GET(entry)) { | |
1496 | case NLPTR_TYPE_QH: | |
26d53979 | 1497 | ehci_set_state(ehci, async, EST_FETCHQH); |
94527ead GH |
1498 | again = 1; |
1499 | break; | |
1500 | ||
1501 | case NLPTR_TYPE_ITD: | |
26d53979 | 1502 | ehci_set_state(ehci, async, EST_FETCHITD); |
94527ead GH |
1503 | again = 1; |
1504 | break; | |
1505 | ||
1506 | default: | |
1507 | // TODO: handle siTD and FSTN types | |
1508 | fprintf(stderr, "FETCHENTRY: entry at %X is of type %d " | |
1509 | "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry)); | |
1510 | return -1; | |
1511 | } | |
1512 | ||
1513 | out: | |
1514 | return again; | |
1515 | } | |
1516 | ||
0122f472 | 1517 | static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async) |
94527ead | 1518 | { |
0122f472 GH |
1519 | uint32_t entry; |
1520 | EHCIQueue *q; | |
94527ead | 1521 | int reload; |
94527ead | 1522 | |
0122f472 | 1523 | entry = ehci_get_fetch_addr(ehci, async); |
8ac6d699 GH |
1524 | q = ehci_find_queue_by_qh(ehci, entry); |
1525 | if (NULL == q) { | |
1526 | q = ehci_alloc_queue(ehci, async); | |
1527 | } | |
0122f472 | 1528 | q->qhaddr = entry; |
8ac6d699 GH |
1529 | q->seen++; |
1530 | ||
1531 | if (q->seen > 1) { | |
1532 | /* we are going in circles -- stop processing */ | |
1533 | ehci_set_state(ehci, async, EST_ACTIVE); | |
1534 | q = NULL; | |
1535 | goto out; | |
1536 | } | |
94527ead | 1537 | |
0122f472 | 1538 | get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2); |
8ac6d699 GH |
1539 | ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh); |
1540 | ||
1541 | if (q->async == EHCI_ASYNC_INFLIGHT) { | |
1542 | /* I/O still in progress -- skip queue */ | |
1543 | ehci_set_state(ehci, async, EST_HORIZONTALQH); | |
1544 | goto out; | |
1545 | } | |
1546 | if (q->async == EHCI_ASYNC_FINISHED) { | |
1547 | /* I/O finished -- continue processing queue */ | |
1548 | trace_usb_ehci_queue_action(q, "resume"); | |
1549 | ehci_set_state(ehci, async, EST_EXECUTING); | |
1550 | goto out; | |
1551 | } | |
0122f472 GH |
1552 | |
1553 | if (async && (q->qh.epchar & QH_EPCHAR_H)) { | |
94527ead GH |
1554 | |
1555 | /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */ | |
1556 | if (ehci->usbsts & USBSTS_REC) { | |
439a97cc | 1557 | ehci_clear_usbsts(ehci, USBSTS_REC); |
94527ead GH |
1558 | } else { |
1559 | DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset" | |
0122f472 | 1560 | " - done processing\n", q->qhaddr); |
26d53979 | 1561 | ehci_set_state(ehci, async, EST_ACTIVE); |
0122f472 | 1562 | q = NULL; |
94527ead GH |
1563 | goto out; |
1564 | } | |
1565 | } | |
1566 | ||
1567 | #if EHCI_DEBUG | |
0122f472 | 1568 | if (q->qhaddr != q->qh.next) { |
94527ead | 1569 | DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", |
0122f472 GH |
1570 | q->qhaddr, |
1571 | q->qh.epchar & QH_EPCHAR_H, | |
1572 | q->qh.token & QTD_TOKEN_HALT, | |
1573 | q->qh.token & QTD_TOKEN_ACTIVE, | |
1574 | q->qh.next); | |
94527ead GH |
1575 | } |
1576 | #endif | |
1577 | ||
0122f472 | 1578 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
94527ead | 1579 | if (reload) { |
0122f472 | 1580 | set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT); |
94527ead GH |
1581 | } |
1582 | ||
0122f472 | 1583 | if (q->qh.token & QTD_TOKEN_HALT) { |
26d53979 | 1584 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead | 1585 | |
0122f472 GH |
1586 | } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) { |
1587 | q->qtdaddr = q->qh.current_qtd; | |
26d53979 | 1588 | ehci_set_state(ehci, async, EST_FETCHQTD); |
94527ead GH |
1589 | |
1590 | } else { | |
1591 | /* EHCI spec version 1.0 Section 4.10.2 */ | |
26d53979 | 1592 | ehci_set_state(ehci, async, EST_ADVANCEQUEUE); |
94527ead GH |
1593 | } |
1594 | ||
1595 | out: | |
0122f472 | 1596 | return q; |
94527ead GH |
1597 | } |
1598 | ||
26d53979 | 1599 | static int ehci_state_fetchitd(EHCIState *ehci, int async) |
94527ead | 1600 | { |
0122f472 | 1601 | uint32_t entry; |
94527ead GH |
1602 | EHCIitd itd; |
1603 | ||
0122f472 GH |
1604 | assert(!async); |
1605 | entry = ehci_get_fetch_addr(ehci, async); | |
1606 | ||
1607 | get_dwords(NLPTR_GET(entry),(uint32_t *) &itd, | |
94527ead | 1608 | sizeof(EHCIitd) >> 2); |
0122f472 | 1609 | ehci_trace_itd(ehci, entry, &itd); |
94527ead GH |
1610 | |
1611 | if (ehci_process_itd(ehci, &itd) != 0) { | |
1612 | return -1; | |
1613 | } | |
1614 | ||
0122f472 | 1615 | put_dwords(NLPTR_GET(entry), (uint32_t *) &itd, |
94527ead | 1616 | sizeof(EHCIitd) >> 2); |
0122f472 | 1617 | ehci_set_fetch_addr(ehci, async, itd.next); |
26d53979 | 1618 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
94527ead GH |
1619 | |
1620 | return 1; | |
1621 | } | |
1622 | ||
1623 | /* Section 4.10.2 - paragraph 3 */ | |
0122f472 | 1624 | static int ehci_state_advqueue(EHCIQueue *q, int async) |
94527ead GH |
1625 | { |
1626 | #if 0 | |
1627 | /* TO-DO: 4.10.2 - paragraph 2 | |
1628 | * if I-bit is set to 1 and QH is not active | |
1629 | * go to horizontal QH | |
1630 | */ | |
1631 | if (I-bit set) { | |
26d53979 | 1632 | ehci_set_state(ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1633 | goto out; |
1634 | } | |
1635 | #endif | |
1636 | ||
1637 | /* | |
1638 | * want data and alt-next qTD is valid | |
1639 | */ | |
0122f472 GH |
1640 | if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) && |
1641 | (q->qh.altnext_qtd > 0x1000) && | |
1642 | (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) { | |
1643 | q->qtdaddr = q->qh.altnext_qtd; | |
1644 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1645 | |
1646 | /* | |
1647 | * next qTD is valid | |
1648 | */ | |
0122f472 GH |
1649 | } else if ((q->qh.next_qtd > 0x1000) && |
1650 | (NLPTR_TBIT(q->qh.next_qtd) == 0)) { | |
1651 | q->qtdaddr = q->qh.next_qtd; | |
1652 | ehci_set_state(q->ehci, async, EST_FETCHQTD); | |
94527ead GH |
1653 | |
1654 | /* | |
1655 | * no valid qTD, try next QH | |
1656 | */ | |
1657 | } else { | |
0122f472 | 1658 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1659 | } |
1660 | ||
1661 | return 1; | |
1662 | } | |
1663 | ||
1664 | /* Section 4.10.2 - paragraph 4 */ | |
0122f472 | 1665 | static int ehci_state_fetchqtd(EHCIQueue *q, int async) |
94527ead | 1666 | { |
94527ead GH |
1667 | int again = 0; |
1668 | ||
0122f472 | 1669 | get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2); |
8ac6d699 | 1670 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd); |
94527ead | 1671 | |
0122f472 GH |
1672 | if (q->qtd.token & QTD_TOKEN_ACTIVE) { |
1673 | ehci_set_state(q->ehci, async, EST_EXECUTE); | |
94527ead GH |
1674 | again = 1; |
1675 | } else { | |
0122f472 | 1676 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1677 | again = 1; |
1678 | } | |
1679 | ||
1680 | return again; | |
1681 | } | |
1682 | ||
0122f472 | 1683 | static int ehci_state_horizqh(EHCIQueue *q, int async) |
94527ead GH |
1684 | { |
1685 | int again = 0; | |
1686 | ||
0122f472 GH |
1687 | if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) { |
1688 | ehci_set_fetch_addr(q->ehci, async, q->qh.next); | |
1689 | ehci_set_state(q->ehci, async, EST_FETCHENTRY); | |
94527ead GH |
1690 | again = 1; |
1691 | } else { | |
0122f472 | 1692 | ehci_set_state(q->ehci, async, EST_ACTIVE); |
94527ead GH |
1693 | } |
1694 | ||
1695 | return again; | |
1696 | } | |
1697 | ||
8ac6d699 GH |
1698 | /* |
1699 | * Write the qh back to guest physical memory. This step isn't | |
1700 | * in the EHCI spec but we need to do it since we don't share | |
1701 | * physical memory with our guest VM. | |
1702 | * | |
1703 | * The first three dwords are read-only for the EHCI, so skip them | |
1704 | * when writing back the qh. | |
1705 | */ | |
1706 | static void ehci_flush_qh(EHCIQueue *q) | |
1707 | { | |
1708 | uint32_t *qh = (uint32_t *) &q->qh; | |
1709 | uint32_t dwords = sizeof(EHCIqh) >> 2; | |
1710 | uint32_t addr = NLPTR_GET(q->qhaddr); | |
1711 | ||
1712 | put_dwords(addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); | |
1713 | } | |
1714 | ||
0122f472 | 1715 | static int ehci_state_execute(EHCIQueue *q, int async) |
94527ead | 1716 | { |
94527ead GH |
1717 | int again = 0; |
1718 | int reload, nakcnt; | |
1719 | int smask; | |
1720 | ||
0122f472 | 1721 | if (ehci_qh_do_overlay(q) != 0) { |
94527ead GH |
1722 | return -1; |
1723 | } | |
1724 | ||
0122f472 | 1725 | smask = get_field(q->qh.epcap, QH_EPCAP_SMASK); |
94527ead GH |
1726 | |
1727 | if (!smask) { | |
0122f472 GH |
1728 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
1729 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); | |
94527ead | 1730 | if (reload && !nakcnt) { |
0122f472 | 1731 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1732 | again = 1; |
1733 | goto out; | |
1734 | } | |
1735 | } | |
1736 | ||
1737 | // TODO verify enough time remains in the uframe as in 4.4.1.1 | |
1738 | // TODO write back ptr to async list when done or out of time | |
1739 | // TODO Windows does not seem to ever set the MULT field | |
1740 | ||
1741 | if (!async) { | |
0122f472 | 1742 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1743 | if (!transactCtr) { |
0122f472 | 1744 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); |
94527ead GH |
1745 | again = 1; |
1746 | goto out; | |
1747 | } | |
1748 | } | |
1749 | ||
1750 | if (async) { | |
0122f472 | 1751 | ehci_set_usbsts(q->ehci, USBSTS_REC); |
94527ead GH |
1752 | } |
1753 | ||
0122f472 GH |
1754 | q->usb_status = ehci_execute(q); |
1755 | if (q->usb_status == USB_RET_PROCERR) { | |
94527ead GH |
1756 | again = -1; |
1757 | goto out; | |
1758 | } | |
8ac6d699 GH |
1759 | if (q->usb_status == USB_RET_ASYNC) { |
1760 | ehci_flush_qh(q); | |
1761 | trace_usb_ehci_queue_action(q, "suspend"); | |
1762 | q->async = EHCI_ASYNC_INFLIGHT; | |
1763 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
94527ead | 1764 | again = 1; |
8ac6d699 | 1765 | goto out; |
94527ead GH |
1766 | } |
1767 | ||
8ac6d699 GH |
1768 | ehci_set_state(q->ehci, async, EST_EXECUTING); |
1769 | again = 1; | |
1770 | ||
94527ead GH |
1771 | out: |
1772 | return again; | |
1773 | } | |
1774 | ||
0122f472 | 1775 | static int ehci_state_executing(EHCIQueue *q, int async) |
94527ead | 1776 | { |
94527ead GH |
1777 | int again = 0; |
1778 | int reload, nakcnt; | |
1779 | ||
0122f472 GH |
1780 | ehci_execute_complete(q); |
1781 | if (q->usb_status == USB_RET_ASYNC) { | |
94527ead GH |
1782 | goto out; |
1783 | } | |
0122f472 | 1784 | if (q->usb_status == USB_RET_PROCERR) { |
94527ead GH |
1785 | again = -1; |
1786 | goto out; | |
1787 | } | |
1788 | ||
1789 | // 4.10.3 | |
1790 | if (!async) { | |
0122f472 | 1791 | int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT); |
94527ead | 1792 | transactCtr--; |
0122f472 | 1793 | set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT); |
94527ead GH |
1794 | // 4.10.3, bottom of page 82, should exit this state when transaction |
1795 | // counter decrements to 0 | |
1796 | } | |
1797 | ||
0122f472 | 1798 | reload = get_field(q->qh.epchar, QH_EPCHAR_RL); |
94527ead | 1799 | if (reload) { |
0122f472 GH |
1800 | nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT); |
1801 | if (q->usb_status == USB_RET_NAK) { | |
94527ead GH |
1802 | if (nakcnt) { |
1803 | nakcnt--; | |
1804 | } | |
94527ead GH |
1805 | } else { |
1806 | nakcnt = reload; | |
94527ead | 1807 | } |
0122f472 | 1808 | set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT); |
94527ead GH |
1809 | } |
1810 | ||
94527ead | 1811 | /* 4.10.5 */ |
0122f472 GH |
1812 | if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) { |
1813 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
94527ead | 1814 | } else { |
0122f472 | 1815 | ehci_set_state(q->ehci, async, EST_WRITEBACK); |
94527ead GH |
1816 | } |
1817 | ||
1818 | again = 1; | |
1819 | ||
1820 | out: | |
8ac6d699 | 1821 | ehci_flush_qh(q); |
94527ead GH |
1822 | return again; |
1823 | } | |
1824 | ||
1825 | ||
0122f472 | 1826 | static int ehci_state_writeback(EHCIQueue *q, int async) |
94527ead | 1827 | { |
94527ead GH |
1828 | int again = 0; |
1829 | ||
1830 | /* Write back the QTD from the QH area */ | |
8ac6d699 | 1831 | ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd); |
0122f472 | 1832 | put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd, |
94527ead GH |
1833 | sizeof(EHCIqtd) >> 2); |
1834 | ||
d2bd525f GH |
1835 | /* |
1836 | * EHCI specs say go horizontal here. | |
1837 | * | |
1838 | * We can also advance the queue here for performance reasons. We | |
1839 | * need to take care to only take that shortcut in case we've | |
1840 | * processed the qtd just written back without errors, i.e. halt | |
1841 | * bit is clear. | |
94527ead | 1842 | */ |
d2bd525f GH |
1843 | if (q->qh.token & QTD_TOKEN_HALT) { |
1844 | ehci_set_state(q->ehci, async, EST_HORIZONTALQH); | |
1845 | again = 1; | |
1846 | } else { | |
0122f472 | 1847 | ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE); |
94527ead | 1848 | again = 1; |
d2bd525f | 1849 | } |
94527ead GH |
1850 | return again; |
1851 | } | |
1852 | ||
1853 | /* | |
1854 | * This is the state machine that is common to both async and periodic | |
1855 | */ | |
1856 | ||
26d53979 GH |
1857 | static void ehci_advance_state(EHCIState *ehci, |
1858 | int async) | |
94527ead | 1859 | { |
0122f472 | 1860 | EHCIQueue *q = NULL; |
94527ead GH |
1861 | int again; |
1862 | int iter = 0; | |
1863 | ||
1864 | do { | |
26d53979 | 1865 | if (ehci_get_state(ehci, async) == EST_FETCHQH) { |
94527ead GH |
1866 | iter++; |
1867 | /* if we are roaming a lot of QH without executing a qTD | |
1868 | * something is wrong with the linked list. TO-DO: why is | |
1869 | * this hack needed? | |
1870 | */ | |
8ac6d699 GH |
1871 | assert(iter < MAX_ITERATIONS); |
1872 | #if 0 | |
94527ead GH |
1873 | if (iter > MAX_ITERATIONS) { |
1874 | DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n"); | |
26d53979 | 1875 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1876 | break; |
1877 | } | |
8ac6d699 | 1878 | #endif |
94527ead | 1879 | } |
26d53979 | 1880 | switch(ehci_get_state(ehci, async)) { |
94527ead | 1881 | case EST_WAITLISTHEAD: |
26d53979 | 1882 | again = ehci_state_waitlisthead(ehci, async); |
94527ead GH |
1883 | break; |
1884 | ||
1885 | case EST_FETCHENTRY: | |
26d53979 | 1886 | again = ehci_state_fetchentry(ehci, async); |
94527ead GH |
1887 | break; |
1888 | ||
1889 | case EST_FETCHQH: | |
0122f472 GH |
1890 | q = ehci_state_fetchqh(ehci, async); |
1891 | again = q ? 1 : 0; | |
94527ead GH |
1892 | break; |
1893 | ||
1894 | case EST_FETCHITD: | |
26d53979 | 1895 | again = ehci_state_fetchitd(ehci, async); |
94527ead GH |
1896 | break; |
1897 | ||
1898 | case EST_ADVANCEQUEUE: | |
0122f472 | 1899 | again = ehci_state_advqueue(q, async); |
94527ead GH |
1900 | break; |
1901 | ||
1902 | case EST_FETCHQTD: | |
0122f472 | 1903 | again = ehci_state_fetchqtd(q, async); |
94527ead GH |
1904 | break; |
1905 | ||
1906 | case EST_HORIZONTALQH: | |
0122f472 | 1907 | again = ehci_state_horizqh(q, async); |
94527ead GH |
1908 | break; |
1909 | ||
1910 | case EST_EXECUTE: | |
1911 | iter = 0; | |
0122f472 | 1912 | again = ehci_state_execute(q, async); |
94527ead GH |
1913 | break; |
1914 | ||
1915 | case EST_EXECUTING: | |
8ac6d699 | 1916 | assert(q != NULL); |
0122f472 | 1917 | again = ehci_state_executing(q, async); |
94527ead GH |
1918 | break; |
1919 | ||
1920 | case EST_WRITEBACK: | |
0122f472 | 1921 | again = ehci_state_writeback(q, async); |
94527ead GH |
1922 | break; |
1923 | ||
1924 | default: | |
1925 | fprintf(stderr, "Bad state!\n"); | |
1926 | again = -1; | |
8ac6d699 | 1927 | assert(0); |
94527ead GH |
1928 | break; |
1929 | } | |
1930 | ||
1931 | if (again < 0) { | |
1932 | fprintf(stderr, "processing error - resetting ehci HC\n"); | |
1933 | ehci_reset(ehci); | |
1934 | again = 0; | |
8ac6d699 | 1935 | assert(0); |
94527ead GH |
1936 | } |
1937 | } | |
1938 | while (again); | |
1939 | ||
1940 | ehci_commit_interrupt(ehci); | |
94527ead GH |
1941 | } |
1942 | ||
1943 | static void ehci_advance_async_state(EHCIState *ehci) | |
1944 | { | |
26d53979 | 1945 | int async = 1; |
94527ead | 1946 | |
26d53979 | 1947 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
1948 | case EST_INACTIVE: |
1949 | if (!(ehci->usbcmd & USBCMD_ASE)) { | |
1950 | break; | |
1951 | } | |
439a97cc | 1952 | ehci_set_usbsts(ehci, USBSTS_ASS); |
26d53979 | 1953 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
1954 | // No break, fall through to ACTIVE |
1955 | ||
1956 | case EST_ACTIVE: | |
1957 | if ( !(ehci->usbcmd & USBCMD_ASE)) { | |
439a97cc | 1958 | ehci_clear_usbsts(ehci, USBSTS_ASS); |
26d53979 | 1959 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
1960 | break; |
1961 | } | |
1962 | ||
1963 | /* If the doorbell is set, the guest wants to make a change to the | |
1964 | * schedule. The host controller needs to release cached data. | |
1965 | * (section 4.8.2) | |
1966 | */ | |
1967 | if (ehci->usbcmd & USBCMD_IAAD) { | |
1968 | DPRINTF("ASYNC: doorbell request acknowledged\n"); | |
1969 | ehci->usbcmd &= ~USBCMD_IAAD; | |
1970 | ehci_set_interrupt(ehci, USBSTS_IAA); | |
1971 | break; | |
1972 | } | |
1973 | ||
1974 | /* make sure guest has acknowledged */ | |
1975 | /* TO-DO: is this really needed? */ | |
1976 | if (ehci->usbsts & USBSTS_IAA) { | |
1977 | DPRINTF("IAA status bit still set.\n"); | |
1978 | break; | |
1979 | } | |
1980 | ||
94527ead GH |
1981 | /* check that address register has been set */ |
1982 | if (ehci->asynclistaddr == 0) { | |
1983 | break; | |
1984 | } | |
1985 | ||
26d53979 | 1986 | ehci_set_state(ehci, async, EST_WAITLISTHEAD); |
26d53979 | 1987 | ehci_advance_state(ehci, async); |
94527ead GH |
1988 | break; |
1989 | ||
1990 | default: | |
1991 | /* this should only be due to a developer mistake */ | |
1992 | fprintf(stderr, "ehci: Bad asynchronous state %d. " | |
1993 | "Resetting to active\n", ehci->astate); | |
0122f472 | 1994 | assert(0); |
94527ead GH |
1995 | } |
1996 | } | |
1997 | ||
1998 | static void ehci_advance_periodic_state(EHCIState *ehci) | |
1999 | { | |
2000 | uint32_t entry; | |
2001 | uint32_t list; | |
26d53979 | 2002 | int async = 0; |
94527ead GH |
2003 | |
2004 | // 4.6 | |
2005 | ||
26d53979 | 2006 | switch(ehci_get_state(ehci, async)) { |
94527ead GH |
2007 | case EST_INACTIVE: |
2008 | if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2009 | ehci_set_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2010 | ehci_set_state(ehci, async, EST_ACTIVE); |
94527ead GH |
2011 | // No break, fall through to ACTIVE |
2012 | } else | |
2013 | break; | |
2014 | ||
2015 | case EST_ACTIVE: | |
2016 | if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) { | |
439a97cc | 2017 | ehci_clear_usbsts(ehci, USBSTS_PSS); |
26d53979 | 2018 | ehci_set_state(ehci, async, EST_INACTIVE); |
94527ead GH |
2019 | break; |
2020 | } | |
2021 | ||
2022 | list = ehci->periodiclistbase & 0xfffff000; | |
2023 | /* check that register has been set */ | |
2024 | if (list == 0) { | |
2025 | break; | |
2026 | } | |
2027 | list |= ((ehci->frindex & 0x1ff8) >> 1); | |
2028 | ||
2029 | cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0); | |
2030 | entry = le32_to_cpu(entry); | |
2031 | ||
2032 | DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", | |
2033 | ehci->frindex / 8, list, entry); | |
0122f472 | 2034 | ehci_set_fetch_addr(ehci, async,entry); |
26d53979 GH |
2035 | ehci_set_state(ehci, async, EST_FETCHENTRY); |
2036 | ehci_advance_state(ehci, async); | |
94527ead GH |
2037 | break; |
2038 | ||
94527ead GH |
2039 | default: |
2040 | /* this should only be due to a developer mistake */ | |
2041 | fprintf(stderr, "ehci: Bad periodic state %d. " | |
2042 | "Resetting to active\n", ehci->pstate); | |
0122f472 | 2043 | assert(0); |
94527ead GH |
2044 | } |
2045 | } | |
2046 | ||
2047 | static void ehci_frame_timer(void *opaque) | |
2048 | { | |
2049 | EHCIState *ehci = opaque; | |
2050 | int64_t expire_time, t_now; | |
adddecb1 | 2051 | uint64_t ns_elapsed; |
94527ead | 2052 | int frames; |
94527ead GH |
2053 | int i; |
2054 | int skipped_frames = 0; | |
2055 | ||
94527ead | 2056 | t_now = qemu_get_clock_ns(vm_clock); |
16a2dee6 | 2057 | expire_time = t_now + (get_ticks_per_sec() / ehci->freq); |
94527ead | 2058 | |
adddecb1 GH |
2059 | ns_elapsed = t_now - ehci->last_run_ns; |
2060 | frames = ns_elapsed / FRAME_TIMER_NS; | |
94527ead GH |
2061 | |
2062 | for (i = 0; i < frames; i++) { | |
2063 | if ( !(ehci->usbsts & USBSTS_HALT)) { | |
2064 | if (ehci->isoch_pause <= 0) { | |
2065 | ehci->frindex += 8; | |
2066 | } | |
2067 | ||
2068 | if (ehci->frindex > 0x00001fff) { | |
2069 | ehci->frindex = 0; | |
2070 | ehci_set_interrupt(ehci, USBSTS_FLR); | |
2071 | } | |
2072 | ||
2073 | ehci->sofv = (ehci->frindex - 1) >> 3; | |
2074 | ehci->sofv &= 0x000003ff; | |
2075 | } | |
2076 | ||
16a2dee6 | 2077 | if (frames - i > ehci->maxframes) { |
94527ead GH |
2078 | skipped_frames++; |
2079 | } else { | |
d0539307 | 2080 | ehci_advance_periodic_state(ehci); |
94527ead GH |
2081 | } |
2082 | ||
adddecb1 | 2083 | ehci->last_run_ns += FRAME_TIMER_NS; |
94527ead GH |
2084 | } |
2085 | ||
2086 | #if 0 | |
2087 | if (skipped_frames) { | |
2088 | DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames); | |
2089 | } | |
2090 | #endif | |
2091 | ||
2092 | /* Async is not inside loop since it executes everything it can once | |
2093 | * called | |
2094 | */ | |
d0539307 | 2095 | ehci_advance_async_state(ehci); |
94527ead GH |
2096 | |
2097 | qemu_mod_timer(ehci->frame_timer, expire_time); | |
2098 | } | |
2099 | ||
2100 | static CPUReadMemoryFunc *ehci_readfn[3]={ | |
2101 | ehci_mem_readb, | |
2102 | ehci_mem_readw, | |
2103 | ehci_mem_readl | |
2104 | }; | |
2105 | ||
2106 | static CPUWriteMemoryFunc *ehci_writefn[3]={ | |
2107 | ehci_mem_writeb, | |
2108 | ehci_mem_writew, | |
2109 | ehci_mem_writel | |
2110 | }; | |
2111 | ||
2112 | static void ehci_map(PCIDevice *pci_dev, int region_num, | |
2113 | pcibus_t addr, pcibus_t size, int type) | |
2114 | { | |
2115 | EHCIState *s =(EHCIState *)pci_dev; | |
2116 | ||
2117 | DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n", | |
2118 | region_num, addr, size, s->mem); | |
2119 | s->mem_base = addr; | |
2120 | cpu_register_physical_memory(addr, size, s->mem); | |
2121 | } | |
2122 | ||
2123 | static int usb_ehci_initfn(PCIDevice *dev); | |
2124 | ||
2125 | static USBPortOps ehci_port_ops = { | |
2126 | .attach = ehci_attach, | |
2127 | .detach = ehci_detach, | |
4706ab6c | 2128 | .child_detach = ehci_child_detach, |
94527ead GH |
2129 | .complete = ehci_async_complete_packet, |
2130 | }; | |
2131 | ||
07771f6f | 2132 | static USBBusOps ehci_bus_ops = { |
07771f6f GH |
2133 | }; |
2134 | ||
94527ead GH |
2135 | static PCIDeviceInfo ehci_info = { |
2136 | .qdev.name = "usb-ehci", | |
2137 | .qdev.size = sizeof(EHCIState), | |
2138 | .init = usb_ehci_initfn, | |
9047c0b4 MT |
2139 | .vendor_id = PCI_VENDOR_ID_INTEL, |
2140 | .device_id = PCI_DEVICE_ID_INTEL_82801D, | |
2141 | .revision = 0x10, | |
2142 | .class_id = PCI_CLASS_SERIAL_USB, | |
16a2dee6 GH |
2143 | .qdev.props = (Property[]) { |
2144 | DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ), | |
2145 | DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), | |
2146 | DEFINE_PROP_END_OF_LIST(), | |
2147 | }, | |
94527ead GH |
2148 | }; |
2149 | ||
2150 | static int usb_ehci_initfn(PCIDevice *dev) | |
2151 | { | |
2152 | EHCIState *s = DO_UPCAST(EHCIState, dev, dev); | |
2153 | uint8_t *pci_conf = s->dev.config; | |
2154 | int i; | |
2155 | ||
94527ead | 2156 | pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); |
94527ead GH |
2157 | |
2158 | /* capabilities pointer */ | |
2159 | pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); | |
2160 | //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); | |
2161 | ||
2162 | pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3 | |
2163 | pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); | |
2164 | pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); | |
2165 | ||
2166 | // pci_conf[0x50] = 0x01; // power management caps | |
2167 | ||
4001f22f | 2168 | pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) |
94527ead GH |
2169 | pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) |
2170 | pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) | |
2171 | ||
2172 | pci_conf[0x64] = 0x00; | |
2173 | pci_conf[0x65] = 0x00; | |
2174 | pci_conf[0x66] = 0x00; | |
2175 | pci_conf[0x67] = 0x00; | |
2176 | pci_conf[0x68] = 0x01; | |
2177 | pci_conf[0x69] = 0x00; | |
2178 | pci_conf[0x6a] = 0x00; | |
2179 | pci_conf[0x6b] = 0x00; // USBLEGSUP | |
2180 | pci_conf[0x6c] = 0x00; | |
2181 | pci_conf[0x6d] = 0x00; | |
2182 | pci_conf[0x6e] = 0x00; | |
2183 | pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS | |
2184 | ||
2185 | // 2.2 host controller interface version | |
2186 | s->mmio[0x00] = (uint8_t) OPREGBASE; | |
2187 | s->mmio[0x01] = 0x00; | |
2188 | s->mmio[0x02] = 0x00; | |
2189 | s->mmio[0x03] = 0x01; // HC version | |
2190 | s->mmio[0x04] = NB_PORTS; // Number of downstream ports | |
2191 | s->mmio[0x05] = 0x00; // No companion ports at present | |
2192 | s->mmio[0x06] = 0x00; | |
2193 | s->mmio[0x07] = 0x00; | |
2194 | s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable | |
2195 | s->mmio[0x09] = 0x68; // EECP | |
2196 | s->mmio[0x0a] = 0x00; | |
2197 | s->mmio[0x0b] = 0x00; | |
2198 | ||
2199 | s->irq = s->dev.irq[3]; | |
2200 | ||
07771f6f | 2201 | usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); |
94527ead GH |
2202 | for(i = 0; i < NB_PORTS; i++) { |
2203 | usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, | |
2204 | USB_SPEED_MASK_HIGH); | |
94527ead GH |
2205 | s->ports[i].dev = 0; |
2206 | } | |
2207 | ||
2208 | s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s); | |
8ac6d699 | 2209 | QTAILQ_INIT(&s->queues); |
94527ead GH |
2210 | |
2211 | qemu_register_reset(ehci_reset, s); | |
2212 | ||
2213 | s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s, | |
2214 | DEVICE_LITTLE_ENDIAN); | |
2215 | ||
2216 | pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY, | |
2217 | ehci_map); | |
2218 | ||
2219 | fprintf(stderr, "*** EHCI support is under development ***\n"); | |
2220 | ||
2221 | return 0; | |
2222 | } | |
2223 | ||
2224 | static void ehci_register(void) | |
2225 | { | |
2226 | pci_qdev_register(&ehci_info); | |
2227 | } | |
2228 | device_init(ehci_register); | |
2229 | ||
2230 | /* | |
2231 | * vim: expandtab ts=4 | |
2232 | */ |