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usb: Add a usb_fill_port helper function
[qemu.git] / hw / usb-musb.c
CommitLineData
942ac052
AZ		 1/*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
942ac052
AZ		 20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23#include "qemu-common.h"
24#include "qemu-timer.h"
25#include "usb.h"
26#include "irq.h"
384dce1e 27#include "hw.h"
942ac052
AZ		 28
29/* Common USB registers */
30#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31#define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34#define MUSB_HDRC_INTRRX 0x04
35#define MUSB_HDRC_INTRTXE 0x06
36#define MUSB_HDRC_INTRRXE 0x08
37#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43/* Per-EP registers in indexed mode */
44#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46/* EP FIFOs */
47#define MUSB_HDRC_FIFO 0x20
48
49/* Additional Control Registers */
50#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52/* These are indexed */
53#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58/* Some more registers */
59#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62/* Added in HDRC 1.9(?) & MHDRC 1.4 */
63/* ULPI pass-through */
64#define MUSB_HDRC_ULPI_VBUSCTL 0x70
65#define MUSB_HDRC_ULPI_REGDATA 0x74
66#define MUSB_HDRC_ULPI_REGADDR 0x75
67#define MUSB_HDRC_ULPI_REGCTL 0x76
68
69/* Extended config & PHY control */
70#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78/* Per-EP BUSCTL registers */
79#define MUSB_HDRC_BUSCTL 0x80
80
81/* Per-EP registers in flat mode */
82#define MUSB_HDRC_EP 0x100
83
84/* offsets to registers in flat model */
85#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101/* "Bus control" registers */
102#define MUSB_HDRC_TXFUNCADDR 0x00
103#define MUSB_HDRC_TXHUBADDR 0x02
104#define MUSB_HDRC_TXHUBPORT 0x03
105
106#define MUSB_HDRC_RXFUNCADDR 0x04
107#define MUSB_HDRC_RXHUBADDR 0x06
108#define MUSB_HDRC_RXHUBPORT 0x07
109
110/*
111 * MUSBHDRC Register bit masks
112 */
113
114/* POWER */
115#define MGC_M_POWER_ISOUPDATE 0x80
116#define MGC_M_POWER_SOFTCONN 0x40
117#define MGC_M_POWER_HSENAB 0x20
118#define MGC_M_POWER_HSMODE 0x10
119#define MGC_M_POWER_RESET 0x08
120#define MGC_M_POWER_RESUME 0x04
121#define MGC_M_POWER_SUSPENDM 0x02
122#define MGC_M_POWER_ENSUSPEND 0x01
123
124/* INTRUSB */
125#define MGC_M_INTR_SUSPEND 0x01
126#define MGC_M_INTR_RESUME 0x02
127#define MGC_M_INTR_RESET 0x04
128#define MGC_M_INTR_BABBLE 0x04
129#define MGC_M_INTR_SOF 0x08
130#define MGC_M_INTR_CONNECT 0x10
131#define MGC_M_INTR_DISCONNECT 0x20
132#define MGC_M_INTR_SESSREQ 0x40
133#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136/* DEVCTL */
137#define MGC_M_DEVCTL_BDEVICE 0x80
138#define MGC_M_DEVCTL_FSDEV 0x40
139#define MGC_M_DEVCTL_LSDEV 0x20
140#define MGC_M_DEVCTL_VBUS 0x18
141#define MGC_S_DEVCTL_VBUS 3
142#define MGC_M_DEVCTL_HM 0x04
143#define MGC_M_DEVCTL_HR 0x02
144#define MGC_M_DEVCTL_SESSION 0x01
145
146/* TESTMODE */
147#define MGC_M_TEST_FORCE_HOST 0x80
148#define MGC_M_TEST_FIFO_ACCESS 0x40
149#define MGC_M_TEST_FORCE_FS 0x20
150#define MGC_M_TEST_FORCE_HS 0x10
151#define MGC_M_TEST_PACKET 0x08
152#define MGC_M_TEST_K 0x04
153#define MGC_M_TEST_J 0x02
154#define MGC_M_TEST_SE0_NAK 0x01
155
156/* CSR0 */
157#define MGC_M_CSR0_FLUSHFIFO 0x0100
158#define MGC_M_CSR0_TXPKTRDY 0x0002
159#define MGC_M_CSR0_RXPKTRDY 0x0001
160
161/* CSR0 in Peripheral mode */
162#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164#define MGC_M_CSR0_P_SENDSTALL 0x0020
165#define MGC_M_CSR0_P_SETUPEND 0x0010
166#define MGC_M_CSR0_P_DATAEND 0x0008
167#define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169/* CSR0 in Host mode */
170#define MGC_M_CSR0_H_NO_PING 0x0800
171#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174#define MGC_M_CSR0_H_STATUSPKT 0x0040
175#define MGC_M_CSR0_H_REQPKT 0x0020
176#define MGC_M_CSR0_H_ERROR 0x0010
177#define MGC_M_CSR0_H_SETUPPKT 0x0008
178#define MGC_M_CSR0_H_RXSTALL 0x0004
179
180/* CONFIGDATA */
181#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190/* TXCSR in Peripheral and Host mode */
191#define MGC_M_TXCSR_AUTOSET 0x8000
192#define MGC_M_TXCSR_ISO 0x4000
193#define MGC_M_TXCSR_MODE 0x2000
194#define MGC_M_TXCSR_DMAENAB 0x1000
195#define MGC_M_TXCSR_FRCDATATOG 0x0800
196#define MGC_M_TXCSR_DMAMODE 0x0400
197#define MGC_M_TXCSR_CLRDATATOG 0x0040
198#define MGC_M_TXCSR_FLUSHFIFO 0x0008
199#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200#define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202/* TXCSR in Peripheral mode */
203#define MGC_M_TXCSR_P_INCOMPTX 0x0080
204#define MGC_M_TXCSR_P_SENTSTALL 0x0020
205#define MGC_M_TXCSR_P_SENDSTALL 0x0010
206#define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208/* TXCSR in Host mode */
209#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212#define MGC_M_TXCSR_H_RXSTALL 0x0020
213#define MGC_M_TXCSR_H_ERROR 0x0004
214
215/* RXCSR in Peripheral and Host mode */
216#define MGC_M_RXCSR_AUTOCLEAR 0x8000
217#define MGC_M_RXCSR_DMAENAB 0x2000
218#define MGC_M_RXCSR_DISNYET 0x1000
219#define MGC_M_RXCSR_DMAMODE 0x0800
220#define MGC_M_RXCSR_INCOMPRX 0x0100
221#define MGC_M_RXCSR_CLRDATATOG 0x0080
222#define MGC_M_RXCSR_FLUSHFIFO 0x0010
223#define MGC_M_RXCSR_DATAERROR 0x0008
224#define MGC_M_RXCSR_FIFOFULL 0x0002
225#define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227/* RXCSR in Peripheral mode */
228#define MGC_M_RXCSR_P_ISO 0x4000
229#define MGC_M_RXCSR_P_SENTSTALL 0x0040
230#define MGC_M_RXCSR_P_SENDSTALL 0x0020
231#define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233/* RXCSR in Host mode */
234#define MGC_M_RXCSR_H_AUTOREQ 0x4000
235#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237#define MGC_M_RXCSR_H_RXSTALL 0x0040
238#define MGC_M_RXCSR_H_REQPKT 0x0020
239#define MGC_M_RXCSR_H_ERROR 0x0004
240
241/* HUBADDR */
242#define MGC_M_HUBADDR_MULTI_TT 0x80
243
244/* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250#define MGC_M_ULPI_REGCTL_REG 0x01
251
384dce1e
RV		 252/* #define MUSB_DEBUG */
253
254#ifdef MUSB_DEBUG
255#define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257#else
258#define TRACE(...)
259#endif
260
261
618c169b
GH		 262static void musb_attach(USBPort *port);
263static void musb_detach(USBPort *port);
13a9a0d3 264static void musb_schedule_cb(USBDevice *dev, USBPacket *p);
07771f6f 265static void musb_device_destroy(USBBus *bus, USBDevice *dev);
942ac052 266
0d86d2be
GH		 267static USBPortOps musb_port_ops = {
268 .attach = musb_attach,
618c169b 269 .detach = musb_detach,
13a9a0d3 270 .complete = musb_schedule_cb,
0d86d2be
GH		 271};
272
07771f6f
GH		 273static USBBusOps musb_bus_ops = {
274 .device_destroy = musb_device_destroy,
275};
276
5dc1672b
GH		 277typedef struct MUSBPacket MUSBPacket;
278typedef struct MUSBEndPoint MUSBEndPoint;
279
280struct MUSBPacket {
281 USBPacket p;
282 MUSBEndPoint *ep;
283 int dir;
284};
285
286struct MUSBEndPoint {
bc24a225
PB		 287 uint16_t faddr[2];
288 uint8_t haddr[2];
289 uint8_t hport[2];
290 uint16_t csr[2];
291 uint16_t maxp[2];
292 uint16_t rxcount;
293 uint8_t type[2];
294 uint8_t interval[2];
295 uint8_t config;
296 uint8_t fifosize;
297 int timeout[2]; /* Always in microframes */
298
384dce1e 299 uint8_t *buf[2];
bc24a225
PB		 300 int fifolen[2];
301 int fifostart[2];
302 int fifoaddr[2];
5dc1672b 303 MUSBPacket packey[2];
bc24a225
PB		 304 int status[2];
305 int ext_size[2];
306
307 /* For callbacks' use */
308 int epnum;
309 int interrupt[2];
310 MUSBState *musb;
311 USBCallback *delayed_cb[2];
312 QEMUTimer *intv_timer[2];
5dc1672b 313};
bc24a225
PB		 314
315struct MUSBState {
942ac052 316 qemu_irq *irqs;
b2317837 317 USBBus bus;
942ac052
AZ		 318 USBPort port;
319
320 int idx;
321 uint8_t devctl;
322 uint8_t power;
323 uint8_t faddr;
324
325 uint8_t intr;
326 uint8_t mask;
327 uint16_t tx_intr;
328 uint16_t tx_mask;
329 uint16_t rx_intr;
330 uint16_t rx_mask;
331
332 int setup_len;
333 int session;
334
384dce1e 335 uint8_t buf[0x8000];
942ac052 336
942ac052
AZ		 337 /* Duplicating the world since 2008!... probably we should have 32
338 * logical, single endpoints instead. */
bc24a225 339 MUSBEndPoint ep[16];
5dc1672b
GH		 340};
341
342struct MUSBState *musb_init(qemu_irq *irqs)
942ac052 343{
bc24a225 344 MUSBState *s = qemu_mallocz(sizeof(*s));
942ac052
AZ		 345 int i;
346
347 s->irqs = irqs;
348
349 s->faddr = 0x00;
350 s->power = MGC_M_POWER_HSENAB;
351 s->tx_intr = 0x0000;
352 s->rx_intr = 0x0000;
353 s->tx_mask = 0xffff;
354 s->rx_mask = 0xffff;
355 s->intr = 0x00;
356 s->mask = 0x06;
357 s->idx = 0;
358
359 /* TODO: _DW */
360 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
361 for (i = 0; i < 16; i ++) {
362 s->ep[i].fifosize = 64;
363 s->ep[i].maxp[0] = 0x40;
364 s->ep[i].maxp[1] = 0x40;
365 s->ep[i].musb = s;
366 s->ep[i].epnum = i;
367 }
368
07771f6f 369 usb_bus_new(&s->bus, &musb_bus_ops, NULL /* FIXME */);
ace1318b 370 usb_register_port(&s->bus, &s->port, s, 0, &musb_port_ops,
843d4e0c 371 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
c7a2196a 372 usb_port_location(&s->port, NULL, 1);
942ac052
AZ		 373
374 return s;
375}
376
bc24a225 377static void musb_vbus_set(MUSBState *s, int level)
942ac052
AZ		 378{
379 if (level)
380 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
381 else
382 s->devctl &= ~MGC_M_DEVCTL_VBUS;
383
384 qemu_set_irq(s->irqs[musb_set_vbus], level);
385}
386
bc24a225 387static void musb_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 388{
389 if (!level) {
390 s->intr &= ~(1 << line);
391 qemu_irq_lower(s->irqs[line]);
392 } else if (s->mask & (1 << line)) {
393 s->intr |= 1 << line;
394 qemu_irq_raise(s->irqs[line]);
395 }
396}
397
bc24a225 398static void musb_tx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 399{
400 if (!level) {
401 s->tx_intr &= ~(1 << line);
402 if (!s->tx_intr)
403 qemu_irq_lower(s->irqs[musb_irq_tx]);
404 } else if (s->tx_mask & (1 << line)) {
405 s->tx_intr |= 1 << line;
406 qemu_irq_raise(s->irqs[musb_irq_tx]);
407 }
408}
409
bc24a225 410static void musb_rx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 411{
412 if (line) {
413 if (!level) {
414 s->rx_intr &= ~(1 << line);
415 if (!s->rx_intr)
416 qemu_irq_lower(s->irqs[musb_irq_rx]);
417 } else if (s->rx_mask & (1 << line)) {
418 s->rx_intr |= 1 << line;
419 qemu_irq_raise(s->irqs[musb_irq_rx]);
420 }
421 } else
422 musb_tx_intr_set(s, line, level);
423}
424
bc24a225 425uint32_t musb_core_intr_get(MUSBState *s)
942ac052
AZ		 426{
427 return (s->rx_intr << 15) | s->tx_intr;
428}
429
bc24a225 430void musb_core_intr_clear(MUSBState *s, uint32_t mask)
942ac052
AZ		 431{
432 if (s->rx_intr) {
433 s->rx_intr &= mask >> 15;
434 if (!s->rx_intr)
435 qemu_irq_lower(s->irqs[musb_irq_rx]);
436 }
437
438 if (s->tx_intr) {
439 s->tx_intr &= mask & 0xffff;
440 if (!s->tx_intr)
441 qemu_irq_lower(s->irqs[musb_irq_tx]);
442 }
443}
444
bc24a225 445void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
942ac052
AZ		 446{
447 s->ep[epnum].ext_size[!is_tx] = size;
448 s->ep[epnum].fifostart[0] = 0;
449 s->ep[epnum].fifostart[1] = 0;
450 s->ep[epnum].fifolen[0] = 0;
451 s->ep[epnum].fifolen[1] = 0;
452}
453
bc24a225 454static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
942ac052
AZ		 455{
456 int detect_prev = prev_dev && prev_sess;
457 int detect = !!s->port.dev && s->session;
458
459 if (detect && !detect_prev) {
460 /* Let's skip the ID pin sense and VBUS sense formalities and
461 * and signal a successful SRP directly. This should work at least
462 * for the Linux driver stack. */
463 musb_intr_set(s, musb_irq_connect, 1);
464
465 if (s->port.dev->speed == USB_SPEED_LOW) {
466 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
467 s->devctl |= MGC_M_DEVCTL_LSDEV;
468 } else {
469 s->devctl |= MGC_M_DEVCTL_FSDEV;
470 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
471 }
472
473 /* A-mode? */
474 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
475
476 /* Host-mode bit? */
477 s->devctl |= MGC_M_DEVCTL_HM;
478#if 1
479 musb_vbus_set(s, 1);
480#endif
481 } else if (!detect && detect_prev) {
482#if 1
483 musb_vbus_set(s, 0);
484#endif
485 }
486}
487
488/* Attach or detach a device on our only port. */
618c169b 489static void musb_attach(USBPort *port)
942ac052 490{
bc24a225 491 MUSBState *s = (MUSBState *) port->opaque;
942ac052 492
618c169b
GH		 493 musb_intr_set(s, musb_irq_vbus_request, 1);
494 musb_session_update(s, 0, s->session);
495}
942ac052 496
618c169b
GH		 497static void musb_detach(USBPort *port)
498{
499 MUSBState *s = (MUSBState *) port->opaque;
942ac052 500
618c169b
GH		 501 musb_intr_set(s, musb_irq_disconnect, 1);
502 musb_session_update(s, 1, s->session);
942ac052
AZ		 503}
504
b3e5759e 505static void musb_cb_tick0(void *opaque)
942ac052 506{
bc24a225 507 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 508
5dc1672b 509 ep->delayed_cb[0](&ep->packey[0].p, opaque);
942ac052
AZ		 510}
511
b3e5759e 512static void musb_cb_tick1(void *opaque)
942ac052 513{
bc24a225 514 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 515
5dc1672b 516 ep->delayed_cb[1](&ep->packey[1].p, opaque);
942ac052
AZ		 517}
518
519#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
520
b3e5759e 521static void musb_schedule_cb(USBDevice *dev, USBPacket *packey)
942ac052 522{
13a9a0d3
GH		 523 MUSBPacket *p = container_of(packey, MUSBPacket, p);
524 MUSBEndPoint *ep = p->ep;
525 int dir = p->dir;
942ac052
AZ		 526 int timeout = 0;
527
528 if (ep->status[dir] == USB_RET_NAK)
529 timeout = ep->timeout[dir];
530 else if (ep->interrupt[dir])
531 timeout = 8;
532 else
13a9a0d3 533 return musb_cb_tick(ep);
942ac052
AZ		 534
535 if (!ep->intv_timer[dir])
13a9a0d3 536 ep->intv_timer[dir] = qemu_new_timer_ns(vm_clock, musb_cb_tick, ep);
942ac052 537
74475455 538 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock_ns(vm_clock) +
6ee093c9 539 muldiv64(timeout, get_ticks_per_sec(), 8000));
942ac052
AZ		 540}
541
942ac052
AZ		 542static int musb_timeout(int ttype, int speed, int val)
543{
544#if 1
545 return val << 3;
546#endif
547
548 switch (ttype) {
549 case USB_ENDPOINT_XFER_CONTROL:
550 if (val < 2)
551 return 0;
552 else if (speed == USB_SPEED_HIGH)
553 return 1 << (val - 1);
554 else
555 return 8 << (val - 1);
556
557 case USB_ENDPOINT_XFER_INT:
558 if (speed == USB_SPEED_HIGH)
559 if (val < 2)
560 return 0;
561 else
562 return 1 << (val - 1);
563 else
564 return val << 3;
565
566 case USB_ENDPOINT_XFER_BULK:
567 case USB_ENDPOINT_XFER_ISOC:
568 if (val < 2)
569 return 0;
570 else if (speed == USB_SPEED_HIGH)
571 return 1 << (val - 1);
572 else
573 return 8 << (val - 1);
574 /* TODO: what with low-speed Bulk and Isochronous? */
575 }
576
2ac71179 577 hw_error("bad interval\n");
942ac052
AZ		 578}
579
b3e5759e 580static void musb_packet(MUSBState *s, MUSBEndPoint *ep,
942ac052
AZ		 581 int epnum, int pid, int len, USBCallback cb, int dir)
582{
583 int ret;
584 int idx = epnum && dir;
585 int ttype;
586
587 /* ep->type[0,1] contains:
588 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
589 * in bits 5:4 the transfer type (BULK / INT)
590 * in bits 3:0 the EP num
591 */
592 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
593
594 ep->timeout[dir] = musb_timeout(ttype,
595 ep->type[idx] >> 6, ep->interval[idx]);
596 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
597 ep->delayed_cb[dir] = cb;
942ac052 598
5dc1672b 599 ep->packey[dir].p.pid = pid;
942ac052 600 /* A wild guess on the FADDR semantics... */
5dc1672b
GH		 601 ep->packey[dir].p.devaddr = ep->faddr[idx];
602 ep->packey[dir].p.devep = ep->type[idx] & 0xf;
603 ep->packey[dir].p.data = (void *) ep->buf[idx];
604 ep->packey[dir].p.len = len;
5dc1672b
GH		 605 ep->packey[dir].ep = ep;
606 ep->packey[dir].dir = dir;
942ac052
AZ		 607
608 if (s->port.dev)
53aa8c0e 609 ret = usb_handle_packet(s->port.dev, &ep->packey[dir].p);
942ac052
AZ		 610 else
611 ret = USB_RET_NODEV;
612
613 if (ret == USB_RET_ASYNC) {
614 ep->status[dir] = len;
615 return;
616 }
617
618 ep->status[dir] = ret;
000eb4fa 619 musb_schedule_cb(s->port.dev, &ep->packey[dir].p);
942ac052
AZ		 620}
621
622static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
623{
624 /* Unfortunately we can't use packey->devep because that's the remote
625 * endpoint number and may be different than our local. */
bc24a225 626 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 627 int epnum = ep->epnum;
bc24a225 628 MUSBState *s = ep->musb;
942ac052
AZ		 629
630 ep->fifostart[0] = 0;
631 ep->fifolen[0] = 0;
632#ifdef CLEAR_NAK
633 if (ep->status[0] != USB_RET_NAK) {
634#endif
635 if (epnum)
636 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
637 else
638 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
639#ifdef CLEAR_NAK
640 }
641#endif
642
643 /* Clear all of the error bits first */
644 if (epnum)
645 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
646 MGC_M_TXCSR_H_NAKTIMEOUT);
647 else
648 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
649 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
650
651 if (ep->status[0] == USB_RET_STALL) {
652 /* Command not supported by target! */
653 ep->status[0] = 0;
654
655 if (epnum)
656 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
657 else
658 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
659 }
660
661 if (ep->status[0] == USB_RET_NAK) {
662 ep->status[0] = 0;
663
664 /* NAK timeouts are only generated in Bulk transfers and
665 * Data-errors in Isochronous. */
666 if (ep->interrupt[0]) {
667 return;
668 }
669
670 if (epnum)
671 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
672 else
673 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
674 }
675
676 if (ep->status[0] < 0) {
677 if (ep->status[0] == USB_RET_BABBLE)
678 musb_intr_set(s, musb_irq_rst_babble, 1);
679
680 /* Pretend we've tried three times already and failed (in
681 * case of USB_TOKEN_SETUP). */
682 if (epnum)
683 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
684 else
685 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
686
687 musb_tx_intr_set(s, epnum, 1);
688 return;
689 }
690 /* TODO: check len for over/underruns of an OUT packet? */
691
692#ifdef SETUPLEN_HACK
693 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
694 s->setup_len = ep->packey[0].data[6];
695#endif
696
697 /* In DMA mode: if no error, assert DMA request for this EP,
698 * and skip the interrupt. */
699 musb_tx_intr_set(s, epnum, 1);
700}
701
702static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
703{
704 /* Unfortunately we can't use packey->devep because that's the remote
705 * endpoint number and may be different than our local. */
bc24a225 706 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 707 int epnum = ep->epnum;
bc24a225 708 MUSBState *s = ep->musb;
942ac052
AZ		 709
710 ep->fifostart[1] = 0;
711 ep->fifolen[1] = 0;
712
713#ifdef CLEAR_NAK
714 if (ep->status[1] != USB_RET_NAK) {
715#endif
716 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
717 if (!epnum)
718 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
719#ifdef CLEAR_NAK
720 }
721#endif
722
723 /* Clear all of the imaginable error bits first */
724 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
725 MGC_M_RXCSR_DATAERROR);
726 if (!epnum)
727 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
728 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
729
730 if (ep->status[1] == USB_RET_STALL) {
731 ep->status[1] = 0;
732 packey->len = 0;
733
734 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
735 if (!epnum)
736 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
737 }
738
739 if (ep->status[1] == USB_RET_NAK) {
740 ep->status[1] = 0;
741
742 /* NAK timeouts are only generated in Bulk transfers and
743 * Data-errors in Isochronous. */
744 if (ep->interrupt[1])
745 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
746 packey->len, musb_rx_packet_complete, 1);
747
748 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
749 if (!epnum)
750 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
751 }
752
753 if (ep->status[1] < 0) {
754 if (ep->status[1] == USB_RET_BABBLE) {
755 musb_intr_set(s, musb_irq_rst_babble, 1);
756 return;
757 }
758
759 /* Pretend we've tried three times already and failed (in
760 * case of a control transfer). */
761 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
762 if (!epnum)
763 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
764
765 musb_rx_intr_set(s, epnum, 1);
766 return;
767 }
768 /* TODO: check len for over/underruns of an OUT packet? */
769 /* TODO: perhaps make use of e->ext_size[1] here. */
770
771 packey->len = ep->status[1];
772
773 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
774 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
775 if (!epnum)
776 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
777
778 ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
779 /* In DMA mode: assert DMA request for this EP */
780 }
781
782 /* Only if DMA has not been asserted */
783 musb_rx_intr_set(s, epnum, 1);
784}
785
07771f6f
GH		 786static void musb_device_destroy(USBBus *bus, USBDevice *dev)
787{
788 MUSBState *s = container_of(bus, MUSBState, bus);
789 int ep, dir;
790
791 for (ep = 0; ep < 16; ep++) {
792 for (dir = 0; dir < 2; dir++) {
793 if (s->ep[ep].packey[dir].p.owner != dev) {
794 continue;
795 }
796 usb_cancel_packet(&s->ep[ep].packey[dir].p);
797 /* status updates needed here? */
798 }
799 }
800}
801
bc24a225 802static void musb_tx_rdy(MUSBState *s, int epnum)
942ac052 803{
bc24a225 804 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 805 int pid;
806 int total, valid = 0;
384dce1e 807 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
942ac052
AZ		 808 ep->fifostart[0] += ep->fifolen[0];
809 ep->fifolen[0] = 0;
810
811 /* XXX: how's the total size of the packet retrieved exactly in
812 * the generic case? */
813 total = ep->maxp[0] & 0x3ff;
814
815 if (ep->ext_size[0]) {
816 total = ep->ext_size[0];
817 ep->ext_size[0] = 0;
818 valid = 1;
819 }
820
821 /* If the packet is not fully ready yet, wait for a next segment. */
384dce1e 822 if (epnum && (ep->fifostart[0]) < total)
942ac052
AZ		 823 return;
824
825 if (!valid)
384dce1e 826 total = ep->fifostart[0];
942ac052
AZ		 827
828 pid = USB_TOKEN_OUT;
829 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
830 pid = USB_TOKEN_SETUP;
384dce1e
RV		 831 if (total != 8) {
832 TRACE("illegal SETUPPKT length of %i bytes", total);
833 }
942ac052
AZ		 834 /* Controller should retry SETUP packets three times on errors
835 * but it doesn't make sense for us to do that. */
836 }
837
838 return musb_packet(s, ep, epnum, pid,
839 total, musb_tx_packet_complete, 0);
840}
841
bc24a225 842static void musb_rx_req(MUSBState *s, int epnum)
942ac052 843{
bc24a225 844 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 845 int total;
846
847 /* If we already have a packet, which didn't fit into the
848 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
5dc1672b 849 if (ep->packey[1].p.pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
384dce1e 850 (ep->fifostart[1]) + ep->rxcount <
5dc1672b 851 ep->packey[1].p.len) {
384dce1e
RV		 852 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
853 ep->fifostart[1] += ep->rxcount;
942ac052
AZ		 854 ep->fifolen[1] = 0;
855
5dc1672b 856 ep->rxcount = MIN(ep->packey[0].p.len - (ep->fifostart[1]),
942ac052
AZ		 857 ep->maxp[1]);
858
859 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
860 if (!epnum)
861 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
862
863 /* Clear all of the error bits first */
864 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
865 MGC_M_RXCSR_DATAERROR);
866 if (!epnum)
867 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
868 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
869
870 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
871 if (!epnum)
872 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
873 musb_rx_intr_set(s, epnum, 1);
874 return;
875 }
876
877 /* The driver sets maxp[1] to 64 or less because it knows the hardware
878 * FIFO is this deep. Bigger packets get split in
879 * usb_generic_handle_packet but we can also do the splitting locally
880 * for performance. It turns out we can also have a bigger FIFO and
881 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
882 * OK with single packets of even 32KB and we avoid splitting, however
883 * usb_msd.c sometimes sends a packet bigger than what Linux expects
884 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
885 * hides this overrun from Linux. Up to 4096 everything is fine
886 * though. Currently this is disabled.
887 *
888 * XXX: mind ep->fifosize. */
889 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
890
891#ifdef SETUPLEN_HACK
892 /* Why should *we* do that instead of Linux? */
893 if (!epnum) {
5dc1672b 894 if (ep->packey[0].p.devaddr == 2) {
942ac052 895 total = MIN(s->setup_len, 8);
5dc1672b 896 } else {
942ac052 897 total = MIN(s->setup_len, 64);
5dc1672b 898 }
942ac052
AZ		 899 s->setup_len -= total;
900 }
901#endif
902
903 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
904 total, musb_rx_packet_complete, 1);
905}
906
384dce1e
RV		 907static uint8_t musb_read_fifo(MUSBEndPoint *ep)
908{
909 uint8_t value;
910 if (ep->fifolen[1] >= 64) {
911 /* We have a FIFO underrun */
912 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
913 return 0x00000000;
914 }
915 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
916 * (if AUTOREQ is set) */
917
918 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
919 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
920 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
921 return value;
922}
923
924static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
925{
926 TRACE("EP%d = %02x", ep->epnum, value);
927 if (ep->fifolen[0] >= 64) {
928 /* We have a FIFO overrun */
929 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
930 return;
931 }
932
933 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
934 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
935}
936
bc24a225 937static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
942ac052
AZ		 938{
939 if (ep->intv_timer[dir])
940 qemu_del_timer(ep->intv_timer[dir]);
941}
942
943/* Bus control */
944static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
945{
bc24a225 946 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 947
948 switch (addr) {
949 /* For USB2.0 HS hubs only */
950 case MUSB_HDRC_TXHUBADDR:
951 return s->ep[ep].haddr[0];
952 case MUSB_HDRC_TXHUBPORT:
953 return s->ep[ep].hport[0];
954 case MUSB_HDRC_RXHUBADDR:
955 return s->ep[ep].haddr[1];
956 case MUSB_HDRC_RXHUBPORT:
957 return s->ep[ep].hport[1];
958
959 default:
384dce1e 960 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 961 return 0x00;
962 };
963}
964
965static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
966{
bc24a225 967 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 968
969 switch (addr) {
384dce1e
RV		 970 case MUSB_HDRC_TXFUNCADDR:
971 s->ep[ep].faddr[0] = value;
972 break;
973 case MUSB_HDRC_RXFUNCADDR:
974 s->ep[ep].faddr[1] = value;
975 break;
942ac052
AZ		 976 case MUSB_HDRC_TXHUBADDR:
977 s->ep[ep].haddr[0] = value;
978 break;
979 case MUSB_HDRC_TXHUBPORT:
980 s->ep[ep].hport[0] = value;
981 break;
982 case MUSB_HDRC_RXHUBADDR:
983 s->ep[ep].haddr[1] = value;
984 break;
985 case MUSB_HDRC_RXHUBPORT:
986 s->ep[ep].hport[1] = value;
987 break;
988
989 default:
384dce1e
RV		 990 TRACE("unknown register 0x%02x", addr);
991 break;
942ac052
AZ		 992 };
993}
994
995static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
996{
bc24a225 997 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 998
999 switch (addr) {
1000 case MUSB_HDRC_TXFUNCADDR:
1001 return s->ep[ep].faddr[0];
1002 case MUSB_HDRC_RXFUNCADDR:
1003 return s->ep[ep].faddr[1];
1004
1005 default:
1006 return musb_busctl_readb(s, ep, addr) |
1007 (musb_busctl_readb(s, ep, addr | 1) << 8);
1008 };
1009}
1010
1011static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
1012{
bc24a225 1013 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1014
1015 switch (addr) {
1016 case MUSB_HDRC_TXFUNCADDR:
1017 s->ep[ep].faddr[0] = value;
1018 break;
1019 case MUSB_HDRC_RXFUNCADDR:
1020 s->ep[ep].faddr[1] = value;
1021 break;
1022
1023 default:
1024 musb_busctl_writeb(s, ep, addr, value & 0xff);
1025 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
1026 };
1027}
1028
1029/* Endpoint control */
1030static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1031{
bc24a225 1032 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1033
1034 switch (addr) {
1035 case MUSB_HDRC_TXTYPE:
1036 return s->ep[ep].type[0];
1037 case MUSB_HDRC_TXINTERVAL:
1038 return s->ep[ep].interval[0];
1039 case MUSB_HDRC_RXTYPE:
1040 return s->ep[ep].type[1];
1041 case MUSB_HDRC_RXINTERVAL:
1042 return s->ep[ep].interval[1];
1043 case (MUSB_HDRC_FIFOSIZE & ~1):
1044 return 0x00;
1045 case MUSB_HDRC_FIFOSIZE:
1046 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
384dce1e
RV		 1047 case MUSB_HDRC_RXCOUNT:
1048 return s->ep[ep].rxcount;
942ac052
AZ		 1049
1050 default:
384dce1e 1051 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 1052 return 0x00;
1053 };
1054}
1055
1056static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1057{
bc24a225 1058 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1059
1060 switch (addr) {
1061 case MUSB_HDRC_TXTYPE:
1062 s->ep[ep].type[0] = value;
1063 break;
1064 case MUSB_HDRC_TXINTERVAL:
1065 s->ep[ep].interval[0] = value;
1066 musb_ep_frame_cancel(&s->ep[ep], 0);
1067 break;
1068 case MUSB_HDRC_RXTYPE:
1069 s->ep[ep].type[1] = value;
1070 break;
1071 case MUSB_HDRC_RXINTERVAL:
1072 s->ep[ep].interval[1] = value;
1073 musb_ep_frame_cancel(&s->ep[ep], 1);
1074 break;
1075 case (MUSB_HDRC_FIFOSIZE & ~1):
1076 break;
1077 case MUSB_HDRC_FIFOSIZE:
384dce1e 1078 TRACE("somebody messes with fifosize (now %i bytes)", value);
942ac052
AZ		 1079 s->ep[ep].fifosize = value;
1080 break;
942ac052 1081 default:
384dce1e
RV		 1082 TRACE("unknown register 0x%02x", addr);
1083 break;
942ac052
AZ		 1084 };
1085}
1086
1087static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1088{
bc24a225 1089 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1090 uint16_t ret;
1091
1092 switch (addr) {
1093 case MUSB_HDRC_TXMAXP:
1094 return s->ep[ep].maxp[0];
1095 case MUSB_HDRC_TXCSR:
1096 return s->ep[ep].csr[0];
1097 case MUSB_HDRC_RXMAXP:
1098 return s->ep[ep].maxp[1];
1099 case MUSB_HDRC_RXCSR:
1100 ret = s->ep[ep].csr[1];
1101
1102 /* TODO: This and other bits probably depend on
1103 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1104 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1105 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1106
1107 return ret;
1108 case MUSB_HDRC_RXCOUNT:
1109 return s->ep[ep].rxcount;
1110
1111 default:
1112 return musb_ep_readb(s, ep, addr) |
1113 (musb_ep_readb(s, ep, addr | 1) << 8);
1114 };
1115}
1116
1117static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1118{
bc24a225 1119 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1120
1121 switch (addr) {
1122 case MUSB_HDRC_TXMAXP:
1123 s->ep[ep].maxp[0] = value;
1124 break;
1125 case MUSB_HDRC_TXCSR:
1126 if (ep) {
1127 s->ep[ep].csr[0] &= value & 0xa6;
1128 s->ep[ep].csr[0] |= value & 0xff59;
1129 } else {
1130 s->ep[ep].csr[0] &= value & 0x85;
1131 s->ep[ep].csr[0] |= value & 0xf7a;
1132 }
1133
1134 musb_ep_frame_cancel(&s->ep[ep], 0);
1135
1136 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1137 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1138 s->ep[ep].fifolen[0] = 0;
1139 s->ep[ep].fifostart[0] = 0;
1140 if (ep)
1141 s->ep[ep].csr[0] &=
1142 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1143 else
1144 s->ep[ep].csr[0] &=
1145 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1146 }
1147 if (
1148 (ep &&
1149#ifdef CLEAR_NAK
1150 (value & MGC_M_TXCSR_TXPKTRDY) &&
1151 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1152#else
1153 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1154#endif
1155 (!ep &&
1156#ifdef CLEAR_NAK
1157 (value & MGC_M_CSR0_TXPKTRDY) &&
1158 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1159#else
1160 (value & MGC_M_CSR0_TXPKTRDY)))
1161#endif
1162 musb_tx_rdy(s, ep);
1163 if (!ep &&
1164 (value & MGC_M_CSR0_H_REQPKT) &&
1165#ifdef CLEAR_NAK
1166 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1167 MGC_M_CSR0_RXPKTRDY)))
1168#else
1169 !(value & MGC_M_CSR0_RXPKTRDY))
1170#endif
1171 musb_rx_req(s, ep);
1172 break;
1173
1174 case MUSB_HDRC_RXMAXP:
1175 s->ep[ep].maxp[1] = value;
1176 break;
1177 case MUSB_HDRC_RXCSR:
1178 /* (DMA mode only) */
1179 if (
1180 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1181 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1182 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1183 value |= MGC_M_RXCSR_H_REQPKT;
1184
1185 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1186 s->ep[ep].csr[1] |= value & 0xfeb0;
1187
1188 musb_ep_frame_cancel(&s->ep[ep], 1);
1189
1190 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1191 s->ep[ep].fifolen[1] = 0;
1192 s->ep[ep].fifostart[1] = 0;
1193 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1194 /* If double buffering and we have two packets ready, flush
1195 * only the first one and set up the fifo at the second packet. */
1196 }
1197#ifdef CLEAR_NAK
1198 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1199#else
1200 if (value & MGC_M_RXCSR_H_REQPKT)
1201#endif
1202 musb_rx_req(s, ep);
1203 break;
1204 case MUSB_HDRC_RXCOUNT:
1205 s->ep[ep].rxcount = value;
1206 break;
1207
1208 default:
1209 musb_ep_writeb(s, ep, addr, value & 0xff);
1210 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1211 };
1212}
1213
1214/* Generic control */
c227f099 1215static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
942ac052 1216{
bc24a225 1217 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1218 int ep, i;
1219 uint8_t ret;
1220
1221 switch (addr) {
1222 case MUSB_HDRC_FADDR:
1223 return s->faddr;
1224 case MUSB_HDRC_POWER:
1225 return s->power;
1226 case MUSB_HDRC_INTRUSB:
1227 ret = s->intr;
1228 for (i = 0; i < sizeof(ret) * 8; i ++)
1229 if (ret & (1 << i))
1230 musb_intr_set(s, i, 0);
1231 return ret;
1232 case MUSB_HDRC_INTRUSBE:
1233 return s->mask;
1234 case MUSB_HDRC_INDEX:
1235 return s->idx;
1236 case MUSB_HDRC_TESTMODE:
1237 return 0x00;
1238
1239 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1240 return musb_ep_readb(s, s->idx, addr & 0xf);
1241
1242 case MUSB_HDRC_DEVCTL:
1243 return s->devctl;
1244
1245 case MUSB_HDRC_TXFIFOSZ:
1246 case MUSB_HDRC_RXFIFOSZ:
1247 case MUSB_HDRC_VCTRL:
1248 /* TODO */
1249 return 0x00;
1250
1251 case MUSB_HDRC_HWVERS:
1252 return (1 << 10) | 400;
1253
1254 case (MUSB_HDRC_VCTRL | 1):
1255 case (MUSB_HDRC_HWVERS | 1):
1256 case (MUSB_HDRC_DEVCTL | 1):
1257 return 0x00;
1258
1259 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1260 ep = (addr >> 3) & 0xf;
1261 return musb_busctl_readb(s, ep, addr & 0x7);
1262
1263 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1264 ep = (addr >> 4) & 0xf;
1265 return musb_ep_readb(s, ep, addr & 0xf);
1266
384dce1e
RV		 1267 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1268 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1269 return musb_read_fifo(s->ep + ep);
1270
942ac052 1271 default:
384dce1e 1272 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1273 return 0x00;
1274 };
1275}
1276
c227f099 1277static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1278{
bc24a225 1279 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1280 int ep;
1281
1282 switch (addr) {
1283 case MUSB_HDRC_FADDR:
1284 s->faddr = value & 0x7f;
1285 break;
1286 case MUSB_HDRC_POWER:
1287 s->power = (value & 0xef) | (s->power & 0x10);
1288 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1289 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1290 usb_send_msg(s->port.dev, USB_MSG_RESET);
1291 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1292 if ((value & MGC_M_POWER_HSENAB) &&
1293 s->port.dev->speed == USB_SPEED_HIGH)
1294 s->power |= MGC_M_POWER_HSMODE; /* Success */
1295 /* Restart frame counting. */
1296 }
1297 if (value & MGC_M_POWER_SUSPENDM) {
1298 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1299 * is set, also go into low power mode. Frame counting stops. */
1300 /* XXX: Cleared when the interrupt register is read */
1301 }
1302 if (value & MGC_M_POWER_RESUME) {
1303 /* Wait 20ms and signal resuming on the bus. Frame counting
1304 * restarts. */
1305 }
1306 break;
1307 case MUSB_HDRC_INTRUSB:
1308 break;
1309 case MUSB_HDRC_INTRUSBE:
1310 s->mask = value & 0xff;
1311 break;
1312 case MUSB_HDRC_INDEX:
1313 s->idx = value & 0xf;
1314 break;
1315 case MUSB_HDRC_TESTMODE:
1316 break;
1317
1318 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1319 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1320 break;
1321
1322 case MUSB_HDRC_DEVCTL:
1323 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1324 musb_session_update(s,
1325 !!s->port.dev,
1326 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1327
1328 /* It seems this is the only R/W bit in this register? */
1329 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1330 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1331 break;
1332
1333 case MUSB_HDRC_TXFIFOSZ:
1334 case MUSB_HDRC_RXFIFOSZ:
1335 case MUSB_HDRC_VCTRL:
1336 /* TODO */
1337 break;
1338
1339 case (MUSB_HDRC_VCTRL | 1):
1340 case (MUSB_HDRC_DEVCTL | 1):
1341 break;
1342
1343 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1344 ep = (addr >> 3) & 0xf;
1345 musb_busctl_writeb(s, ep, addr & 0x7, value);
1346 break;
1347
1348 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1349 ep = (addr >> 4) & 0xf;
1350 musb_ep_writeb(s, ep, addr & 0xf, value);
1351 break;
1352
384dce1e
RV		 1353 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1354 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1355 musb_write_fifo(s->ep + ep, value & 0xff);
1356 break;
1357
942ac052 1358 default:
384dce1e
RV		 1359 TRACE("unknown register 0x%02x", (int) addr);
1360 break;
942ac052
AZ		 1361 };
1362}
1363
c227f099 1364static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
942ac052 1365{
bc24a225 1366 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1367 int ep, i;
1368 uint16_t ret;
1369
1370 switch (addr) {
1371 case MUSB_HDRC_INTRTX:
1372 ret = s->tx_intr;
1373 /* Auto clear */
1374 for (i = 0; i < sizeof(ret) * 8; i ++)
1375 if (ret & (1 << i))
1376 musb_tx_intr_set(s, i, 0);
1377 return ret;
1378 case MUSB_HDRC_INTRRX:
1379 ret = s->rx_intr;
1380 /* Auto clear */
1381 for (i = 0; i < sizeof(ret) * 8; i ++)
1382 if (ret & (1 << i))
1383 musb_rx_intr_set(s, i, 0);
1384 return ret;
1385 case MUSB_HDRC_INTRTXE:
1386 return s->tx_mask;
1387 case MUSB_HDRC_INTRRXE:
1388 return s->rx_mask;
1389
1390 case MUSB_HDRC_FRAME:
1391 /* TODO */
1392 return 0x0000;
1393 case MUSB_HDRC_TXFIFOADDR:
1394 return s->ep[s->idx].fifoaddr[0];
1395 case MUSB_HDRC_RXFIFOADDR:
1396 return s->ep[s->idx].fifoaddr[1];
1397
1398 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1399 return musb_ep_readh(s, s->idx, addr & 0xf);
1400
1401 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1402 ep = (addr >> 3) & 0xf;
1403 return musb_busctl_readh(s, ep, addr & 0x7);
1404
1405 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1406 ep = (addr >> 4) & 0xf;
1407 return musb_ep_readh(s, ep, addr & 0xf);
1408
384dce1e
RV		 1409 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1410 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1411 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1412
942ac052
AZ		 1413 default:
1414 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1415 };
1416}
1417
c227f099 1418static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1419{
bc24a225 1420 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1421 int ep;
1422
1423 switch (addr) {
1424 case MUSB_HDRC_INTRTXE:
1425 s->tx_mask = value;
1426 /* XXX: the masks seem to apply on the raising edge like with
1427 * edge-triggered interrupts, thus no need to update. I may be
1428 * wrong though. */
1429 break;
1430 case MUSB_HDRC_INTRRXE:
1431 s->rx_mask = value;
1432 break;
1433
1434 case MUSB_HDRC_FRAME:
1435 /* TODO */
1436 break;
1437 case MUSB_HDRC_TXFIFOADDR:
1438 s->ep[s->idx].fifoaddr[0] = value;
1439 s->ep[s->idx].buf[0] =
384dce1e 1440 s->buf + ((value << 3) & 0x7ff );
942ac052
AZ		 1441 break;
1442 case MUSB_HDRC_RXFIFOADDR:
1443 s->ep[s->idx].fifoaddr[1] = value;
1444 s->ep[s->idx].buf[1] =
384dce1e 1445 s->buf + ((value << 3) & 0x7ff);
942ac052
AZ		 1446 break;
1447
1448 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1449 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1450 break;
1451
1452 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1453 ep = (addr >> 3) & 0xf;
1454 musb_busctl_writeh(s, ep, addr & 0x7, value);
1455 break;
1456
1457 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1458 ep = (addr >> 4) & 0xf;
1459 musb_ep_writeh(s, ep, addr & 0xf, value);
1460 break;
1461
384dce1e
RV		 1462 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1463 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1464 musb_write_fifo(s->ep + ep, value & 0xff);
1465 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1466 break;
1467
942ac052
AZ		 1468 default:
1469 musb_writeb(s, addr, value & 0xff);
1470 musb_writeb(s, addr | 1, value >> 8);
1471 };
1472}
1473
c227f099 1474static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
942ac052 1475{
bc24a225 1476 MUSBState *s = (MUSBState *) opaque;
384dce1e 1477 int ep;
942ac052
AZ		 1478
1479 switch (addr) {
1480 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1481 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1482 return ( musb_read_fifo(s->ep + ep) |
1483 musb_read_fifo(s->ep + ep) << 8 |
1484 musb_read_fifo(s->ep + ep) << 16 |
1485 musb_read_fifo(s->ep + ep) << 24 );
942ac052 1486 default:
384dce1e 1487 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1488 return 0x00000000;
1489 };
1490}
1491
c227f099 1492static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1493{
bc24a225 1494 MUSBState *s = (MUSBState *) opaque;
384dce1e 1495 int ep;
942ac052
AZ		 1496
1497 switch (addr) {
1498 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1499 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1500 musb_write_fifo(s->ep + ep, value & 0xff);
1501 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1502 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1503 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
942ac052 1504 break;
942ac052 1505 default:
384dce1e
RV		 1506 TRACE("unknown register 0x%02x", (int) addr);
1507 break;
942ac052
AZ		 1508 };
1509}
1510
d60efc6b 1511CPUReadMemoryFunc * const musb_read[] = {
942ac052
AZ		 1512 musb_readb,
1513 musb_readh,
1514 musb_readw,
1515};
1516
d60efc6b 1517CPUWriteMemoryFunc * const musb_write[] = {
942ac052
AZ		 1518 musb_writeb,
1519 musb_writeh,
1520 musb_writew,
1521};
Qemu copy for testing