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usb: create USBPortOps, move attach there.
[qemu.git] / hw / usb-musb.c
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942ac052
AZ		 1/*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
942ac052
AZ		 20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23#include "qemu-common.h"
24#include "qemu-timer.h"
25#include "usb.h"
26#include "irq.h"
384dce1e 27#include "hw.h"
942ac052
AZ		 28
29/* Common USB registers */
30#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31#define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34#define MUSB_HDRC_INTRRX 0x04
35#define MUSB_HDRC_INTRTXE 0x06
36#define MUSB_HDRC_INTRRXE 0x08
37#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43/* Per-EP registers in indexed mode */
44#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46/* EP FIFOs */
47#define MUSB_HDRC_FIFO 0x20
48
49/* Additional Control Registers */
50#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52/* These are indexed */
53#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58/* Some more registers */
59#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62/* Added in HDRC 1.9(?) & MHDRC 1.4 */
63/* ULPI pass-through */
64#define MUSB_HDRC_ULPI_VBUSCTL 0x70
65#define MUSB_HDRC_ULPI_REGDATA 0x74
66#define MUSB_HDRC_ULPI_REGADDR 0x75
67#define MUSB_HDRC_ULPI_REGCTL 0x76
68
69/* Extended config & PHY control */
70#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78/* Per-EP BUSCTL registers */
79#define MUSB_HDRC_BUSCTL 0x80
80
81/* Per-EP registers in flat mode */
82#define MUSB_HDRC_EP 0x100
83
84/* offsets to registers in flat model */
85#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101/* "Bus control" registers */
102#define MUSB_HDRC_TXFUNCADDR 0x00
103#define MUSB_HDRC_TXHUBADDR 0x02
104#define MUSB_HDRC_TXHUBPORT 0x03
105
106#define MUSB_HDRC_RXFUNCADDR 0x04
107#define MUSB_HDRC_RXHUBADDR 0x06
108#define MUSB_HDRC_RXHUBPORT 0x07
109
110/*
111 * MUSBHDRC Register bit masks
112 */
113
114/* POWER */
115#define MGC_M_POWER_ISOUPDATE 0x80
116#define MGC_M_POWER_SOFTCONN 0x40
117#define MGC_M_POWER_HSENAB 0x20
118#define MGC_M_POWER_HSMODE 0x10
119#define MGC_M_POWER_RESET 0x08
120#define MGC_M_POWER_RESUME 0x04
121#define MGC_M_POWER_SUSPENDM 0x02
122#define MGC_M_POWER_ENSUSPEND 0x01
123
124/* INTRUSB */
125#define MGC_M_INTR_SUSPEND 0x01
126#define MGC_M_INTR_RESUME 0x02
127#define MGC_M_INTR_RESET 0x04
128#define MGC_M_INTR_BABBLE 0x04
129#define MGC_M_INTR_SOF 0x08
130#define MGC_M_INTR_CONNECT 0x10
131#define MGC_M_INTR_DISCONNECT 0x20
132#define MGC_M_INTR_SESSREQ 0x40
133#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136/* DEVCTL */
137#define MGC_M_DEVCTL_BDEVICE 0x80
138#define MGC_M_DEVCTL_FSDEV 0x40
139#define MGC_M_DEVCTL_LSDEV 0x20
140#define MGC_M_DEVCTL_VBUS 0x18
141#define MGC_S_DEVCTL_VBUS 3
142#define MGC_M_DEVCTL_HM 0x04
143#define MGC_M_DEVCTL_HR 0x02
144#define MGC_M_DEVCTL_SESSION 0x01
145
146/* TESTMODE */
147#define MGC_M_TEST_FORCE_HOST 0x80
148#define MGC_M_TEST_FIFO_ACCESS 0x40
149#define MGC_M_TEST_FORCE_FS 0x20
150#define MGC_M_TEST_FORCE_HS 0x10
151#define MGC_M_TEST_PACKET 0x08
152#define MGC_M_TEST_K 0x04
153#define MGC_M_TEST_J 0x02
154#define MGC_M_TEST_SE0_NAK 0x01
155
156/* CSR0 */
157#define MGC_M_CSR0_FLUSHFIFO 0x0100
158#define MGC_M_CSR0_TXPKTRDY 0x0002
159#define MGC_M_CSR0_RXPKTRDY 0x0001
160
161/* CSR0 in Peripheral mode */
162#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164#define MGC_M_CSR0_P_SENDSTALL 0x0020
165#define MGC_M_CSR0_P_SETUPEND 0x0010
166#define MGC_M_CSR0_P_DATAEND 0x0008
167#define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169/* CSR0 in Host mode */
170#define MGC_M_CSR0_H_NO_PING 0x0800
171#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174#define MGC_M_CSR0_H_STATUSPKT 0x0040
175#define MGC_M_CSR0_H_REQPKT 0x0020
176#define MGC_M_CSR0_H_ERROR 0x0010
177#define MGC_M_CSR0_H_SETUPPKT 0x0008
178#define MGC_M_CSR0_H_RXSTALL 0x0004
179
180/* CONFIGDATA */
181#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190/* TXCSR in Peripheral and Host mode */
191#define MGC_M_TXCSR_AUTOSET 0x8000
192#define MGC_M_TXCSR_ISO 0x4000
193#define MGC_M_TXCSR_MODE 0x2000
194#define MGC_M_TXCSR_DMAENAB 0x1000
195#define MGC_M_TXCSR_FRCDATATOG 0x0800
196#define MGC_M_TXCSR_DMAMODE 0x0400
197#define MGC_M_TXCSR_CLRDATATOG 0x0040
198#define MGC_M_TXCSR_FLUSHFIFO 0x0008
199#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200#define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202/* TXCSR in Peripheral mode */
203#define MGC_M_TXCSR_P_INCOMPTX 0x0080
204#define MGC_M_TXCSR_P_SENTSTALL 0x0020
205#define MGC_M_TXCSR_P_SENDSTALL 0x0010
206#define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208/* TXCSR in Host mode */
209#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212#define MGC_M_TXCSR_H_RXSTALL 0x0020
213#define MGC_M_TXCSR_H_ERROR 0x0004
214
215/* RXCSR in Peripheral and Host mode */
216#define MGC_M_RXCSR_AUTOCLEAR 0x8000
217#define MGC_M_RXCSR_DMAENAB 0x2000
218#define MGC_M_RXCSR_DISNYET 0x1000
219#define MGC_M_RXCSR_DMAMODE 0x0800
220#define MGC_M_RXCSR_INCOMPRX 0x0100
221#define MGC_M_RXCSR_CLRDATATOG 0x0080
222#define MGC_M_RXCSR_FLUSHFIFO 0x0010
223#define MGC_M_RXCSR_DATAERROR 0x0008
224#define MGC_M_RXCSR_FIFOFULL 0x0002
225#define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227/* RXCSR in Peripheral mode */
228#define MGC_M_RXCSR_P_ISO 0x4000
229#define MGC_M_RXCSR_P_SENTSTALL 0x0040
230#define MGC_M_RXCSR_P_SENDSTALL 0x0020
231#define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233/* RXCSR in Host mode */
234#define MGC_M_RXCSR_H_AUTOREQ 0x4000
235#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237#define MGC_M_RXCSR_H_RXSTALL 0x0040
238#define MGC_M_RXCSR_H_REQPKT 0x0020
239#define MGC_M_RXCSR_H_ERROR 0x0004
240
241/* HUBADDR */
242#define MGC_M_HUBADDR_MULTI_TT 0x80
243
244/* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250#define MGC_M_ULPI_REGCTL_REG 0x01
251
384dce1e
RV		 252/* #define MUSB_DEBUG */
253
254#ifdef MUSB_DEBUG
255#define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257#else
258#define TRACE(...)
259#endif
260
261
942ac052
AZ		 262static void musb_attach(USBPort *port, USBDevice *dev);
263
0d86d2be
GH		 264static USBPortOps musb_port_ops = {
265 .attach = musb_attach,
266};
267
bc24a225
PB		 268typedef struct {
269 uint16_t faddr[2];
270 uint8_t haddr[2];
271 uint8_t hport[2];
272 uint16_t csr[2];
273 uint16_t maxp[2];
274 uint16_t rxcount;
275 uint8_t type[2];
276 uint8_t interval[2];
277 uint8_t config;
278 uint8_t fifosize;
279 int timeout[2]; /* Always in microframes */
280
384dce1e 281 uint8_t *buf[2];
bc24a225
PB		 282 int fifolen[2];
283 int fifostart[2];
284 int fifoaddr[2];
285 USBPacket packey[2];
286 int status[2];
287 int ext_size[2];
288
289 /* For callbacks' use */
290 int epnum;
291 int interrupt[2];
292 MUSBState *musb;
293 USBCallback *delayed_cb[2];
294 QEMUTimer *intv_timer[2];
295} MUSBEndPoint;
296
297struct MUSBState {
942ac052 298 qemu_irq *irqs;
b2317837 299 USBBus bus;
942ac052
AZ		 300 USBPort port;
301
302 int idx;
303 uint8_t devctl;
304 uint8_t power;
305 uint8_t faddr;
306
307 uint8_t intr;
308 uint8_t mask;
309 uint16_t tx_intr;
310 uint16_t tx_mask;
311 uint16_t rx_intr;
312 uint16_t rx_mask;
313
314 int setup_len;
315 int session;
316
384dce1e 317 uint8_t buf[0x8000];
942ac052 318
942ac052
AZ		 319 /* Duplicating the world since 2008!... probably we should have 32
320 * logical, single endpoints instead. */
bc24a225 321 MUSBEndPoint ep[16];
942ac052
AZ		 322} *musb_init(qemu_irq *irqs)
323{
bc24a225 324 MUSBState *s = qemu_mallocz(sizeof(*s));
942ac052
AZ		 325 int i;
326
327 s->irqs = irqs;
328
329 s->faddr = 0x00;
330 s->power = MGC_M_POWER_HSENAB;
331 s->tx_intr = 0x0000;
332 s->rx_intr = 0x0000;
333 s->tx_mask = 0xffff;
334 s->rx_mask = 0xffff;
335 s->intr = 0x00;
336 s->mask = 0x06;
337 s->idx = 0;
338
339 /* TODO: _DW */
340 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
341 for (i = 0; i < 16; i ++) {
342 s->ep[i].fifosize = 64;
343 s->ep[i].maxp[0] = 0x40;
344 s->ep[i].maxp[1] = 0x40;
345 s->ep[i].musb = s;
346 s->ep[i].epnum = i;
347 }
348
b2317837 349 usb_bus_new(&s->bus, NULL /* FIXME */);
0d86d2be 350 usb_register_port(&s->bus, &s->port, s, 0, NULL, &musb_port_ops);
942ac052
AZ		 351
352 return s;
353}
354
bc24a225 355static void musb_vbus_set(MUSBState *s, int level)
942ac052
AZ		 356{
357 if (level)
358 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
359 else
360 s->devctl &= ~MGC_M_DEVCTL_VBUS;
361
362 qemu_set_irq(s->irqs[musb_set_vbus], level);
363}
364
bc24a225 365static void musb_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 366{
367 if (!level) {
368 s->intr &= ~(1 << line);
369 qemu_irq_lower(s->irqs[line]);
370 } else if (s->mask & (1 << line)) {
371 s->intr |= 1 << line;
372 qemu_irq_raise(s->irqs[line]);
373 }
374}
375
bc24a225 376static void musb_tx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 377{
378 if (!level) {
379 s->tx_intr &= ~(1 << line);
380 if (!s->tx_intr)
381 qemu_irq_lower(s->irqs[musb_irq_tx]);
382 } else if (s->tx_mask & (1 << line)) {
383 s->tx_intr |= 1 << line;
384 qemu_irq_raise(s->irqs[musb_irq_tx]);
385 }
386}
387
bc24a225 388static void musb_rx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 389{
390 if (line) {
391 if (!level) {
392 s->rx_intr &= ~(1 << line);
393 if (!s->rx_intr)
394 qemu_irq_lower(s->irqs[musb_irq_rx]);
395 } else if (s->rx_mask & (1 << line)) {
396 s->rx_intr |= 1 << line;
397 qemu_irq_raise(s->irqs[musb_irq_rx]);
398 }
399 } else
400 musb_tx_intr_set(s, line, level);
401}
402
bc24a225 403uint32_t musb_core_intr_get(MUSBState *s)
942ac052
AZ		 404{
405 return (s->rx_intr << 15) | s->tx_intr;
406}
407
bc24a225 408void musb_core_intr_clear(MUSBState *s, uint32_t mask)
942ac052
AZ		 409{
410 if (s->rx_intr) {
411 s->rx_intr &= mask >> 15;
412 if (!s->rx_intr)
413 qemu_irq_lower(s->irqs[musb_irq_rx]);
414 }
415
416 if (s->tx_intr) {
417 s->tx_intr &= mask & 0xffff;
418 if (!s->tx_intr)
419 qemu_irq_lower(s->irqs[musb_irq_tx]);
420 }
421}
422
bc24a225 423void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
942ac052
AZ		 424{
425 s->ep[epnum].ext_size[!is_tx] = size;
426 s->ep[epnum].fifostart[0] = 0;
427 s->ep[epnum].fifostart[1] = 0;
428 s->ep[epnum].fifolen[0] = 0;
429 s->ep[epnum].fifolen[1] = 0;
430}
431
bc24a225 432static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
942ac052
AZ		 433{
434 int detect_prev = prev_dev && prev_sess;
435 int detect = !!s->port.dev && s->session;
436
437 if (detect && !detect_prev) {
438 /* Let's skip the ID pin sense and VBUS sense formalities and
439 * and signal a successful SRP directly. This should work at least
440 * for the Linux driver stack. */
441 musb_intr_set(s, musb_irq_connect, 1);
442
443 if (s->port.dev->speed == USB_SPEED_LOW) {
444 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
445 s->devctl |= MGC_M_DEVCTL_LSDEV;
446 } else {
447 s->devctl |= MGC_M_DEVCTL_FSDEV;
448 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
449 }
450
451 /* A-mode? */
452 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
453
454 /* Host-mode bit? */
455 s->devctl |= MGC_M_DEVCTL_HM;
456#if 1
457 musb_vbus_set(s, 1);
458#endif
459 } else if (!detect && detect_prev) {
460#if 1
461 musb_vbus_set(s, 0);
462#endif
463 }
464}
465
466/* Attach or detach a device on our only port. */
467static void musb_attach(USBPort *port, USBDevice *dev)
468{
bc24a225 469 MUSBState *s = (MUSBState *) port->opaque;
942ac052
AZ		 470 USBDevice *curr;
471
472 port = &s->port;
473 curr = port->dev;
474
475 if (dev) {
476 if (curr) {
477 usb_attach(port, NULL);
478 /* TODO: signal some interrupts */
479 }
480
481 musb_intr_set(s, musb_irq_vbus_request, 1);
482
483 /* Send the attach message to device */
484 usb_send_msg(dev, USB_MSG_ATTACH);
485 } else if (curr) {
486 /* Send the detach message */
487 usb_send_msg(curr, USB_MSG_DETACH);
488
489 musb_intr_set(s, musb_irq_disconnect, 1);
490 }
491
492 port->dev = dev;
493
494 musb_session_update(s, !!curr, s->session);
495}
496
497static inline void musb_cb_tick0(void *opaque)
498{
bc24a225 499 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052
AZ		 500
501 ep->delayed_cb[0](&ep->packey[0], opaque);
502}
503
504static inline void musb_cb_tick1(void *opaque)
505{
bc24a225 506 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052
AZ		 507
508 ep->delayed_cb[1](&ep->packey[1], opaque);
509}
510
511#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
512
513static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir)
514{
bc24a225 515 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052
AZ		 516 int timeout = 0;
517
518 if (ep->status[dir] == USB_RET_NAK)
519 timeout = ep->timeout[dir];
520 else if (ep->interrupt[dir])
521 timeout = 8;
522 else
523 return musb_cb_tick(opaque);
524
525 if (!ep->intv_timer[dir])
526 ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque);
527
528 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) +
6ee093c9 529 muldiv64(timeout, get_ticks_per_sec(), 8000));
942ac052
AZ		 530}
531
532static void musb_schedule0_cb(USBPacket *packey, void *opaque)
533{
534 return musb_schedule_cb(packey, opaque, 0);
535}
536
537static void musb_schedule1_cb(USBPacket *packey, void *opaque)
538{
539 return musb_schedule_cb(packey, opaque, 1);
540}
541
542static int musb_timeout(int ttype, int speed, int val)
543{
544#if 1
545 return val << 3;
546#endif
547
548 switch (ttype) {
549 case USB_ENDPOINT_XFER_CONTROL:
550 if (val < 2)
551 return 0;
552 else if (speed == USB_SPEED_HIGH)
553 return 1 << (val - 1);
554 else
555 return 8 << (val - 1);
556
557 case USB_ENDPOINT_XFER_INT:
558 if (speed == USB_SPEED_HIGH)
559 if (val < 2)
560 return 0;
561 else
562 return 1 << (val - 1);
563 else
564 return val << 3;
565
566 case USB_ENDPOINT_XFER_BULK:
567 case USB_ENDPOINT_XFER_ISOC:
568 if (val < 2)
569 return 0;
570 else if (speed == USB_SPEED_HIGH)
571 return 1 << (val - 1);
572 else
573 return 8 << (val - 1);
574 /* TODO: what with low-speed Bulk and Isochronous? */
575 }
576
2ac71179 577 hw_error("bad interval\n");
942ac052
AZ		 578}
579
bc24a225 580static inline void musb_packet(MUSBState *s, MUSBEndPoint *ep,
942ac052
AZ		 581 int epnum, int pid, int len, USBCallback cb, int dir)
582{
583 int ret;
584 int idx = epnum && dir;
585 int ttype;
586
587 /* ep->type[0,1] contains:
588 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
589 * in bits 5:4 the transfer type (BULK / INT)
590 * in bits 3:0 the EP num
591 */
592 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
593
594 ep->timeout[dir] = musb_timeout(ttype,
595 ep->type[idx] >> 6, ep->interval[idx]);
596 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
597 ep->delayed_cb[dir] = cb;
598 cb = dir ? musb_schedule1_cb : musb_schedule0_cb;
599
600 ep->packey[dir].pid = pid;
601 /* A wild guess on the FADDR semantics... */
602 ep->packey[dir].devaddr = ep->faddr[idx];
603 ep->packey[dir].devep = ep->type[idx] & 0xf;
604 ep->packey[dir].data = (void *) ep->buf[idx];
605 ep->packey[dir].len = len;
606 ep->packey[dir].complete_cb = cb;
607 ep->packey[dir].complete_opaque = ep;
608
609 if (s->port.dev)
806b6024 610 ret = s->port.dev->info->handle_packet(s->port.dev, &ep->packey[dir]);
942ac052
AZ		 611 else
612 ret = USB_RET_NODEV;
613
614 if (ret == USB_RET_ASYNC) {
615 ep->status[dir] = len;
616 return;
617 }
618
619 ep->status[dir] = ret;
620 usb_packet_complete(&ep->packey[dir]);
621}
622
623static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
624{
625 /* Unfortunately we can't use packey->devep because that's the remote
626 * endpoint number and may be different than our local. */
bc24a225 627 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 628 int epnum = ep->epnum;
bc24a225 629 MUSBState *s = ep->musb;
942ac052
AZ		 630
631 ep->fifostart[0] = 0;
632 ep->fifolen[0] = 0;
633#ifdef CLEAR_NAK
634 if (ep->status[0] != USB_RET_NAK) {
635#endif
636 if (epnum)
637 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
638 else
639 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
640#ifdef CLEAR_NAK
641 }
642#endif
643
644 /* Clear all of the error bits first */
645 if (epnum)
646 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
647 MGC_M_TXCSR_H_NAKTIMEOUT);
648 else
649 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
650 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
651
652 if (ep->status[0] == USB_RET_STALL) {
653 /* Command not supported by target! */
654 ep->status[0] = 0;
655
656 if (epnum)
657 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
658 else
659 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
660 }
661
662 if (ep->status[0] == USB_RET_NAK) {
663 ep->status[0] = 0;
664
665 /* NAK timeouts are only generated in Bulk transfers and
666 * Data-errors in Isochronous. */
667 if (ep->interrupt[0]) {
668 return;
669 }
670
671 if (epnum)
672 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
673 else
674 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
675 }
676
677 if (ep->status[0] < 0) {
678 if (ep->status[0] == USB_RET_BABBLE)
679 musb_intr_set(s, musb_irq_rst_babble, 1);
680
681 /* Pretend we've tried three times already and failed (in
682 * case of USB_TOKEN_SETUP). */
683 if (epnum)
684 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
685 else
686 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
687
688 musb_tx_intr_set(s, epnum, 1);
689 return;
690 }
691 /* TODO: check len for over/underruns of an OUT packet? */
692
693#ifdef SETUPLEN_HACK
694 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
695 s->setup_len = ep->packey[0].data[6];
696#endif
697
698 /* In DMA mode: if no error, assert DMA request for this EP,
699 * and skip the interrupt. */
700 musb_tx_intr_set(s, epnum, 1);
701}
702
703static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
704{
705 /* Unfortunately we can't use packey->devep because that's the remote
706 * endpoint number and may be different than our local. */
bc24a225 707 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 708 int epnum = ep->epnum;
bc24a225 709 MUSBState *s = ep->musb;
942ac052
AZ		 710
711 ep->fifostart[1] = 0;
712 ep->fifolen[1] = 0;
713
714#ifdef CLEAR_NAK
715 if (ep->status[1] != USB_RET_NAK) {
716#endif
717 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
718 if (!epnum)
719 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
720#ifdef CLEAR_NAK
721 }
722#endif
723
724 /* Clear all of the imaginable error bits first */
725 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
726 MGC_M_RXCSR_DATAERROR);
727 if (!epnum)
728 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
729 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
730
731 if (ep->status[1] == USB_RET_STALL) {
732 ep->status[1] = 0;
733 packey->len = 0;
734
735 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
736 if (!epnum)
737 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
738 }
739
740 if (ep->status[1] == USB_RET_NAK) {
741 ep->status[1] = 0;
742
743 /* NAK timeouts are only generated in Bulk transfers and
744 * Data-errors in Isochronous. */
745 if (ep->interrupt[1])
746 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
747 packey->len, musb_rx_packet_complete, 1);
748
749 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
750 if (!epnum)
751 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
752 }
753
754 if (ep->status[1] < 0) {
755 if (ep->status[1] == USB_RET_BABBLE) {
756 musb_intr_set(s, musb_irq_rst_babble, 1);
757 return;
758 }
759
760 /* Pretend we've tried three times already and failed (in
761 * case of a control transfer). */
762 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
763 if (!epnum)
764 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
765
766 musb_rx_intr_set(s, epnum, 1);
767 return;
768 }
769 /* TODO: check len for over/underruns of an OUT packet? */
770 /* TODO: perhaps make use of e->ext_size[1] here. */
771
772 packey->len = ep->status[1];
773
774 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
775 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
776 if (!epnum)
777 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
778
779 ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
780 /* In DMA mode: assert DMA request for this EP */
781 }
782
783 /* Only if DMA has not been asserted */
784 musb_rx_intr_set(s, epnum, 1);
785}
786
bc24a225 787static void musb_tx_rdy(MUSBState *s, int epnum)
942ac052 788{
bc24a225 789 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 790 int pid;
791 int total, valid = 0;
384dce1e 792 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
942ac052
AZ		 793 ep->fifostart[0] += ep->fifolen[0];
794 ep->fifolen[0] = 0;
795
796 /* XXX: how's the total size of the packet retrieved exactly in
797 * the generic case? */
798 total = ep->maxp[0] & 0x3ff;
799
800 if (ep->ext_size[0]) {
801 total = ep->ext_size[0];
802 ep->ext_size[0] = 0;
803 valid = 1;
804 }
805
806 /* If the packet is not fully ready yet, wait for a next segment. */
384dce1e 807 if (epnum && (ep->fifostart[0]) < total)
942ac052
AZ		 808 return;
809
810 if (!valid)
384dce1e 811 total = ep->fifostart[0];
942ac052
AZ		 812
813 pid = USB_TOKEN_OUT;
814 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
815 pid = USB_TOKEN_SETUP;
384dce1e
RV		 816 if (total != 8) {
817 TRACE("illegal SETUPPKT length of %i bytes", total);
818 }
942ac052
AZ		 819 /* Controller should retry SETUP packets three times on errors
820 * but it doesn't make sense for us to do that. */
821 }
822
823 return musb_packet(s, ep, epnum, pid,
824 total, musb_tx_packet_complete, 0);
825}
826
bc24a225 827static void musb_rx_req(MUSBState *s, int epnum)
942ac052 828{
bc24a225 829 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 830 int total;
831
832 /* If we already have a packet, which didn't fit into the
833 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
834 if (ep->packey[1].pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
384dce1e 835 (ep->fifostart[1]) + ep->rxcount <
942ac052 836 ep->packey[1].len) {
384dce1e
RV		 837 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
838 ep->fifostart[1] += ep->rxcount;
942ac052
AZ		 839 ep->fifolen[1] = 0;
840
384dce1e 841 ep->rxcount = MIN(ep->packey[0].len - (ep->fifostart[1]),
942ac052
AZ		 842 ep->maxp[1]);
843
844 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
845 if (!epnum)
846 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
847
848 /* Clear all of the error bits first */
849 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
850 MGC_M_RXCSR_DATAERROR);
851 if (!epnum)
852 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
853 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
854
855 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
856 if (!epnum)
857 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
858 musb_rx_intr_set(s, epnum, 1);
859 return;
860 }
861
862 /* The driver sets maxp[1] to 64 or less because it knows the hardware
863 * FIFO is this deep. Bigger packets get split in
864 * usb_generic_handle_packet but we can also do the splitting locally
865 * for performance. It turns out we can also have a bigger FIFO and
866 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
867 * OK with single packets of even 32KB and we avoid splitting, however
868 * usb_msd.c sometimes sends a packet bigger than what Linux expects
869 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
870 * hides this overrun from Linux. Up to 4096 everything is fine
871 * though. Currently this is disabled.
872 *
873 * XXX: mind ep->fifosize. */
874 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
875
876#ifdef SETUPLEN_HACK
877 /* Why should *we* do that instead of Linux? */
878 if (!epnum) {
879 if (ep->packey[0].devaddr == 2)
880 total = MIN(s->setup_len, 8);
881 else
882 total = MIN(s->setup_len, 64);
883 s->setup_len -= total;
884 }
885#endif
886
887 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
888 total, musb_rx_packet_complete, 1);
889}
890
384dce1e
RV		 891static uint8_t musb_read_fifo(MUSBEndPoint *ep)
892{
893 uint8_t value;
894 if (ep->fifolen[1] >= 64) {
895 /* We have a FIFO underrun */
896 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
897 return 0x00000000;
898 }
899 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
900 * (if AUTOREQ is set) */
901
902 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
903 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
904 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
905 return value;
906}
907
908static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
909{
910 TRACE("EP%d = %02x", ep->epnum, value);
911 if (ep->fifolen[0] >= 64) {
912 /* We have a FIFO overrun */
913 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
914 return;
915 }
916
917 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
918 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
919}
920
bc24a225 921static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
942ac052
AZ		 922{
923 if (ep->intv_timer[dir])
924 qemu_del_timer(ep->intv_timer[dir]);
925}
926
927/* Bus control */
928static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
929{
bc24a225 930 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 931
932 switch (addr) {
933 /* For USB2.0 HS hubs only */
934 case MUSB_HDRC_TXHUBADDR:
935 return s->ep[ep].haddr[0];
936 case MUSB_HDRC_TXHUBPORT:
937 return s->ep[ep].hport[0];
938 case MUSB_HDRC_RXHUBADDR:
939 return s->ep[ep].haddr[1];
940 case MUSB_HDRC_RXHUBPORT:
941 return s->ep[ep].hport[1];
942
943 default:
384dce1e 944 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 945 return 0x00;
946 };
947}
948
949static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
950{
bc24a225 951 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 952
953 switch (addr) {
384dce1e
RV		 954 case MUSB_HDRC_TXFUNCADDR:
955 s->ep[ep].faddr[0] = value;
956 break;
957 case MUSB_HDRC_RXFUNCADDR:
958 s->ep[ep].faddr[1] = value;
959 break;
942ac052
AZ		 960 case MUSB_HDRC_TXHUBADDR:
961 s->ep[ep].haddr[0] = value;
962 break;
963 case MUSB_HDRC_TXHUBPORT:
964 s->ep[ep].hport[0] = value;
965 break;
966 case MUSB_HDRC_RXHUBADDR:
967 s->ep[ep].haddr[1] = value;
968 break;
969 case MUSB_HDRC_RXHUBPORT:
970 s->ep[ep].hport[1] = value;
971 break;
972
973 default:
384dce1e
RV		 974 TRACE("unknown register 0x%02x", addr);
975 break;
942ac052
AZ		 976 };
977}
978
979static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
980{
bc24a225 981 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 982
983 switch (addr) {
984 case MUSB_HDRC_TXFUNCADDR:
985 return s->ep[ep].faddr[0];
986 case MUSB_HDRC_RXFUNCADDR:
987 return s->ep[ep].faddr[1];
988
989 default:
990 return musb_busctl_readb(s, ep, addr) |
991 (musb_busctl_readb(s, ep, addr | 1) << 8);
992 };
993}
994
995static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
996{
bc24a225 997 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 998
999 switch (addr) {
1000 case MUSB_HDRC_TXFUNCADDR:
1001 s->ep[ep].faddr[0] = value;
1002 break;
1003 case MUSB_HDRC_RXFUNCADDR:
1004 s->ep[ep].faddr[1] = value;
1005 break;
1006
1007 default:
1008 musb_busctl_writeb(s, ep, addr, value & 0xff);
1009 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
1010 };
1011}
1012
1013/* Endpoint control */
1014static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1015{
bc24a225 1016 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1017
1018 switch (addr) {
1019 case MUSB_HDRC_TXTYPE:
1020 return s->ep[ep].type[0];
1021 case MUSB_HDRC_TXINTERVAL:
1022 return s->ep[ep].interval[0];
1023 case MUSB_HDRC_RXTYPE:
1024 return s->ep[ep].type[1];
1025 case MUSB_HDRC_RXINTERVAL:
1026 return s->ep[ep].interval[1];
1027 case (MUSB_HDRC_FIFOSIZE & ~1):
1028 return 0x00;
1029 case MUSB_HDRC_FIFOSIZE:
1030 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
384dce1e
RV		 1031 case MUSB_HDRC_RXCOUNT:
1032 return s->ep[ep].rxcount;
942ac052
AZ		 1033
1034 default:
384dce1e 1035 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 1036 return 0x00;
1037 };
1038}
1039
1040static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1041{
bc24a225 1042 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1043
1044 switch (addr) {
1045 case MUSB_HDRC_TXTYPE:
1046 s->ep[ep].type[0] = value;
1047 break;
1048 case MUSB_HDRC_TXINTERVAL:
1049 s->ep[ep].interval[0] = value;
1050 musb_ep_frame_cancel(&s->ep[ep], 0);
1051 break;
1052 case MUSB_HDRC_RXTYPE:
1053 s->ep[ep].type[1] = value;
1054 break;
1055 case MUSB_HDRC_RXINTERVAL:
1056 s->ep[ep].interval[1] = value;
1057 musb_ep_frame_cancel(&s->ep[ep], 1);
1058 break;
1059 case (MUSB_HDRC_FIFOSIZE & ~1):
1060 break;
1061 case MUSB_HDRC_FIFOSIZE:
384dce1e 1062 TRACE("somebody messes with fifosize (now %i bytes)", value);
942ac052
AZ		 1063 s->ep[ep].fifosize = value;
1064 break;
942ac052 1065 default:
384dce1e
RV		 1066 TRACE("unknown register 0x%02x", addr);
1067 break;
942ac052
AZ		 1068 };
1069}
1070
1071static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1072{
bc24a225 1073 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1074 uint16_t ret;
1075
1076 switch (addr) {
1077 case MUSB_HDRC_TXMAXP:
1078 return s->ep[ep].maxp[0];
1079 case MUSB_HDRC_TXCSR:
1080 return s->ep[ep].csr[0];
1081 case MUSB_HDRC_RXMAXP:
1082 return s->ep[ep].maxp[1];
1083 case MUSB_HDRC_RXCSR:
1084 ret = s->ep[ep].csr[1];
1085
1086 /* TODO: This and other bits probably depend on
1087 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1088 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1089 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1090
1091 return ret;
1092 case MUSB_HDRC_RXCOUNT:
1093 return s->ep[ep].rxcount;
1094
1095 default:
1096 return musb_ep_readb(s, ep, addr) |
1097 (musb_ep_readb(s, ep, addr | 1) << 8);
1098 };
1099}
1100
1101static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1102{
bc24a225 1103 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1104
1105 switch (addr) {
1106 case MUSB_HDRC_TXMAXP:
1107 s->ep[ep].maxp[0] = value;
1108 break;
1109 case MUSB_HDRC_TXCSR:
1110 if (ep) {
1111 s->ep[ep].csr[0] &= value & 0xa6;
1112 s->ep[ep].csr[0] |= value & 0xff59;
1113 } else {
1114 s->ep[ep].csr[0] &= value & 0x85;
1115 s->ep[ep].csr[0] |= value & 0xf7a;
1116 }
1117
1118 musb_ep_frame_cancel(&s->ep[ep], 0);
1119
1120 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1121 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1122 s->ep[ep].fifolen[0] = 0;
1123 s->ep[ep].fifostart[0] = 0;
1124 if (ep)
1125 s->ep[ep].csr[0] &=
1126 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1127 else
1128 s->ep[ep].csr[0] &=
1129 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1130 }
1131 if (
1132 (ep &&
1133#ifdef CLEAR_NAK
1134 (value & MGC_M_TXCSR_TXPKTRDY) &&
1135 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1136#else
1137 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1138#endif
1139 (!ep &&
1140#ifdef CLEAR_NAK
1141 (value & MGC_M_CSR0_TXPKTRDY) &&
1142 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1143#else
1144 (value & MGC_M_CSR0_TXPKTRDY)))
1145#endif
1146 musb_tx_rdy(s, ep);
1147 if (!ep &&
1148 (value & MGC_M_CSR0_H_REQPKT) &&
1149#ifdef CLEAR_NAK
1150 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1151 MGC_M_CSR0_RXPKTRDY)))
1152#else
1153 !(value & MGC_M_CSR0_RXPKTRDY))
1154#endif
1155 musb_rx_req(s, ep);
1156 break;
1157
1158 case MUSB_HDRC_RXMAXP:
1159 s->ep[ep].maxp[1] = value;
1160 break;
1161 case MUSB_HDRC_RXCSR:
1162 /* (DMA mode only) */
1163 if (
1164 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1165 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1166 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1167 value |= MGC_M_RXCSR_H_REQPKT;
1168
1169 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1170 s->ep[ep].csr[1] |= value & 0xfeb0;
1171
1172 musb_ep_frame_cancel(&s->ep[ep], 1);
1173
1174 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1175 s->ep[ep].fifolen[1] = 0;
1176 s->ep[ep].fifostart[1] = 0;
1177 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1178 /* If double buffering and we have two packets ready, flush
1179 * only the first one and set up the fifo at the second packet. */
1180 }
1181#ifdef CLEAR_NAK
1182 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1183#else
1184 if (value & MGC_M_RXCSR_H_REQPKT)
1185#endif
1186 musb_rx_req(s, ep);
1187 break;
1188 case MUSB_HDRC_RXCOUNT:
1189 s->ep[ep].rxcount = value;
1190 break;
1191
1192 default:
1193 musb_ep_writeb(s, ep, addr, value & 0xff);
1194 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1195 };
1196}
1197
1198/* Generic control */
c227f099 1199static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
942ac052 1200{
bc24a225 1201 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1202 int ep, i;
1203 uint8_t ret;
1204
1205 switch (addr) {
1206 case MUSB_HDRC_FADDR:
1207 return s->faddr;
1208 case MUSB_HDRC_POWER:
1209 return s->power;
1210 case MUSB_HDRC_INTRUSB:
1211 ret = s->intr;
1212 for (i = 0; i < sizeof(ret) * 8; i ++)
1213 if (ret & (1 << i))
1214 musb_intr_set(s, i, 0);
1215 return ret;
1216 case MUSB_HDRC_INTRUSBE:
1217 return s->mask;
1218 case MUSB_HDRC_INDEX:
1219 return s->idx;
1220 case MUSB_HDRC_TESTMODE:
1221 return 0x00;
1222
1223 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1224 return musb_ep_readb(s, s->idx, addr & 0xf);
1225
1226 case MUSB_HDRC_DEVCTL:
1227 return s->devctl;
1228
1229 case MUSB_HDRC_TXFIFOSZ:
1230 case MUSB_HDRC_RXFIFOSZ:
1231 case MUSB_HDRC_VCTRL:
1232 /* TODO */
1233 return 0x00;
1234
1235 case MUSB_HDRC_HWVERS:
1236 return (1 << 10) | 400;
1237
1238 case (MUSB_HDRC_VCTRL | 1):
1239 case (MUSB_HDRC_HWVERS | 1):
1240 case (MUSB_HDRC_DEVCTL | 1):
1241 return 0x00;
1242
1243 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1244 ep = (addr >> 3) & 0xf;
1245 return musb_busctl_readb(s, ep, addr & 0x7);
1246
1247 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1248 ep = (addr >> 4) & 0xf;
1249 return musb_ep_readb(s, ep, addr & 0xf);
1250
384dce1e
RV		 1251 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1252 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1253 return musb_read_fifo(s->ep + ep);
1254
942ac052 1255 default:
384dce1e 1256 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1257 return 0x00;
1258 };
1259}
1260
c227f099 1261static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1262{
bc24a225 1263 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1264 int ep;
1265
1266 switch (addr) {
1267 case MUSB_HDRC_FADDR:
1268 s->faddr = value & 0x7f;
1269 break;
1270 case MUSB_HDRC_POWER:
1271 s->power = (value & 0xef) | (s->power & 0x10);
1272 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1273 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1274 usb_send_msg(s->port.dev, USB_MSG_RESET);
1275 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1276 if ((value & MGC_M_POWER_HSENAB) &&
1277 s->port.dev->speed == USB_SPEED_HIGH)
1278 s->power |= MGC_M_POWER_HSMODE; /* Success */
1279 /* Restart frame counting. */
1280 }
1281 if (value & MGC_M_POWER_SUSPENDM) {
1282 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1283 * is set, also go into low power mode. Frame counting stops. */
1284 /* XXX: Cleared when the interrupt register is read */
1285 }
1286 if (value & MGC_M_POWER_RESUME) {
1287 /* Wait 20ms and signal resuming on the bus. Frame counting
1288 * restarts. */
1289 }
1290 break;
1291 case MUSB_HDRC_INTRUSB:
1292 break;
1293 case MUSB_HDRC_INTRUSBE:
1294 s->mask = value & 0xff;
1295 break;
1296 case MUSB_HDRC_INDEX:
1297 s->idx = value & 0xf;
1298 break;
1299 case MUSB_HDRC_TESTMODE:
1300 break;
1301
1302 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1303 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1304 break;
1305
1306 case MUSB_HDRC_DEVCTL:
1307 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1308 musb_session_update(s,
1309 !!s->port.dev,
1310 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1311
1312 /* It seems this is the only R/W bit in this register? */
1313 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1314 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1315 break;
1316
1317 case MUSB_HDRC_TXFIFOSZ:
1318 case MUSB_HDRC_RXFIFOSZ:
1319 case MUSB_HDRC_VCTRL:
1320 /* TODO */
1321 break;
1322
1323 case (MUSB_HDRC_VCTRL | 1):
1324 case (MUSB_HDRC_DEVCTL | 1):
1325 break;
1326
1327 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1328 ep = (addr >> 3) & 0xf;
1329 musb_busctl_writeb(s, ep, addr & 0x7, value);
1330 break;
1331
1332 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1333 ep = (addr >> 4) & 0xf;
1334 musb_ep_writeb(s, ep, addr & 0xf, value);
1335 break;
1336
384dce1e
RV		 1337 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1338 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1339 musb_write_fifo(s->ep + ep, value & 0xff);
1340 break;
1341
942ac052 1342 default:
384dce1e
RV		 1343 TRACE("unknown register 0x%02x", (int) addr);
1344 break;
942ac052
AZ		 1345 };
1346}
1347
c227f099 1348static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
942ac052 1349{
bc24a225 1350 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1351 int ep, i;
1352 uint16_t ret;
1353
1354 switch (addr) {
1355 case MUSB_HDRC_INTRTX:
1356 ret = s->tx_intr;
1357 /* Auto clear */
1358 for (i = 0; i < sizeof(ret) * 8; i ++)
1359 if (ret & (1 << i))
1360 musb_tx_intr_set(s, i, 0);
1361 return ret;
1362 case MUSB_HDRC_INTRRX:
1363 ret = s->rx_intr;
1364 /* Auto clear */
1365 for (i = 0; i < sizeof(ret) * 8; i ++)
1366 if (ret & (1 << i))
1367 musb_rx_intr_set(s, i, 0);
1368 return ret;
1369 case MUSB_HDRC_INTRTXE:
1370 return s->tx_mask;
1371 case MUSB_HDRC_INTRRXE:
1372 return s->rx_mask;
1373
1374 case MUSB_HDRC_FRAME:
1375 /* TODO */
1376 return 0x0000;
1377 case MUSB_HDRC_TXFIFOADDR:
1378 return s->ep[s->idx].fifoaddr[0];
1379 case MUSB_HDRC_RXFIFOADDR:
1380 return s->ep[s->idx].fifoaddr[1];
1381
1382 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1383 return musb_ep_readh(s, s->idx, addr & 0xf);
1384
1385 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1386 ep = (addr >> 3) & 0xf;
1387 return musb_busctl_readh(s, ep, addr & 0x7);
1388
1389 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1390 ep = (addr >> 4) & 0xf;
1391 return musb_ep_readh(s, ep, addr & 0xf);
1392
384dce1e
RV		 1393 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1394 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1395 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1396
942ac052
AZ		 1397 default:
1398 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1399 };
1400}
1401
c227f099 1402static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1403{
bc24a225 1404 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1405 int ep;
1406
1407 switch (addr) {
1408 case MUSB_HDRC_INTRTXE:
1409 s->tx_mask = value;
1410 /* XXX: the masks seem to apply on the raising edge like with
1411 * edge-triggered interrupts, thus no need to update. I may be
1412 * wrong though. */
1413 break;
1414 case MUSB_HDRC_INTRRXE:
1415 s->rx_mask = value;
1416 break;
1417
1418 case MUSB_HDRC_FRAME:
1419 /* TODO */
1420 break;
1421 case MUSB_HDRC_TXFIFOADDR:
1422 s->ep[s->idx].fifoaddr[0] = value;
1423 s->ep[s->idx].buf[0] =
384dce1e 1424 s->buf + ((value << 3) & 0x7ff );
942ac052
AZ		 1425 break;
1426 case MUSB_HDRC_RXFIFOADDR:
1427 s->ep[s->idx].fifoaddr[1] = value;
1428 s->ep[s->idx].buf[1] =
384dce1e 1429 s->buf + ((value << 3) & 0x7ff);
942ac052
AZ		 1430 break;
1431
1432 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1433 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1434 break;
1435
1436 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1437 ep = (addr >> 3) & 0xf;
1438 musb_busctl_writeh(s, ep, addr & 0x7, value);
1439 break;
1440
1441 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1442 ep = (addr >> 4) & 0xf;
1443 musb_ep_writeh(s, ep, addr & 0xf, value);
1444 break;
1445
384dce1e
RV		 1446 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1447 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1448 musb_write_fifo(s->ep + ep, value & 0xff);
1449 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1450 break;
1451
942ac052
AZ		 1452 default:
1453 musb_writeb(s, addr, value & 0xff);
1454 musb_writeb(s, addr | 1, value >> 8);
1455 };
1456}
1457
c227f099 1458static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
942ac052 1459{
bc24a225 1460 MUSBState *s = (MUSBState *) opaque;
384dce1e 1461 int ep;
942ac052
AZ		 1462
1463 switch (addr) {
1464 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1465 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1466 return ( musb_read_fifo(s->ep + ep) |
1467 musb_read_fifo(s->ep + ep) << 8 |
1468 musb_read_fifo(s->ep + ep) << 16 |
1469 musb_read_fifo(s->ep + ep) << 24 );
942ac052 1470 default:
384dce1e 1471 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1472 return 0x00000000;
1473 };
1474}
1475
c227f099 1476static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1477{
bc24a225 1478 MUSBState *s = (MUSBState *) opaque;
384dce1e 1479 int ep;
942ac052
AZ		 1480
1481 switch (addr) {
1482 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1483 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1484 musb_write_fifo(s->ep + ep, value & 0xff);
1485 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1486 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1487 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
942ac052 1488 break;
942ac052 1489 default:
384dce1e
RV		 1490 TRACE("unknown register 0x%02x", (int) addr);
1491 break;
942ac052
AZ		 1492 };
1493}
1494
d60efc6b 1495CPUReadMemoryFunc * const musb_read[] = {
942ac052
AZ		 1496 musb_readb,
1497 musb_readh,
1498 musb_readw,
1499};
1500
d60efc6b 1501CPUWriteMemoryFunc * const musb_write[] = {
942ac052
AZ		 1502 musb_writeb,
1503 musb_writeh,
1504 musb_writew,
1505};
Qemu copy for testing