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musb: get musb state via container_of()
[qemu.git] / hw / usb-musb.c
CommitLineData
942ac052
AZ		 1/*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
fad6cb1a 18 * You should have received a copy of the GNU General Public License along
8167ee88 19 * with this program; if not, see <http://www.gnu.org/licenses/>.
942ac052
AZ		 20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23#include "qemu-common.h"
24#include "qemu-timer.h"
25#include "usb.h"
26#include "irq.h"
384dce1e 27#include "hw.h"
942ac052
AZ		 28
29/* Common USB registers */
30#define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31#define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33#define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34#define MUSB_HDRC_INTRRX 0x04
35#define MUSB_HDRC_INTRTXE 0x06
36#define MUSB_HDRC_INTRRXE 0x08
37#define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38#define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39#define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40#define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41#define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43/* Per-EP registers in indexed mode */
44#define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46/* EP FIFOs */
47#define MUSB_HDRC_FIFO 0x20
48
49/* Additional Control Registers */
50#define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52/* These are indexed */
53#define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54#define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55#define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56#define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58/* Some more registers */
59#define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60#define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62/* Added in HDRC 1.9(?) & MHDRC 1.4 */
63/* ULPI pass-through */
64#define MUSB_HDRC_ULPI_VBUSCTL 0x70
65#define MUSB_HDRC_ULPI_REGDATA 0x74
66#define MUSB_HDRC_ULPI_REGADDR 0x75
67#define MUSB_HDRC_ULPI_REGCTL 0x76
68
69/* Extended config & PHY control */
70#define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71#define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72#define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73#define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74#define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75#define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76#define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78/* Per-EP BUSCTL registers */
79#define MUSB_HDRC_BUSCTL 0x80
80
81/* Per-EP registers in flat mode */
82#define MUSB_HDRC_EP 0x100
83
84/* offsets to registers in flat model */
85#define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86#define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87#define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88#define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89#define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90#define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91#define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92#define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93#define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94#define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95#define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96#define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97#define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98#define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99#define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101/* "Bus control" registers */
102#define MUSB_HDRC_TXFUNCADDR 0x00
103#define MUSB_HDRC_TXHUBADDR 0x02
104#define MUSB_HDRC_TXHUBPORT 0x03
105
106#define MUSB_HDRC_RXFUNCADDR 0x04
107#define MUSB_HDRC_RXHUBADDR 0x06
108#define MUSB_HDRC_RXHUBPORT 0x07
109
110/*
111 * MUSBHDRC Register bit masks
112 */
113
114/* POWER */
115#define MGC_M_POWER_ISOUPDATE 0x80
116#define MGC_M_POWER_SOFTCONN 0x40
117#define MGC_M_POWER_HSENAB 0x20
118#define MGC_M_POWER_HSMODE 0x10
119#define MGC_M_POWER_RESET 0x08
120#define MGC_M_POWER_RESUME 0x04
121#define MGC_M_POWER_SUSPENDM 0x02
122#define MGC_M_POWER_ENSUSPEND 0x01
123
124/* INTRUSB */
125#define MGC_M_INTR_SUSPEND 0x01
126#define MGC_M_INTR_RESUME 0x02
127#define MGC_M_INTR_RESET 0x04
128#define MGC_M_INTR_BABBLE 0x04
129#define MGC_M_INTR_SOF 0x08
130#define MGC_M_INTR_CONNECT 0x10
131#define MGC_M_INTR_DISCONNECT 0x20
132#define MGC_M_INTR_SESSREQ 0x40
133#define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134#define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136/* DEVCTL */
137#define MGC_M_DEVCTL_BDEVICE 0x80
138#define MGC_M_DEVCTL_FSDEV 0x40
139#define MGC_M_DEVCTL_LSDEV 0x20
140#define MGC_M_DEVCTL_VBUS 0x18
141#define MGC_S_DEVCTL_VBUS 3
142#define MGC_M_DEVCTL_HM 0x04
143#define MGC_M_DEVCTL_HR 0x02
144#define MGC_M_DEVCTL_SESSION 0x01
145
146/* TESTMODE */
147#define MGC_M_TEST_FORCE_HOST 0x80
148#define MGC_M_TEST_FIFO_ACCESS 0x40
149#define MGC_M_TEST_FORCE_FS 0x20
150#define MGC_M_TEST_FORCE_HS 0x10
151#define MGC_M_TEST_PACKET 0x08
152#define MGC_M_TEST_K 0x04
153#define MGC_M_TEST_J 0x02
154#define MGC_M_TEST_SE0_NAK 0x01
155
156/* CSR0 */
157#define MGC_M_CSR0_FLUSHFIFO 0x0100
158#define MGC_M_CSR0_TXPKTRDY 0x0002
159#define MGC_M_CSR0_RXPKTRDY 0x0001
160
161/* CSR0 in Peripheral mode */
162#define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163#define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164#define MGC_M_CSR0_P_SENDSTALL 0x0020
165#define MGC_M_CSR0_P_SETUPEND 0x0010
166#define MGC_M_CSR0_P_DATAEND 0x0008
167#define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169/* CSR0 in Host mode */
170#define MGC_M_CSR0_H_NO_PING 0x0800
171#define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172#define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173#define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174#define MGC_M_CSR0_H_STATUSPKT 0x0040
175#define MGC_M_CSR0_H_REQPKT 0x0020
176#define MGC_M_CSR0_H_ERROR 0x0010
177#define MGC_M_CSR0_H_SETUPPKT 0x0008
178#define MGC_M_CSR0_H_RXSTALL 0x0004
179
180/* CONFIGDATA */
181#define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182#define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183#define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184#define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185#define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186#define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187#define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188#define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190/* TXCSR in Peripheral and Host mode */
191#define MGC_M_TXCSR_AUTOSET 0x8000
192#define MGC_M_TXCSR_ISO 0x4000
193#define MGC_M_TXCSR_MODE 0x2000
194#define MGC_M_TXCSR_DMAENAB 0x1000
195#define MGC_M_TXCSR_FRCDATATOG 0x0800
196#define MGC_M_TXCSR_DMAMODE 0x0400
197#define MGC_M_TXCSR_CLRDATATOG 0x0040
198#define MGC_M_TXCSR_FLUSHFIFO 0x0008
199#define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200#define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202/* TXCSR in Peripheral mode */
203#define MGC_M_TXCSR_P_INCOMPTX 0x0080
204#define MGC_M_TXCSR_P_SENTSTALL 0x0020
205#define MGC_M_TXCSR_P_SENDSTALL 0x0010
206#define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208/* TXCSR in Host mode */
209#define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210#define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211#define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212#define MGC_M_TXCSR_H_RXSTALL 0x0020
213#define MGC_M_TXCSR_H_ERROR 0x0004
214
215/* RXCSR in Peripheral and Host mode */
216#define MGC_M_RXCSR_AUTOCLEAR 0x8000
217#define MGC_M_RXCSR_DMAENAB 0x2000
218#define MGC_M_RXCSR_DISNYET 0x1000
219#define MGC_M_RXCSR_DMAMODE 0x0800
220#define MGC_M_RXCSR_INCOMPRX 0x0100
221#define MGC_M_RXCSR_CLRDATATOG 0x0080
222#define MGC_M_RXCSR_FLUSHFIFO 0x0010
223#define MGC_M_RXCSR_DATAERROR 0x0008
224#define MGC_M_RXCSR_FIFOFULL 0x0002
225#define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227/* RXCSR in Peripheral mode */
228#define MGC_M_RXCSR_P_ISO 0x4000
229#define MGC_M_RXCSR_P_SENTSTALL 0x0040
230#define MGC_M_RXCSR_P_SENDSTALL 0x0020
231#define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233/* RXCSR in Host mode */
234#define MGC_M_RXCSR_H_AUTOREQ 0x4000
235#define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236#define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237#define MGC_M_RXCSR_H_RXSTALL 0x0040
238#define MGC_M_RXCSR_H_REQPKT 0x0020
239#define MGC_M_RXCSR_H_ERROR 0x0004
240
241/* HUBADDR */
242#define MGC_M_HUBADDR_MULTI_TT 0x80
243
244/* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245#define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246#define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247#define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248#define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249#define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250#define MGC_M_ULPI_REGCTL_REG 0x01
251
384dce1e
RV		 252/* #define MUSB_DEBUG */
253
254#ifdef MUSB_DEBUG
255#define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257#else
258#define TRACE(...)
259#endif
260
261
618c169b
GH		 262static void musb_attach(USBPort *port);
263static void musb_detach(USBPort *port);
942ac052 264
0d86d2be
GH		 265static USBPortOps musb_port_ops = {
266 .attach = musb_attach,
618c169b 267 .detach = musb_detach,
0d86d2be
GH		 268};
269
5dc1672b
GH		 270typedef struct MUSBPacket MUSBPacket;
271typedef struct MUSBEndPoint MUSBEndPoint;
272
273struct MUSBPacket {
274 USBPacket p;
275 MUSBEndPoint *ep;
276 int dir;
277};
278
279struct MUSBEndPoint {
bc24a225
PB		 280 uint16_t faddr[2];
281 uint8_t haddr[2];
282 uint8_t hport[2];
283 uint16_t csr[2];
284 uint16_t maxp[2];
285 uint16_t rxcount;
286 uint8_t type[2];
287 uint8_t interval[2];
288 uint8_t config;
289 uint8_t fifosize;
290 int timeout[2]; /* Always in microframes */
291
384dce1e 292 uint8_t *buf[2];
bc24a225
PB		 293 int fifolen[2];
294 int fifostart[2];
295 int fifoaddr[2];
5dc1672b 296 MUSBPacket packey[2];
bc24a225
PB		 297 int status[2];
298 int ext_size[2];
299
300 /* For callbacks' use */
301 int epnum;
302 int interrupt[2];
303 MUSBState *musb;
304 USBCallback *delayed_cb[2];
305 QEMUTimer *intv_timer[2];
5dc1672b 306};
bc24a225
PB		 307
308struct MUSBState {
942ac052 309 qemu_irq *irqs;
b2317837 310 USBBus bus;
942ac052
AZ		 311 USBPort port;
312
313 int idx;
314 uint8_t devctl;
315 uint8_t power;
316 uint8_t faddr;
317
318 uint8_t intr;
319 uint8_t mask;
320 uint16_t tx_intr;
321 uint16_t tx_mask;
322 uint16_t rx_intr;
323 uint16_t rx_mask;
324
325 int setup_len;
326 int session;
327
384dce1e 328 uint8_t buf[0x8000];
942ac052 329
942ac052
AZ		 330 /* Duplicating the world since 2008!... probably we should have 32
331 * logical, single endpoints instead. */
bc24a225 332 MUSBEndPoint ep[16];
5dc1672b
GH		 333};
334
335struct MUSBState *musb_init(qemu_irq *irqs)
942ac052 336{
bc24a225 337 MUSBState *s = qemu_mallocz(sizeof(*s));
942ac052
AZ		 338 int i;
339
340 s->irqs = irqs;
341
342 s->faddr = 0x00;
343 s->power = MGC_M_POWER_HSENAB;
344 s->tx_intr = 0x0000;
345 s->rx_intr = 0x0000;
346 s->tx_mask = 0xffff;
347 s->rx_mask = 0xffff;
348 s->intr = 0x00;
349 s->mask = 0x06;
350 s->idx = 0;
351
352 /* TODO: _DW */
353 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
354 for (i = 0; i < 16; i ++) {
355 s->ep[i].fifosize = 64;
356 s->ep[i].maxp[0] = 0x40;
357 s->ep[i].maxp[1] = 0x40;
358 s->ep[i].musb = s;
359 s->ep[i].epnum = i;
360 }
361
b2317837 362 usb_bus_new(&s->bus, NULL /* FIXME */);
ace1318b 363 usb_register_port(&s->bus, &s->port, s, 0, &musb_port_ops,
843d4e0c 364 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
c7a2196a 365 usb_port_location(&s->port, NULL, 1);
942ac052
AZ		 366
367 return s;
368}
369
bc24a225 370static void musb_vbus_set(MUSBState *s, int level)
942ac052
AZ		 371{
372 if (level)
373 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
374 else
375 s->devctl &= ~MGC_M_DEVCTL_VBUS;
376
377 qemu_set_irq(s->irqs[musb_set_vbus], level);
378}
379
bc24a225 380static void musb_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 381{
382 if (!level) {
383 s->intr &= ~(1 << line);
384 qemu_irq_lower(s->irqs[line]);
385 } else if (s->mask & (1 << line)) {
386 s->intr |= 1 << line;
387 qemu_irq_raise(s->irqs[line]);
388 }
389}
390
bc24a225 391static void musb_tx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 392{
393 if (!level) {
394 s->tx_intr &= ~(1 << line);
395 if (!s->tx_intr)
396 qemu_irq_lower(s->irqs[musb_irq_tx]);
397 } else if (s->tx_mask & (1 << line)) {
398 s->tx_intr |= 1 << line;
399 qemu_irq_raise(s->irqs[musb_irq_tx]);
400 }
401}
402
bc24a225 403static void musb_rx_intr_set(MUSBState *s, int line, int level)
942ac052
AZ		 404{
405 if (line) {
406 if (!level) {
407 s->rx_intr &= ~(1 << line);
408 if (!s->rx_intr)
409 qemu_irq_lower(s->irqs[musb_irq_rx]);
410 } else if (s->rx_mask & (1 << line)) {
411 s->rx_intr |= 1 << line;
412 qemu_irq_raise(s->irqs[musb_irq_rx]);
413 }
414 } else
415 musb_tx_intr_set(s, line, level);
416}
417
bc24a225 418uint32_t musb_core_intr_get(MUSBState *s)
942ac052
AZ		 419{
420 return (s->rx_intr << 15) | s->tx_intr;
421}
422
bc24a225 423void musb_core_intr_clear(MUSBState *s, uint32_t mask)
942ac052
AZ		 424{
425 if (s->rx_intr) {
426 s->rx_intr &= mask >> 15;
427 if (!s->rx_intr)
428 qemu_irq_lower(s->irqs[musb_irq_rx]);
429 }
430
431 if (s->tx_intr) {
432 s->tx_intr &= mask & 0xffff;
433 if (!s->tx_intr)
434 qemu_irq_lower(s->irqs[musb_irq_tx]);
435 }
436}
437
bc24a225 438void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
942ac052
AZ		 439{
440 s->ep[epnum].ext_size[!is_tx] = size;
441 s->ep[epnum].fifostart[0] = 0;
442 s->ep[epnum].fifostart[1] = 0;
443 s->ep[epnum].fifolen[0] = 0;
444 s->ep[epnum].fifolen[1] = 0;
445}
446
bc24a225 447static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
942ac052
AZ		 448{
449 int detect_prev = prev_dev && prev_sess;
450 int detect = !!s->port.dev && s->session;
451
452 if (detect && !detect_prev) {
453 /* Let's skip the ID pin sense and VBUS sense formalities and
454 * and signal a successful SRP directly. This should work at least
455 * for the Linux driver stack. */
456 musb_intr_set(s, musb_irq_connect, 1);
457
458 if (s->port.dev->speed == USB_SPEED_LOW) {
459 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
460 s->devctl |= MGC_M_DEVCTL_LSDEV;
461 } else {
462 s->devctl |= MGC_M_DEVCTL_FSDEV;
463 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
464 }
465
466 /* A-mode? */
467 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
468
469 /* Host-mode bit? */
470 s->devctl |= MGC_M_DEVCTL_HM;
471#if 1
472 musb_vbus_set(s, 1);
473#endif
474 } else if (!detect && detect_prev) {
475#if 1
476 musb_vbus_set(s, 0);
477#endif
478 }
479}
480
481/* Attach or detach a device on our only port. */
618c169b 482static void musb_attach(USBPort *port)
942ac052 483{
bc24a225 484 MUSBState *s = (MUSBState *) port->opaque;
942ac052 485
618c169b
GH		 486 musb_intr_set(s, musb_irq_vbus_request, 1);
487 musb_session_update(s, 0, s->session);
488}
942ac052 489
618c169b
GH		 490static void musb_detach(USBPort *port)
491{
492 MUSBState *s = (MUSBState *) port->opaque;
942ac052 493
618c169b
GH		 494 musb_intr_set(s, musb_irq_disconnect, 1);
495 musb_session_update(s, 1, s->session);
942ac052
AZ		 496}
497
498static inline void musb_cb_tick0(void *opaque)
499{
bc24a225 500 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 501
5dc1672b 502 ep->delayed_cb[0](&ep->packey[0].p, opaque);
942ac052
AZ		 503}
504
505static inline void musb_cb_tick1(void *opaque)
506{
bc24a225 507 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 508
5dc1672b 509 ep->delayed_cb[1](&ep->packey[1].p, opaque);
942ac052
AZ		 510}
511
512#define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
513
514static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir)
515{
bc24a225 516 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052
AZ		 517 int timeout = 0;
518
519 if (ep->status[dir] == USB_RET_NAK)
520 timeout = ep->timeout[dir];
521 else if (ep->interrupt[dir])
522 timeout = 8;
523 else
524 return musb_cb_tick(opaque);
525
526 if (!ep->intv_timer[dir])
74475455 527 ep->intv_timer[dir] = qemu_new_timer_ns(vm_clock, musb_cb_tick, opaque);
942ac052 528
74475455 529 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock_ns(vm_clock) +
6ee093c9 530 muldiv64(timeout, get_ticks_per_sec(), 8000));
942ac052
AZ		 531}
532
533static void musb_schedule0_cb(USBPacket *packey, void *opaque)
534{
535 return musb_schedule_cb(packey, opaque, 0);
536}
537
538static void musb_schedule1_cb(USBPacket *packey, void *opaque)
539{
540 return musb_schedule_cb(packey, opaque, 1);
541}
542
543static int musb_timeout(int ttype, int speed, int val)
544{
545#if 1
546 return val << 3;
547#endif
548
549 switch (ttype) {
550 case USB_ENDPOINT_XFER_CONTROL:
551 if (val < 2)
552 return 0;
553 else if (speed == USB_SPEED_HIGH)
554 return 1 << (val - 1);
555 else
556 return 8 << (val - 1);
557
558 case USB_ENDPOINT_XFER_INT:
559 if (speed == USB_SPEED_HIGH)
560 if (val < 2)
561 return 0;
562 else
563 return 1 << (val - 1);
564 else
565 return val << 3;
566
567 case USB_ENDPOINT_XFER_BULK:
568 case USB_ENDPOINT_XFER_ISOC:
569 if (val < 2)
570 return 0;
571 else if (speed == USB_SPEED_HIGH)
572 return 1 << (val - 1);
573 else
574 return 8 << (val - 1);
575 /* TODO: what with low-speed Bulk and Isochronous? */
576 }
577
2ac71179 578 hw_error("bad interval\n");
942ac052
AZ		 579}
580
bc24a225 581static inline void musb_packet(MUSBState *s, MUSBEndPoint *ep,
942ac052
AZ		 582 int epnum, int pid, int len, USBCallback cb, int dir)
583{
584 int ret;
585 int idx = epnum && dir;
586 int ttype;
587
588 /* ep->type[0,1] contains:
589 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
590 * in bits 5:4 the transfer type (BULK / INT)
591 * in bits 3:0 the EP num
592 */
593 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
594
595 ep->timeout[dir] = musb_timeout(ttype,
596 ep->type[idx] >> 6, ep->interval[idx]);
597 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
598 ep->delayed_cb[dir] = cb;
599 cb = dir ? musb_schedule1_cb : musb_schedule0_cb;
600
5dc1672b 601 ep->packey[dir].p.pid = pid;
942ac052 602 /* A wild guess on the FADDR semantics... */
5dc1672b
GH		 603 ep->packey[dir].p.devaddr = ep->faddr[idx];
604 ep->packey[dir].p.devep = ep->type[idx] & 0xf;
605 ep->packey[dir].p.data = (void *) ep->buf[idx];
606 ep->packey[dir].p.len = len;
607 ep->packey[dir].p.complete_cb = cb;
608 ep->packey[dir].p.complete_opaque = ep;
609 ep->packey[dir].ep = ep;
610 ep->packey[dir].dir = dir;
942ac052
AZ		 611
612 if (s->port.dev)
5dc1672b 613 ret = s->port.dev->info->handle_packet(s->port.dev, &ep->packey[dir].p);
942ac052
AZ		 614 else
615 ret = USB_RET_NODEV;
616
617 if (ret == USB_RET_ASYNC) {
618 ep->status[dir] = len;
619 return;
620 }
621
622 ep->status[dir] = ret;
5dc1672b 623 usb_packet_complete(&ep->packey[dir].p);
942ac052
AZ		 624}
625
626static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
627{
628 /* Unfortunately we can't use packey->devep because that's the remote
629 * endpoint number and may be different than our local. */
bc24a225 630 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 631 int epnum = ep->epnum;
bc24a225 632 MUSBState *s = ep->musb;
942ac052
AZ		 633
634 ep->fifostart[0] = 0;
635 ep->fifolen[0] = 0;
636#ifdef CLEAR_NAK
637 if (ep->status[0] != USB_RET_NAK) {
638#endif
639 if (epnum)
640 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
641 else
642 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
643#ifdef CLEAR_NAK
644 }
645#endif
646
647 /* Clear all of the error bits first */
648 if (epnum)
649 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
650 MGC_M_TXCSR_H_NAKTIMEOUT);
651 else
652 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
653 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
654
655 if (ep->status[0] == USB_RET_STALL) {
656 /* Command not supported by target! */
657 ep->status[0] = 0;
658
659 if (epnum)
660 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
661 else
662 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
663 }
664
665 if (ep->status[0] == USB_RET_NAK) {
666 ep->status[0] = 0;
667
668 /* NAK timeouts are only generated in Bulk transfers and
669 * Data-errors in Isochronous. */
670 if (ep->interrupt[0]) {
671 return;
672 }
673
674 if (epnum)
675 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
676 else
677 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
678 }
679
680 if (ep->status[0] < 0) {
681 if (ep->status[0] == USB_RET_BABBLE)
682 musb_intr_set(s, musb_irq_rst_babble, 1);
683
684 /* Pretend we've tried three times already and failed (in
685 * case of USB_TOKEN_SETUP). */
686 if (epnum)
687 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
688 else
689 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
690
691 musb_tx_intr_set(s, epnum, 1);
692 return;
693 }
694 /* TODO: check len for over/underruns of an OUT packet? */
695
696#ifdef SETUPLEN_HACK
697 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
698 s->setup_len = ep->packey[0].data[6];
699#endif
700
701 /* In DMA mode: if no error, assert DMA request for this EP,
702 * and skip the interrupt. */
703 musb_tx_intr_set(s, epnum, 1);
704}
705
706static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
707{
708 /* Unfortunately we can't use packey->devep because that's the remote
709 * endpoint number and may be different than our local. */
bc24a225 710 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
942ac052 711 int epnum = ep->epnum;
bc24a225 712 MUSBState *s = ep->musb;
942ac052
AZ		 713
714 ep->fifostart[1] = 0;
715 ep->fifolen[1] = 0;
716
717#ifdef CLEAR_NAK
718 if (ep->status[1] != USB_RET_NAK) {
719#endif
720 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
721 if (!epnum)
722 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
723#ifdef CLEAR_NAK
724 }
725#endif
726
727 /* Clear all of the imaginable error bits first */
728 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
729 MGC_M_RXCSR_DATAERROR);
730 if (!epnum)
731 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
732 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
733
734 if (ep->status[1] == USB_RET_STALL) {
735 ep->status[1] = 0;
736 packey->len = 0;
737
738 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
739 if (!epnum)
740 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
741 }
742
743 if (ep->status[1] == USB_RET_NAK) {
744 ep->status[1] = 0;
745
746 /* NAK timeouts are only generated in Bulk transfers and
747 * Data-errors in Isochronous. */
748 if (ep->interrupt[1])
749 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
750 packey->len, musb_rx_packet_complete, 1);
751
752 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
753 if (!epnum)
754 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
755 }
756
757 if (ep->status[1] < 0) {
758 if (ep->status[1] == USB_RET_BABBLE) {
759 musb_intr_set(s, musb_irq_rst_babble, 1);
760 return;
761 }
762
763 /* Pretend we've tried three times already and failed (in
764 * case of a control transfer). */
765 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
766 if (!epnum)
767 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
768
769 musb_rx_intr_set(s, epnum, 1);
770 return;
771 }
772 /* TODO: check len for over/underruns of an OUT packet? */
773 /* TODO: perhaps make use of e->ext_size[1] here. */
774
775 packey->len = ep->status[1];
776
777 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
778 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
779 if (!epnum)
780 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
781
782 ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
783 /* In DMA mode: assert DMA request for this EP */
784 }
785
786 /* Only if DMA has not been asserted */
787 musb_rx_intr_set(s, epnum, 1);
788}
789
bc24a225 790static void musb_tx_rdy(MUSBState *s, int epnum)
942ac052 791{
bc24a225 792 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 793 int pid;
794 int total, valid = 0;
384dce1e 795 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
942ac052
AZ		 796 ep->fifostart[0] += ep->fifolen[0];
797 ep->fifolen[0] = 0;
798
799 /* XXX: how's the total size of the packet retrieved exactly in
800 * the generic case? */
801 total = ep->maxp[0] & 0x3ff;
802
803 if (ep->ext_size[0]) {
804 total = ep->ext_size[0];
805 ep->ext_size[0] = 0;
806 valid = 1;
807 }
808
809 /* If the packet is not fully ready yet, wait for a next segment. */
384dce1e 810 if (epnum && (ep->fifostart[0]) < total)
942ac052
AZ		 811 return;
812
813 if (!valid)
384dce1e 814 total = ep->fifostart[0];
942ac052
AZ		 815
816 pid = USB_TOKEN_OUT;
817 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
818 pid = USB_TOKEN_SETUP;
384dce1e
RV		 819 if (total != 8) {
820 TRACE("illegal SETUPPKT length of %i bytes", total);
821 }
942ac052
AZ		 822 /* Controller should retry SETUP packets three times on errors
823 * but it doesn't make sense for us to do that. */
824 }
825
826 return musb_packet(s, ep, epnum, pid,
827 total, musb_tx_packet_complete, 0);
828}
829
bc24a225 830static void musb_rx_req(MUSBState *s, int epnum)
942ac052 831{
bc24a225 832 MUSBEndPoint *ep = s->ep + epnum;
942ac052
AZ		 833 int total;
834
835 /* If we already have a packet, which didn't fit into the
836 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
5dc1672b 837 if (ep->packey[1].p.pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
384dce1e 838 (ep->fifostart[1]) + ep->rxcount <
5dc1672b 839 ep->packey[1].p.len) {
384dce1e
RV		 840 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
841 ep->fifostart[1] += ep->rxcount;
942ac052
AZ		 842 ep->fifolen[1] = 0;
843
5dc1672b 844 ep->rxcount = MIN(ep->packey[0].p.len - (ep->fifostart[1]),
942ac052
AZ		 845 ep->maxp[1]);
846
847 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
848 if (!epnum)
849 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
850
851 /* Clear all of the error bits first */
852 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
853 MGC_M_RXCSR_DATAERROR);
854 if (!epnum)
855 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
856 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
857
858 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
859 if (!epnum)
860 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
861 musb_rx_intr_set(s, epnum, 1);
862 return;
863 }
864
865 /* The driver sets maxp[1] to 64 or less because it knows the hardware
866 * FIFO is this deep. Bigger packets get split in
867 * usb_generic_handle_packet but we can also do the splitting locally
868 * for performance. It turns out we can also have a bigger FIFO and
869 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
870 * OK with single packets of even 32KB and we avoid splitting, however
871 * usb_msd.c sometimes sends a packet bigger than what Linux expects
872 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
873 * hides this overrun from Linux. Up to 4096 everything is fine
874 * though. Currently this is disabled.
875 *
876 * XXX: mind ep->fifosize. */
877 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
878
879#ifdef SETUPLEN_HACK
880 /* Why should *we* do that instead of Linux? */
881 if (!epnum) {
5dc1672b 882 if (ep->packey[0].p.devaddr == 2) {
942ac052 883 total = MIN(s->setup_len, 8);
5dc1672b 884 } else {
942ac052 885 total = MIN(s->setup_len, 64);
5dc1672b 886 }
942ac052
AZ		 887 s->setup_len -= total;
888 }
889#endif
890
891 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
892 total, musb_rx_packet_complete, 1);
893}
894
384dce1e
RV		 895static uint8_t musb_read_fifo(MUSBEndPoint *ep)
896{
897 uint8_t value;
898 if (ep->fifolen[1] >= 64) {
899 /* We have a FIFO underrun */
900 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
901 return 0x00000000;
902 }
903 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
904 * (if AUTOREQ is set) */
905
906 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
907 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
908 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
909 return value;
910}
911
912static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
913{
914 TRACE("EP%d = %02x", ep->epnum, value);
915 if (ep->fifolen[0] >= 64) {
916 /* We have a FIFO overrun */
917 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
918 return;
919 }
920
921 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
922 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
923}
924
bc24a225 925static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
942ac052
AZ		 926{
927 if (ep->intv_timer[dir])
928 qemu_del_timer(ep->intv_timer[dir]);
929}
930
931/* Bus control */
932static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
933{
bc24a225 934 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 935
936 switch (addr) {
937 /* For USB2.0 HS hubs only */
938 case MUSB_HDRC_TXHUBADDR:
939 return s->ep[ep].haddr[0];
940 case MUSB_HDRC_TXHUBPORT:
941 return s->ep[ep].hport[0];
942 case MUSB_HDRC_RXHUBADDR:
943 return s->ep[ep].haddr[1];
944 case MUSB_HDRC_RXHUBPORT:
945 return s->ep[ep].hport[1];
946
947 default:
384dce1e 948 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 949 return 0x00;
950 };
951}
952
953static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
954{
bc24a225 955 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 956
957 switch (addr) {
384dce1e
RV		 958 case MUSB_HDRC_TXFUNCADDR:
959 s->ep[ep].faddr[0] = value;
960 break;
961 case MUSB_HDRC_RXFUNCADDR:
962 s->ep[ep].faddr[1] = value;
963 break;
942ac052
AZ		 964 case MUSB_HDRC_TXHUBADDR:
965 s->ep[ep].haddr[0] = value;
966 break;
967 case MUSB_HDRC_TXHUBPORT:
968 s->ep[ep].hport[0] = value;
969 break;
970 case MUSB_HDRC_RXHUBADDR:
971 s->ep[ep].haddr[1] = value;
972 break;
973 case MUSB_HDRC_RXHUBPORT:
974 s->ep[ep].hport[1] = value;
975 break;
976
977 default:
384dce1e
RV		 978 TRACE("unknown register 0x%02x", addr);
979 break;
942ac052
AZ		 980 };
981}
982
983static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
984{
bc24a225 985 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 986
987 switch (addr) {
988 case MUSB_HDRC_TXFUNCADDR:
989 return s->ep[ep].faddr[0];
990 case MUSB_HDRC_RXFUNCADDR:
991 return s->ep[ep].faddr[1];
992
993 default:
994 return musb_busctl_readb(s, ep, addr) |
995 (musb_busctl_readb(s, ep, addr | 1) << 8);
996 };
997}
998
999static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
1000{
bc24a225 1001 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1002
1003 switch (addr) {
1004 case MUSB_HDRC_TXFUNCADDR:
1005 s->ep[ep].faddr[0] = value;
1006 break;
1007 case MUSB_HDRC_RXFUNCADDR:
1008 s->ep[ep].faddr[1] = value;
1009 break;
1010
1011 default:
1012 musb_busctl_writeb(s, ep, addr, value & 0xff);
1013 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
1014 };
1015}
1016
1017/* Endpoint control */
1018static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1019{
bc24a225 1020 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1021
1022 switch (addr) {
1023 case MUSB_HDRC_TXTYPE:
1024 return s->ep[ep].type[0];
1025 case MUSB_HDRC_TXINTERVAL:
1026 return s->ep[ep].interval[0];
1027 case MUSB_HDRC_RXTYPE:
1028 return s->ep[ep].type[1];
1029 case MUSB_HDRC_RXINTERVAL:
1030 return s->ep[ep].interval[1];
1031 case (MUSB_HDRC_FIFOSIZE & ~1):
1032 return 0x00;
1033 case MUSB_HDRC_FIFOSIZE:
1034 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
384dce1e
RV		 1035 case MUSB_HDRC_RXCOUNT:
1036 return s->ep[ep].rxcount;
942ac052
AZ		 1037
1038 default:
384dce1e 1039 TRACE("unknown register 0x%02x", addr);
942ac052
AZ		 1040 return 0x00;
1041 };
1042}
1043
1044static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1045{
bc24a225 1046 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1047
1048 switch (addr) {
1049 case MUSB_HDRC_TXTYPE:
1050 s->ep[ep].type[0] = value;
1051 break;
1052 case MUSB_HDRC_TXINTERVAL:
1053 s->ep[ep].interval[0] = value;
1054 musb_ep_frame_cancel(&s->ep[ep], 0);
1055 break;
1056 case MUSB_HDRC_RXTYPE:
1057 s->ep[ep].type[1] = value;
1058 break;
1059 case MUSB_HDRC_RXINTERVAL:
1060 s->ep[ep].interval[1] = value;
1061 musb_ep_frame_cancel(&s->ep[ep], 1);
1062 break;
1063 case (MUSB_HDRC_FIFOSIZE & ~1):
1064 break;
1065 case MUSB_HDRC_FIFOSIZE:
384dce1e 1066 TRACE("somebody messes with fifosize (now %i bytes)", value);
942ac052
AZ		 1067 s->ep[ep].fifosize = value;
1068 break;
942ac052 1069 default:
384dce1e
RV		 1070 TRACE("unknown register 0x%02x", addr);
1071 break;
942ac052
AZ		 1072 };
1073}
1074
1075static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1076{
bc24a225 1077 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1078 uint16_t ret;
1079
1080 switch (addr) {
1081 case MUSB_HDRC_TXMAXP:
1082 return s->ep[ep].maxp[0];
1083 case MUSB_HDRC_TXCSR:
1084 return s->ep[ep].csr[0];
1085 case MUSB_HDRC_RXMAXP:
1086 return s->ep[ep].maxp[1];
1087 case MUSB_HDRC_RXCSR:
1088 ret = s->ep[ep].csr[1];
1089
1090 /* TODO: This and other bits probably depend on
1091 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1092 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1093 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1094
1095 return ret;
1096 case MUSB_HDRC_RXCOUNT:
1097 return s->ep[ep].rxcount;
1098
1099 default:
1100 return musb_ep_readb(s, ep, addr) |
1101 (musb_ep_readb(s, ep, addr | 1) << 8);
1102 };
1103}
1104
1105static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1106{
bc24a225 1107 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1108
1109 switch (addr) {
1110 case MUSB_HDRC_TXMAXP:
1111 s->ep[ep].maxp[0] = value;
1112 break;
1113 case MUSB_HDRC_TXCSR:
1114 if (ep) {
1115 s->ep[ep].csr[0] &= value & 0xa6;
1116 s->ep[ep].csr[0] |= value & 0xff59;
1117 } else {
1118 s->ep[ep].csr[0] &= value & 0x85;
1119 s->ep[ep].csr[0] |= value & 0xf7a;
1120 }
1121
1122 musb_ep_frame_cancel(&s->ep[ep], 0);
1123
1124 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1125 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1126 s->ep[ep].fifolen[0] = 0;
1127 s->ep[ep].fifostart[0] = 0;
1128 if (ep)
1129 s->ep[ep].csr[0] &=
1130 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1131 else
1132 s->ep[ep].csr[0] &=
1133 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1134 }
1135 if (
1136 (ep &&
1137#ifdef CLEAR_NAK
1138 (value & MGC_M_TXCSR_TXPKTRDY) &&
1139 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1140#else
1141 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1142#endif
1143 (!ep &&
1144#ifdef CLEAR_NAK
1145 (value & MGC_M_CSR0_TXPKTRDY) &&
1146 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1147#else
1148 (value & MGC_M_CSR0_TXPKTRDY)))
1149#endif
1150 musb_tx_rdy(s, ep);
1151 if (!ep &&
1152 (value & MGC_M_CSR0_H_REQPKT) &&
1153#ifdef CLEAR_NAK
1154 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1155 MGC_M_CSR0_RXPKTRDY)))
1156#else
1157 !(value & MGC_M_CSR0_RXPKTRDY))
1158#endif
1159 musb_rx_req(s, ep);
1160 break;
1161
1162 case MUSB_HDRC_RXMAXP:
1163 s->ep[ep].maxp[1] = value;
1164 break;
1165 case MUSB_HDRC_RXCSR:
1166 /* (DMA mode only) */
1167 if (
1168 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1169 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1170 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1171 value |= MGC_M_RXCSR_H_REQPKT;
1172
1173 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1174 s->ep[ep].csr[1] |= value & 0xfeb0;
1175
1176 musb_ep_frame_cancel(&s->ep[ep], 1);
1177
1178 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1179 s->ep[ep].fifolen[1] = 0;
1180 s->ep[ep].fifostart[1] = 0;
1181 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1182 /* If double buffering and we have two packets ready, flush
1183 * only the first one and set up the fifo at the second packet. */
1184 }
1185#ifdef CLEAR_NAK
1186 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1187#else
1188 if (value & MGC_M_RXCSR_H_REQPKT)
1189#endif
1190 musb_rx_req(s, ep);
1191 break;
1192 case MUSB_HDRC_RXCOUNT:
1193 s->ep[ep].rxcount = value;
1194 break;
1195
1196 default:
1197 musb_ep_writeb(s, ep, addr, value & 0xff);
1198 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1199 };
1200}
1201
1202/* Generic control */
c227f099 1203static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
942ac052 1204{
bc24a225 1205 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1206 int ep, i;
1207 uint8_t ret;
1208
1209 switch (addr) {
1210 case MUSB_HDRC_FADDR:
1211 return s->faddr;
1212 case MUSB_HDRC_POWER:
1213 return s->power;
1214 case MUSB_HDRC_INTRUSB:
1215 ret = s->intr;
1216 for (i = 0; i < sizeof(ret) * 8; i ++)
1217 if (ret & (1 << i))
1218 musb_intr_set(s, i, 0);
1219 return ret;
1220 case MUSB_HDRC_INTRUSBE:
1221 return s->mask;
1222 case MUSB_HDRC_INDEX:
1223 return s->idx;
1224 case MUSB_HDRC_TESTMODE:
1225 return 0x00;
1226
1227 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1228 return musb_ep_readb(s, s->idx, addr & 0xf);
1229
1230 case MUSB_HDRC_DEVCTL:
1231 return s->devctl;
1232
1233 case MUSB_HDRC_TXFIFOSZ:
1234 case MUSB_HDRC_RXFIFOSZ:
1235 case MUSB_HDRC_VCTRL:
1236 /* TODO */
1237 return 0x00;
1238
1239 case MUSB_HDRC_HWVERS:
1240 return (1 << 10) | 400;
1241
1242 case (MUSB_HDRC_VCTRL | 1):
1243 case (MUSB_HDRC_HWVERS | 1):
1244 case (MUSB_HDRC_DEVCTL | 1):
1245 return 0x00;
1246
1247 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1248 ep = (addr >> 3) & 0xf;
1249 return musb_busctl_readb(s, ep, addr & 0x7);
1250
1251 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1252 ep = (addr >> 4) & 0xf;
1253 return musb_ep_readb(s, ep, addr & 0xf);
1254
384dce1e
RV		 1255 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1256 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1257 return musb_read_fifo(s->ep + ep);
1258
942ac052 1259 default:
384dce1e 1260 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1261 return 0x00;
1262 };
1263}
1264
c227f099 1265static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1266{
bc24a225 1267 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1268 int ep;
1269
1270 switch (addr) {
1271 case MUSB_HDRC_FADDR:
1272 s->faddr = value & 0x7f;
1273 break;
1274 case MUSB_HDRC_POWER:
1275 s->power = (value & 0xef) | (s->power & 0x10);
1276 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1277 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1278 usb_send_msg(s->port.dev, USB_MSG_RESET);
1279 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1280 if ((value & MGC_M_POWER_HSENAB) &&
1281 s->port.dev->speed == USB_SPEED_HIGH)
1282 s->power |= MGC_M_POWER_HSMODE; /* Success */
1283 /* Restart frame counting. */
1284 }
1285 if (value & MGC_M_POWER_SUSPENDM) {
1286 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1287 * is set, also go into low power mode. Frame counting stops. */
1288 /* XXX: Cleared when the interrupt register is read */
1289 }
1290 if (value & MGC_M_POWER_RESUME) {
1291 /* Wait 20ms and signal resuming on the bus. Frame counting
1292 * restarts. */
1293 }
1294 break;
1295 case MUSB_HDRC_INTRUSB:
1296 break;
1297 case MUSB_HDRC_INTRUSBE:
1298 s->mask = value & 0xff;
1299 break;
1300 case MUSB_HDRC_INDEX:
1301 s->idx = value & 0xf;
1302 break;
1303 case MUSB_HDRC_TESTMODE:
1304 break;
1305
1306 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1307 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1308 break;
1309
1310 case MUSB_HDRC_DEVCTL:
1311 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1312 musb_session_update(s,
1313 !!s->port.dev,
1314 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1315
1316 /* It seems this is the only R/W bit in this register? */
1317 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1318 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1319 break;
1320
1321 case MUSB_HDRC_TXFIFOSZ:
1322 case MUSB_HDRC_RXFIFOSZ:
1323 case MUSB_HDRC_VCTRL:
1324 /* TODO */
1325 break;
1326
1327 case (MUSB_HDRC_VCTRL | 1):
1328 case (MUSB_HDRC_DEVCTL | 1):
1329 break;
1330
1331 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1332 ep = (addr >> 3) & 0xf;
1333 musb_busctl_writeb(s, ep, addr & 0x7, value);
1334 break;
1335
1336 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1337 ep = (addr >> 4) & 0xf;
1338 musb_ep_writeb(s, ep, addr & 0xf, value);
1339 break;
1340
384dce1e
RV		 1341 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1342 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1343 musb_write_fifo(s->ep + ep, value & 0xff);
1344 break;
1345
942ac052 1346 default:
384dce1e
RV		 1347 TRACE("unknown register 0x%02x", (int) addr);
1348 break;
942ac052
AZ		 1349 };
1350}
1351
c227f099 1352static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
942ac052 1353{
bc24a225 1354 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1355 int ep, i;
1356 uint16_t ret;
1357
1358 switch (addr) {
1359 case MUSB_HDRC_INTRTX:
1360 ret = s->tx_intr;
1361 /* Auto clear */
1362 for (i = 0; i < sizeof(ret) * 8; i ++)
1363 if (ret & (1 << i))
1364 musb_tx_intr_set(s, i, 0);
1365 return ret;
1366 case MUSB_HDRC_INTRRX:
1367 ret = s->rx_intr;
1368 /* Auto clear */
1369 for (i = 0; i < sizeof(ret) * 8; i ++)
1370 if (ret & (1 << i))
1371 musb_rx_intr_set(s, i, 0);
1372 return ret;
1373 case MUSB_HDRC_INTRTXE:
1374 return s->tx_mask;
1375 case MUSB_HDRC_INTRRXE:
1376 return s->rx_mask;
1377
1378 case MUSB_HDRC_FRAME:
1379 /* TODO */
1380 return 0x0000;
1381 case MUSB_HDRC_TXFIFOADDR:
1382 return s->ep[s->idx].fifoaddr[0];
1383 case MUSB_HDRC_RXFIFOADDR:
1384 return s->ep[s->idx].fifoaddr[1];
1385
1386 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1387 return musb_ep_readh(s, s->idx, addr & 0xf);
1388
1389 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1390 ep = (addr >> 3) & 0xf;
1391 return musb_busctl_readh(s, ep, addr & 0x7);
1392
1393 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1394 ep = (addr >> 4) & 0xf;
1395 return musb_ep_readh(s, ep, addr & 0xf);
1396
384dce1e
RV		 1397 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1398 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1399 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1400
942ac052
AZ		 1401 default:
1402 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1403 };
1404}
1405
c227f099 1406static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1407{
bc24a225 1408 MUSBState *s = (MUSBState *) opaque;
942ac052
AZ		 1409 int ep;
1410
1411 switch (addr) {
1412 case MUSB_HDRC_INTRTXE:
1413 s->tx_mask = value;
1414 /* XXX: the masks seem to apply on the raising edge like with
1415 * edge-triggered interrupts, thus no need to update. I may be
1416 * wrong though. */
1417 break;
1418 case MUSB_HDRC_INTRRXE:
1419 s->rx_mask = value;
1420 break;
1421
1422 case MUSB_HDRC_FRAME:
1423 /* TODO */
1424 break;
1425 case MUSB_HDRC_TXFIFOADDR:
1426 s->ep[s->idx].fifoaddr[0] = value;
1427 s->ep[s->idx].buf[0] =
384dce1e 1428 s->buf + ((value << 3) & 0x7ff );
942ac052
AZ		 1429 break;
1430 case MUSB_HDRC_RXFIFOADDR:
1431 s->ep[s->idx].fifoaddr[1] = value;
1432 s->ep[s->idx].buf[1] =
384dce1e 1433 s->buf + ((value << 3) & 0x7ff);
942ac052
AZ		 1434 break;
1435
1436 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1437 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1438 break;
1439
1440 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1441 ep = (addr >> 3) & 0xf;
1442 musb_busctl_writeh(s, ep, addr & 0x7, value);
1443 break;
1444
1445 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1446 ep = (addr >> 4) & 0xf;
1447 musb_ep_writeh(s, ep, addr & 0xf, value);
1448 break;
1449
384dce1e
RV		 1450 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1451 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1452 musb_write_fifo(s->ep + ep, value & 0xff);
1453 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1454 break;
1455
942ac052
AZ		 1456 default:
1457 musb_writeb(s, addr, value & 0xff);
1458 musb_writeb(s, addr | 1, value >> 8);
1459 };
1460}
1461
c227f099 1462static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
942ac052 1463{
bc24a225 1464 MUSBState *s = (MUSBState *) opaque;
384dce1e 1465 int ep;
942ac052
AZ		 1466
1467 switch (addr) {
1468 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1469 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1470 return ( musb_read_fifo(s->ep + ep) |
1471 musb_read_fifo(s->ep + ep) << 8 |
1472 musb_read_fifo(s->ep + ep) << 16 |
1473 musb_read_fifo(s->ep + ep) << 24 );
942ac052 1474 default:
384dce1e 1475 TRACE("unknown register 0x%02x", (int) addr);
942ac052
AZ		 1476 return 0x00000000;
1477 };
1478}
1479
c227f099 1480static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
942ac052 1481{
bc24a225 1482 MUSBState *s = (MUSBState *) opaque;
384dce1e 1483 int ep;
942ac052
AZ		 1484
1485 switch (addr) {
1486 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
384dce1e
RV		 1487 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1488 musb_write_fifo(s->ep + ep, value & 0xff);
1489 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1490 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1491 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
942ac052 1492 break;
942ac052 1493 default:
384dce1e
RV		 1494 TRACE("unknown register 0x%02x", (int) addr);
1495 break;
942ac052
AZ		 1496 };
1497}
1498
d60efc6b 1499CPUReadMemoryFunc * const musb_read[] = {
942ac052
AZ		 1500 musb_readb,
1501 musb_readh,
1502 musb_readw,
1503};
1504
d60efc6b 1505CPUWriteMemoryFunc * const musb_write[] = {
942ac052
AZ		 1506 musb_writeb,
1507 musb_writeh,
1508 musb_writew,
1509};
Qemu copy for testing