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Commit | Line | Data |
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bb36d470 FB |
1 | /* |
2 | * USB UHCI controller emulation | |
5fafdf24 | 3 | * |
bb36d470 | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
54f254f9 AL |
6 | * Copyright (c) 2008 Max Krasnyansky |
7 | * Magor rewrite of the UHCI data structures parser and frame processor | |
8 | * Support for fully async operation and multiple outstanding transactions | |
9 | * | |
bb36d470 FB |
10 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
11 | * of this software and associated documentation files (the "Software"), to deal | |
12 | * in the Software without restriction, including without limitation the rights | |
13 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
14 | * copies of the Software, and to permit persons to whom the Software is | |
15 | * furnished to do so, subject to the following conditions: | |
16 | * | |
17 | * The above copyright notice and this permission notice shall be included in | |
18 | * all copies or substantial portions of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
24 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
25 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
26 | * THE SOFTWARE. | |
27 | */ | |
87ecb68b PB |
28 | #include "hw.h" |
29 | #include "usb.h" | |
30 | #include "pci.h" | |
31 | #include "qemu-timer.h" | |
18e08a55 | 32 | #include "usb-uhci.h" |
4f4321c1 | 33 | #include "iov.h" |
df5e66ee | 34 | #include "dma.h" |
bb36d470 FB |
35 | |
36 | //#define DEBUG | |
54f254f9 | 37 | //#define DEBUG_DUMP_DATA |
bb36d470 | 38 | |
96217e31 TS |
39 | #define UHCI_CMD_FGR (1 << 4) |
40 | #define UHCI_CMD_EGSM (1 << 3) | |
bb36d470 FB |
41 | #define UHCI_CMD_GRESET (1 << 2) |
42 | #define UHCI_CMD_HCRESET (1 << 1) | |
43 | #define UHCI_CMD_RS (1 << 0) | |
44 | ||
45 | #define UHCI_STS_HCHALTED (1 << 5) | |
46 | #define UHCI_STS_HCPERR (1 << 4) | |
47 | #define UHCI_STS_HSERR (1 << 3) | |
48 | #define UHCI_STS_RD (1 << 2) | |
49 | #define UHCI_STS_USBERR (1 << 1) | |
50 | #define UHCI_STS_USBINT (1 << 0) | |
51 | ||
52 | #define TD_CTRL_SPD (1 << 29) | |
53 | #define TD_CTRL_ERROR_SHIFT 27 | |
54 | #define TD_CTRL_IOS (1 << 25) | |
55 | #define TD_CTRL_IOC (1 << 24) | |
56 | #define TD_CTRL_ACTIVE (1 << 23) | |
57 | #define TD_CTRL_STALL (1 << 22) | |
58 | #define TD_CTRL_BABBLE (1 << 20) | |
59 | #define TD_CTRL_NAK (1 << 19) | |
60 | #define TD_CTRL_TIMEOUT (1 << 18) | |
61 | ||
9159f679 | 62 | #define UHCI_PORT_SUSPEND (1 << 12) |
bb36d470 FB |
63 | #define UHCI_PORT_RESET (1 << 9) |
64 | #define UHCI_PORT_LSDA (1 << 8) | |
9159f679 | 65 | #define UHCI_PORT_RD (1 << 6) |
bb36d470 FB |
66 | #define UHCI_PORT_ENC (1 << 3) |
67 | #define UHCI_PORT_EN (1 << 2) | |
68 | #define UHCI_PORT_CSC (1 << 1) | |
69 | #define UHCI_PORT_CCS (1 << 0) | |
70 | ||
9159f679 GH |
71 | #define UHCI_PORT_READ_ONLY (0x1bb) |
72 | #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC) | |
73 | ||
bb36d470 FB |
74 | #define FRAME_TIMER_FREQ 1000 |
75 | ||
3200d108 | 76 | #define FRAME_MAX_LOOPS 256 |
bb36d470 FB |
77 | |
78 | #define NB_PORTS 2 | |
79 | ||
54f254f9 | 80 | #ifdef DEBUG |
d0f2c4c6 | 81 | #define DPRINTF printf |
54f254f9 | 82 | |
0bf9e31a | 83 | static const char *pid2str(int pid) |
54f254f9 AL |
84 | { |
85 | switch (pid) { | |
86 | case USB_TOKEN_SETUP: return "SETUP"; | |
87 | case USB_TOKEN_IN: return "IN"; | |
88 | case USB_TOKEN_OUT: return "OUT"; | |
89 | } | |
90 | return "?"; | |
91 | } | |
92 | ||
93 | #else | |
d0f2c4c6 | 94 | #define DPRINTF(...) |
54f254f9 AL |
95 | #endif |
96 | ||
7b5a44c5 GH |
97 | typedef struct UHCIState UHCIState; |
98 | ||
54f254f9 AL |
99 | /* |
100 | * Pending async transaction. | |
101 | * 'packet' must be the first field because completion | |
102 | * handler does "(UHCIAsync *) pkt" cast. | |
103 | */ | |
104 | typedef struct UHCIAsync { | |
105 | USBPacket packet; | |
df5e66ee | 106 | QEMUSGList sgl; |
7b5a44c5 | 107 | UHCIState *uhci; |
ddf6583f | 108 | QTAILQ_ENTRY(UHCIAsync) next; |
54f254f9 AL |
109 | uint32_t td; |
110 | uint32_t token; | |
111 | int8_t valid; | |
8e65b7c0 | 112 | uint8_t isoc; |
54f254f9 | 113 | uint8_t done; |
54f254f9 AL |
114 | } UHCIAsync; |
115 | ||
bb36d470 FB |
116 | typedef struct UHCIPort { |
117 | USBPort port; | |
118 | uint16_t ctrl; | |
bb36d470 FB |
119 | } UHCIPort; |
120 | ||
7b5a44c5 | 121 | struct UHCIState { |
bb36d470 | 122 | PCIDevice dev; |
a03f66e4 | 123 | MemoryRegion io_bar; |
35e4977f | 124 | USBBus bus; /* Note unused when we're a companion controller */ |
bb36d470 FB |
125 | uint16_t cmd; /* cmd register */ |
126 | uint16_t status; | |
127 | uint16_t intr; /* interrupt enable register */ | |
128 | uint16_t frnum; /* frame number */ | |
129 | uint32_t fl_base_addr; /* frame list base address */ | |
130 | uint8_t sof_timing; | |
131 | uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */ | |
8e65b7c0 | 132 | int64_t expire_time; |
bb36d470 FB |
133 | QEMUTimer *frame_timer; |
134 | UHCIPort ports[NB_PORTS]; | |
4d611c9a PB |
135 | |
136 | /* Interrupts that should be raised at the end of the current frame. */ | |
137 | uint32_t pending_int_mask; | |
54f254f9 AL |
138 | |
139 | /* Active packets */ | |
ddf6583f | 140 | QTAILQ_HEAD(,UHCIAsync) async_pending; |
64e58fe5 | 141 | uint8_t num_ports_vmstate; |
35e4977f HG |
142 | |
143 | /* Properties */ | |
144 | char *masterbus; | |
145 | uint32_t firstport; | |
7b5a44c5 | 146 | }; |
bb36d470 FB |
147 | |
148 | typedef struct UHCI_TD { | |
149 | uint32_t link; | |
150 | uint32_t ctrl; /* see TD_CTRL_xxx */ | |
151 | uint32_t token; | |
152 | uint32_t buffer; | |
153 | } UHCI_TD; | |
154 | ||
155 | typedef struct UHCI_QH { | |
156 | uint32_t link; | |
157 | uint32_t el_link; | |
158 | } UHCI_QH; | |
159 | ||
54f254f9 AL |
160 | static UHCIAsync *uhci_async_alloc(UHCIState *s) |
161 | { | |
7267c094 | 162 | UHCIAsync *async = g_malloc(sizeof(UHCIAsync)); |
487414f1 AL |
163 | |
164 | memset(&async->packet, 0, sizeof(async->packet)); | |
7b5a44c5 | 165 | async->uhci = s; |
487414f1 AL |
166 | async->valid = 0; |
167 | async->td = 0; | |
168 | async->token = 0; | |
169 | async->done = 0; | |
8e65b7c0 | 170 | async->isoc = 0; |
4f4321c1 | 171 | usb_packet_init(&async->packet); |
fff23ee9 | 172 | pci_dma_sglist_init(&async->sgl, &s->dev, 1); |
54f254f9 AL |
173 | |
174 | return async; | |
175 | } | |
176 | ||
177 | static void uhci_async_free(UHCIState *s, UHCIAsync *async) | |
178 | { | |
4f4321c1 | 179 | usb_packet_cleanup(&async->packet); |
df5e66ee | 180 | qemu_sglist_destroy(&async->sgl); |
7267c094 | 181 | g_free(async); |
54f254f9 AL |
182 | } |
183 | ||
184 | static void uhci_async_link(UHCIState *s, UHCIAsync *async) | |
185 | { | |
ddf6583f | 186 | QTAILQ_INSERT_HEAD(&s->async_pending, async, next); |
54f254f9 AL |
187 | } |
188 | ||
189 | static void uhci_async_unlink(UHCIState *s, UHCIAsync *async) | |
190 | { | |
ddf6583f | 191 | QTAILQ_REMOVE(&s->async_pending, async, next); |
54f254f9 AL |
192 | } |
193 | ||
194 | static void uhci_async_cancel(UHCIState *s, UHCIAsync *async) | |
195 | { | |
d0f2c4c6 | 196 | DPRINTF("uhci: cancel td 0x%x token 0x%x done %u\n", |
54f254f9 AL |
197 | async->td, async->token, async->done); |
198 | ||
199 | if (!async->done) | |
200 | usb_cancel_packet(&async->packet); | |
201 | uhci_async_free(s, async); | |
202 | } | |
203 | ||
204 | /* | |
205 | * Mark all outstanding async packets as invalid. | |
206 | * This is used for canceling them when TDs are removed by the HCD. | |
207 | */ | |
208 | static UHCIAsync *uhci_async_validate_begin(UHCIState *s) | |
209 | { | |
ddf6583f | 210 | UHCIAsync *async; |
54f254f9 | 211 | |
ddf6583f | 212 | QTAILQ_FOREACH(async, &s->async_pending, next) { |
54f254f9 | 213 | async->valid--; |
54f254f9 AL |
214 | } |
215 | return NULL; | |
216 | } | |
217 | ||
218 | /* | |
219 | * Cancel async packets that are no longer valid | |
220 | */ | |
221 | static void uhci_async_validate_end(UHCIState *s) | |
222 | { | |
ddf6583f | 223 | UHCIAsync *curr, *n; |
54f254f9 | 224 | |
ddf6583f | 225 | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
54f254f9 | 226 | if (curr->valid > 0) { |
54f254f9 AL |
227 | continue; |
228 | } | |
ddf6583f | 229 | uhci_async_unlink(s, curr); |
54f254f9 | 230 | uhci_async_cancel(s, curr); |
54f254f9 AL |
231 | } |
232 | } | |
233 | ||
07771f6f GH |
234 | static void uhci_async_cancel_device(UHCIState *s, USBDevice *dev) |
235 | { | |
236 | UHCIAsync *curr, *n; | |
237 | ||
238 | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { | |
f53c398a GH |
239 | if (!usb_packet_is_inflight(&curr->packet) || |
240 | curr->packet.ep->dev != dev) { | |
07771f6f GH |
241 | continue; |
242 | } | |
243 | uhci_async_unlink(s, curr); | |
244 | uhci_async_cancel(s, curr); | |
245 | } | |
246 | } | |
247 | ||
54f254f9 AL |
248 | static void uhci_async_cancel_all(UHCIState *s) |
249 | { | |
ddf6583f | 250 | UHCIAsync *curr, *n; |
54f254f9 | 251 | |
ddf6583f GH |
252 | QTAILQ_FOREACH_SAFE(curr, &s->async_pending, next, n) { |
253 | uhci_async_unlink(s, curr); | |
54f254f9 | 254 | uhci_async_cancel(s, curr); |
54f254f9 | 255 | } |
54f254f9 AL |
256 | } |
257 | ||
258 | static UHCIAsync *uhci_async_find_td(UHCIState *s, uint32_t addr, uint32_t token) | |
259 | { | |
ddf6583f | 260 | UHCIAsync *async; |
e8ee3c72 AJ |
261 | UHCIAsync *match = NULL; |
262 | int count = 0; | |
263 | ||
264 | /* | |
265 | * We're looking for the best match here. ie both td addr and token. | |
266 | * Otherwise we return last good match. ie just token. | |
267 | * It's ok to match just token because it identifies the transaction | |
268 | * rather well, token includes: device addr, endpoint, size, etc. | |
269 | * | |
270 | * Also since we queue async transactions in reverse order by returning | |
271 | * last good match we restores the order. | |
272 | * | |
273 | * It's expected that we wont have a ton of outstanding transactions. | |
274 | * If we ever do we'd want to optimize this algorithm. | |
275 | */ | |
54f254f9 | 276 | |
ddf6583f | 277 | QTAILQ_FOREACH(async, &s->async_pending, next) { |
e8ee3c72 AJ |
278 | if (async->token == token) { |
279 | /* Good match */ | |
280 | match = async; | |
281 | ||
282 | if (async->td == addr) { | |
283 | /* Best match */ | |
284 | break; | |
54f254f9 AL |
285 | } |
286 | } | |
e8ee3c72 | 287 | count++; |
54f254f9 | 288 | } |
e8ee3c72 AJ |
289 | |
290 | if (count > 64) | |
291 | fprintf(stderr, "uhci: warning lots of async transactions\n"); | |
292 | ||
293 | return match; | |
54f254f9 AL |
294 | } |
295 | ||
bb36d470 FB |
296 | static void uhci_update_irq(UHCIState *s) |
297 | { | |
298 | int level; | |
299 | if (((s->status2 & 1) && (s->intr & (1 << 2))) || | |
300 | ((s->status2 & 2) && (s->intr & (1 << 3))) || | |
301 | ((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || | |
302 | ((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || | |
303 | (s->status & UHCI_STS_HSERR) || | |
304 | (s->status & UHCI_STS_HCPERR)) { | |
305 | level = 1; | |
306 | } else { | |
307 | level = 0; | |
308 | } | |
d537cf6c | 309 | qemu_set_irq(s->dev.irq[3], level); |
bb36d470 FB |
310 | } |
311 | ||
c8075ac3 | 312 | static void uhci_reset(void *opaque) |
bb36d470 | 313 | { |
c8075ac3 | 314 | UHCIState *s = opaque; |
bb36d470 FB |
315 | uint8_t *pci_conf; |
316 | int i; | |
317 | UHCIPort *port; | |
318 | ||
d0f2c4c6 | 319 | DPRINTF("uhci: full reset\n"); |
6f382b5e | 320 | |
bb36d470 FB |
321 | pci_conf = s->dev.config; |
322 | ||
323 | pci_conf[0x6a] = 0x01; /* usb clock */ | |
324 | pci_conf[0x6b] = 0x00; | |
325 | s->cmd = 0; | |
326 | s->status = 0; | |
327 | s->status2 = 0; | |
328 | s->intr = 0; | |
329 | s->fl_base_addr = 0; | |
330 | s->sof_timing = 64; | |
54f254f9 | 331 | |
bb36d470 FB |
332 | for(i = 0; i < NB_PORTS; i++) { |
333 | port = &s->ports[i]; | |
334 | port->ctrl = 0x0080; | |
891fb2cd | 335 | if (port->port.dev && port->port.dev->attached) { |
d28f4e2d | 336 | usb_port_reset(&port->port); |
618c169b | 337 | } |
bb36d470 | 338 | } |
54f254f9 AL |
339 | |
340 | uhci_async_cancel_all(s); | |
bb36d470 FB |
341 | } |
342 | ||
817afc61 | 343 | static void uhci_pre_save(void *opaque) |
b9dc033c AZ |
344 | { |
345 | UHCIState *s = opaque; | |
b9dc033c | 346 | |
6f382b5e | 347 | uhci_async_cancel_all(s); |
b9dc033c AZ |
348 | } |
349 | ||
817afc61 JQ |
350 | static const VMStateDescription vmstate_uhci_port = { |
351 | .name = "uhci port", | |
352 | .version_id = 1, | |
353 | .minimum_version_id = 1, | |
354 | .minimum_version_id_old = 1, | |
355 | .fields = (VMStateField []) { | |
356 | VMSTATE_UINT16(ctrl, UHCIPort), | |
357 | VMSTATE_END_OF_LIST() | |
358 | } | |
359 | }; | |
360 | ||
361 | static const VMStateDescription vmstate_uhci = { | |
362 | .name = "uhci", | |
6881dd5f | 363 | .version_id = 2, |
817afc61 JQ |
364 | .minimum_version_id = 1, |
365 | .minimum_version_id_old = 1, | |
366 | .pre_save = uhci_pre_save, | |
367 | .fields = (VMStateField []) { | |
368 | VMSTATE_PCI_DEVICE(dev, UHCIState), | |
369 | VMSTATE_UINT8_EQUAL(num_ports_vmstate, UHCIState), | |
370 | VMSTATE_STRUCT_ARRAY(ports, UHCIState, NB_PORTS, 1, | |
371 | vmstate_uhci_port, UHCIPort), | |
372 | VMSTATE_UINT16(cmd, UHCIState), | |
373 | VMSTATE_UINT16(status, UHCIState), | |
374 | VMSTATE_UINT16(intr, UHCIState), | |
375 | VMSTATE_UINT16(frnum, UHCIState), | |
376 | VMSTATE_UINT32(fl_base_addr, UHCIState), | |
377 | VMSTATE_UINT8(sof_timing, UHCIState), | |
378 | VMSTATE_UINT8(status2, UHCIState), | |
379 | VMSTATE_TIMER(frame_timer, UHCIState), | |
6881dd5f | 380 | VMSTATE_INT64_V(expire_time, UHCIState, 2), |
817afc61 JQ |
381 | VMSTATE_END_OF_LIST() |
382 | } | |
383 | }; | |
b9dc033c | 384 | |
bb36d470 FB |
385 | static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
386 | { | |
387 | UHCIState *s = opaque; | |
3b46e624 | 388 | |
bb36d470 FB |
389 | addr &= 0x1f; |
390 | switch(addr) { | |
391 | case 0x0c: | |
392 | s->sof_timing = val; | |
393 | break; | |
394 | } | |
395 | } | |
396 | ||
397 | static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) | |
398 | { | |
399 | UHCIState *s = opaque; | |
400 | uint32_t val; | |
401 | ||
402 | addr &= 0x1f; | |
403 | switch(addr) { | |
404 | case 0x0c: | |
405 | val = s->sof_timing; | |
d80cfb3f | 406 | break; |
bb36d470 FB |
407 | default: |
408 | val = 0xff; | |
409 | break; | |
410 | } | |
411 | return val; | |
412 | } | |
413 | ||
414 | static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) | |
415 | { | |
416 | UHCIState *s = opaque; | |
3b46e624 | 417 | |
bb36d470 | 418 | addr &= 0x1f; |
d0f2c4c6 | 419 | DPRINTF("uhci: writew port=0x%04x val=0x%04x\n", addr, val); |
54f254f9 | 420 | |
bb36d470 FB |
421 | switch(addr) { |
422 | case 0x00: | |
423 | if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) { | |
424 | /* start frame processing */ | |
94cc916a GH |
425 | s->expire_time = qemu_get_clock_ns(vm_clock) + |
426 | (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
74475455 | 427 | qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock)); |
52328140 | 428 | s->status &= ~UHCI_STS_HCHALTED; |
467d409f | 429 | } else if (!(val & UHCI_CMD_RS)) { |
52328140 | 430 | s->status |= UHCI_STS_HCHALTED; |
bb36d470 FB |
431 | } |
432 | if (val & UHCI_CMD_GRESET) { | |
433 | UHCIPort *port; | |
bb36d470 FB |
434 | int i; |
435 | ||
436 | /* send reset on the USB bus */ | |
437 | for(i = 0; i < NB_PORTS; i++) { | |
438 | port = &s->ports[i]; | |
d28f4e2d | 439 | usb_device_reset(port->port.dev); |
bb36d470 FB |
440 | } |
441 | uhci_reset(s); | |
442 | return; | |
443 | } | |
5e9ab4c4 | 444 | if (val & UHCI_CMD_HCRESET) { |
bb36d470 FB |
445 | uhci_reset(s); |
446 | return; | |
447 | } | |
448 | s->cmd = val; | |
449 | break; | |
450 | case 0x02: | |
451 | s->status &= ~val; | |
452 | /* XXX: the chip spec is not coherent, so we add a hidden | |
453 | register to distinguish between IOC and SPD */ | |
454 | if (val & UHCI_STS_USBINT) | |
455 | s->status2 = 0; | |
456 | uhci_update_irq(s); | |
457 | break; | |
458 | case 0x04: | |
459 | s->intr = val; | |
460 | uhci_update_irq(s); | |
461 | break; | |
462 | case 0x06: | |
463 | if (s->status & UHCI_STS_HCHALTED) | |
464 | s->frnum = val & 0x7ff; | |
465 | break; | |
466 | case 0x10 ... 0x1f: | |
467 | { | |
468 | UHCIPort *port; | |
469 | USBDevice *dev; | |
470 | int n; | |
471 | ||
472 | n = (addr >> 1) & 7; | |
473 | if (n >= NB_PORTS) | |
474 | return; | |
475 | port = &s->ports[n]; | |
a594cfbf | 476 | dev = port->port.dev; |
891fb2cd | 477 | if (dev && dev->attached) { |
bb36d470 | 478 | /* port reset */ |
5fafdf24 | 479 | if ( (val & UHCI_PORT_RESET) && |
bb36d470 | 480 | !(port->ctrl & UHCI_PORT_RESET) ) { |
d28f4e2d | 481 | usb_device_reset(dev); |
bb36d470 FB |
482 | } |
483 | } | |
9159f679 GH |
484 | port->ctrl &= UHCI_PORT_READ_ONLY; |
485 | port->ctrl |= (val & ~UHCI_PORT_READ_ONLY); | |
bb36d470 | 486 | /* some bits are reset when a '1' is written to them */ |
9159f679 | 487 | port->ctrl &= ~(val & UHCI_PORT_WRITE_CLEAR); |
bb36d470 FB |
488 | } |
489 | break; | |
490 | } | |
491 | } | |
492 | ||
493 | static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) | |
494 | { | |
495 | UHCIState *s = opaque; | |
496 | uint32_t val; | |
497 | ||
498 | addr &= 0x1f; | |
499 | switch(addr) { | |
500 | case 0x00: | |
501 | val = s->cmd; | |
502 | break; | |
503 | case 0x02: | |
504 | val = s->status; | |
505 | break; | |
506 | case 0x04: | |
507 | val = s->intr; | |
508 | break; | |
509 | case 0x06: | |
510 | val = s->frnum; | |
511 | break; | |
512 | case 0x10 ... 0x1f: | |
513 | { | |
514 | UHCIPort *port; | |
515 | int n; | |
516 | n = (addr >> 1) & 7; | |
5fafdf24 | 517 | if (n >= NB_PORTS) |
bb36d470 FB |
518 | goto read_default; |
519 | port = &s->ports[n]; | |
520 | val = port->ctrl; | |
521 | } | |
522 | break; | |
523 | default: | |
524 | read_default: | |
525 | val = 0xff7f; /* disabled port */ | |
526 | break; | |
527 | } | |
54f254f9 | 528 | |
d0f2c4c6 | 529 | DPRINTF("uhci: readw port=0x%04x val=0x%04x\n", addr, val); |
54f254f9 | 530 | |
bb36d470 FB |
531 | return val; |
532 | } | |
533 | ||
534 | static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) | |
535 | { | |
536 | UHCIState *s = opaque; | |
537 | ||
538 | addr &= 0x1f; | |
d0f2c4c6 | 539 | DPRINTF("uhci: writel port=0x%04x val=0x%08x\n", addr, val); |
54f254f9 | 540 | |
bb36d470 FB |
541 | switch(addr) { |
542 | case 0x08: | |
543 | s->fl_base_addr = val & ~0xfff; | |
544 | break; | |
545 | } | |
546 | } | |
547 | ||
548 | static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) | |
549 | { | |
550 | UHCIState *s = opaque; | |
551 | uint32_t val; | |
552 | ||
553 | addr &= 0x1f; | |
554 | switch(addr) { | |
555 | case 0x08: | |
556 | val = s->fl_base_addr; | |
557 | break; | |
558 | default: | |
559 | val = 0xffffffff; | |
560 | break; | |
561 | } | |
562 | return val; | |
563 | } | |
564 | ||
96217e31 TS |
565 | /* signal resume if controller suspended */ |
566 | static void uhci_resume (void *opaque) | |
567 | { | |
568 | UHCIState *s = (UHCIState *)opaque; | |
569 | ||
570 | if (!s) | |
571 | return; | |
572 | ||
573 | if (s->cmd & UHCI_CMD_EGSM) { | |
574 | s->cmd |= UHCI_CMD_FGR; | |
575 | s->status |= UHCI_STS_RD; | |
576 | uhci_update_irq(s); | |
577 | } | |
578 | } | |
579 | ||
618c169b | 580 | static void uhci_attach(USBPort *port1) |
bb36d470 FB |
581 | { |
582 | UHCIState *s = port1->opaque; | |
583 | UHCIPort *port = &s->ports[port1->index]; | |
584 | ||
618c169b GH |
585 | /* set connect status */ |
586 | port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; | |
61064870 | 587 | |
618c169b GH |
588 | /* update speed */ |
589 | if (port->port.dev->speed == USB_SPEED_LOW) { | |
590 | port->ctrl |= UHCI_PORT_LSDA; | |
bb36d470 | 591 | } else { |
618c169b GH |
592 | port->ctrl &= ~UHCI_PORT_LSDA; |
593 | } | |
96217e31 | 594 | |
618c169b GH |
595 | uhci_resume(s); |
596 | } | |
96217e31 | 597 | |
618c169b GH |
598 | static void uhci_detach(USBPort *port1) |
599 | { | |
600 | UHCIState *s = port1->opaque; | |
601 | UHCIPort *port = &s->ports[port1->index]; | |
602 | ||
4706ab6c HG |
603 | uhci_async_cancel_device(s, port1->dev); |
604 | ||
618c169b GH |
605 | /* set connect status */ |
606 | if (port->ctrl & UHCI_PORT_CCS) { | |
607 | port->ctrl &= ~UHCI_PORT_CCS; | |
608 | port->ctrl |= UHCI_PORT_CSC; | |
bb36d470 | 609 | } |
618c169b GH |
610 | /* disable port */ |
611 | if (port->ctrl & UHCI_PORT_EN) { | |
612 | port->ctrl &= ~UHCI_PORT_EN; | |
613 | port->ctrl |= UHCI_PORT_ENC; | |
614 | } | |
615 | ||
616 | uhci_resume(s); | |
bb36d470 FB |
617 | } |
618 | ||
4706ab6c HG |
619 | static void uhci_child_detach(USBPort *port1, USBDevice *child) |
620 | { | |
621 | UHCIState *s = port1->opaque; | |
622 | ||
623 | uhci_async_cancel_device(s, child); | |
624 | } | |
625 | ||
d47e59b8 | 626 | static void uhci_wakeup(USBPort *port1) |
9159f679 | 627 | { |
d47e59b8 HG |
628 | UHCIState *s = port1->opaque; |
629 | UHCIPort *port = &s->ports[port1->index]; | |
9159f679 GH |
630 | |
631 | if (port->ctrl & UHCI_PORT_SUSPEND && !(port->ctrl & UHCI_PORT_RD)) { | |
632 | port->ctrl |= UHCI_PORT_RD; | |
633 | uhci_resume(s); | |
634 | } | |
635 | } | |
636 | ||
461700c1 | 637 | static USBDevice *uhci_find_device(UHCIState *s, uint8_t addr) |
bb36d470 | 638 | { |
461700c1 GH |
639 | USBDevice *dev; |
640 | int i; | |
54f254f9 | 641 | |
461700c1 | 642 | for (i = 0; i < NB_PORTS; i++) { |
54f254f9 | 643 | UHCIPort *port = &s->ports[i]; |
461700c1 GH |
644 | if (!(port->ctrl & UHCI_PORT_EN)) { |
645 | continue; | |
646 | } | |
647 | dev = usb_find_device(&port->port, addr); | |
648 | if (dev != NULL) { | |
649 | return dev; | |
891fb2cd | 650 | } |
bb36d470 | 651 | } |
461700c1 | 652 | return NULL; |
bb36d470 FB |
653 | } |
654 | ||
d47e59b8 | 655 | static void uhci_async_complete(USBPort *port, USBPacket *packet); |
54f254f9 | 656 | static void uhci_process_frame(UHCIState *s); |
4d611c9a | 657 | |
bb36d470 FB |
658 | /* return -1 if fatal error (frame must be stopped) |
659 | 0 if TD successful | |
660 | 1 if TD unsuccessful or inactive | |
661 | */ | |
54f254f9 | 662 | static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) |
bb36d470 | 663 | { |
54f254f9 | 664 | int len = 0, max_len, err, ret; |
bb36d470 | 665 | uint8_t pid; |
bb36d470 | 666 | |
54f254f9 AL |
667 | max_len = ((td->token >> 21) + 1) & 0x7ff; |
668 | pid = td->token & 0xff; | |
669 | ||
4f4321c1 | 670 | ret = async->packet.result; |
54f254f9 | 671 | |
54f254f9 AL |
672 | if (td->ctrl & TD_CTRL_IOS) |
673 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
bb36d470 | 674 | |
54f254f9 AL |
675 | if (ret < 0) |
676 | goto out; | |
b9dc033c | 677 | |
4f4321c1 | 678 | len = async->packet.result; |
54f254f9 AL |
679 | td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
680 | ||
681 | /* The NAK bit may have been set by a previous frame, so clear it | |
682 | here. The docs are somewhat unclear, but win2k relies on this | |
683 | behavior. */ | |
684 | td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); | |
5bd2c0d7 PB |
685 | if (td->ctrl & TD_CTRL_IOC) |
686 | *int_mask |= 0x01; | |
54f254f9 AL |
687 | |
688 | if (pid == USB_TOKEN_IN) { | |
689 | if (len > max_len) { | |
54f254f9 AL |
690 | ret = USB_RET_BABBLE; |
691 | goto out; | |
4d611c9a | 692 | } |
b9dc033c | 693 | |
54f254f9 | 694 | if ((td->ctrl & TD_CTRL_SPD) && len < max_len) { |
bb36d470 FB |
695 | *int_mask |= 0x02; |
696 | /* short packet: do not update QH */ | |
d0f2c4c6 | 697 | DPRINTF("uhci: short packet. td 0x%x token 0x%x\n", async->td, async->token); |
bb36d470 | 698 | return 1; |
bb36d470 | 699 | } |
54f254f9 AL |
700 | } |
701 | ||
702 | /* success */ | |
703 | return 0; | |
704 | ||
705 | out: | |
706 | switch(ret) { | |
707 | case USB_RET_STALL: | |
708 | td->ctrl |= TD_CTRL_STALL; | |
709 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
8656954a | 710 | s->status |= UHCI_STS_USBERR; |
0070f095 GH |
711 | if (td->ctrl & TD_CTRL_IOC) { |
712 | *int_mask |= 0x01; | |
713 | } | |
8656954a | 714 | uhci_update_irq(s); |
54f254f9 AL |
715 | return 1; |
716 | ||
717 | case USB_RET_BABBLE: | |
718 | td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; | |
719 | td->ctrl &= ~TD_CTRL_ACTIVE; | |
8656954a | 720 | s->status |= UHCI_STS_USBERR; |
0070f095 GH |
721 | if (td->ctrl & TD_CTRL_IOC) { |
722 | *int_mask |= 0x01; | |
723 | } | |
8656954a | 724 | uhci_update_irq(s); |
54f254f9 AL |
725 | /* frame interrupted */ |
726 | return -1; | |
727 | ||
728 | case USB_RET_NAK: | |
729 | td->ctrl |= TD_CTRL_NAK; | |
730 | if (pid == USB_TOKEN_SETUP) | |
731 | break; | |
732 | return 1; | |
733 | ||
734 | case USB_RET_NODEV: | |
735 | default: | |
736 | break; | |
737 | } | |
738 | ||
739 | /* Retry the TD if error count is not zero */ | |
740 | ||
741 | td->ctrl |= TD_CTRL_TIMEOUT; | |
742 | err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3; | |
743 | if (err != 0) { | |
744 | err--; | |
745 | if (err == 0) { | |
bb36d470 | 746 | td->ctrl &= ~TD_CTRL_ACTIVE; |
54f254f9 | 747 | s->status |= UHCI_STS_USBERR; |
5bd2c0d7 PB |
748 | if (td->ctrl & TD_CTRL_IOC) |
749 | *int_mask |= 0x01; | |
54f254f9 | 750 | uhci_update_irq(s); |
bb36d470 FB |
751 | } |
752 | } | |
54f254f9 AL |
753 | td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) | |
754 | (err << TD_CTRL_ERROR_SHIFT); | |
755 | return 1; | |
bb36d470 FB |
756 | } |
757 | ||
54f254f9 AL |
758 | static int uhci_handle_td(UHCIState *s, uint32_t addr, UHCI_TD *td, uint32_t *int_mask) |
759 | { | |
760 | UHCIAsync *async; | |
5d808245 | 761 | int len = 0, max_len; |
8e65b7c0 DA |
762 | uint8_t pid, isoc; |
763 | uint32_t token; | |
54f254f9 AL |
764 | |
765 | /* Is active ? */ | |
766 | if (!(td->ctrl & TD_CTRL_ACTIVE)) | |
767 | return 1; | |
768 | ||
8e65b7c0 DA |
769 | /* token field is not unique for isochronous requests, |
770 | * so use the destination buffer | |
771 | */ | |
772 | if (td->ctrl & TD_CTRL_IOS) { | |
773 | token = td->buffer; | |
774 | isoc = 1; | |
775 | } else { | |
776 | token = td->token; | |
777 | isoc = 0; | |
778 | } | |
779 | ||
780 | async = uhci_async_find_td(s, addr, token); | |
54f254f9 AL |
781 | if (async) { |
782 | /* Already submitted */ | |
a145ea51 | 783 | async->valid = 32; |
54f254f9 AL |
784 | |
785 | if (!async->done) | |
786 | return 1; | |
787 | ||
788 | uhci_async_unlink(s, async); | |
789 | goto done; | |
790 | } | |
791 | ||
792 | /* Allocate new packet */ | |
793 | async = uhci_async_alloc(s); | |
794 | if (!async) | |
795 | return 1; | |
796 | ||
8e65b7c0 DA |
797 | /* valid needs to be large enough to handle 10 frame delay |
798 | * for initial isochronous requests | |
799 | */ | |
800 | async->valid = 32; | |
54f254f9 | 801 | async->td = addr; |
8e65b7c0 DA |
802 | async->token = token; |
803 | async->isoc = isoc; | |
54f254f9 AL |
804 | |
805 | max_len = ((td->token >> 21) + 1) & 0x7ff; | |
806 | pid = td->token & 0xff; | |
807 | ||
4f4321c1 GH |
808 | usb_packet_setup(&async->packet, pid, (td->token >> 8) & 0x7f, |
809 | (td->token >> 15) & 0xf); | |
df5e66ee GH |
810 | qemu_sglist_add(&async->sgl, td->buffer, max_len); |
811 | usb_packet_map(&async->packet, &async->sgl); | |
54f254f9 AL |
812 | |
813 | switch(pid) { | |
814 | case USB_TOKEN_OUT: | |
815 | case USB_TOKEN_SETUP: | |
461700c1 GH |
816 | len = usb_handle_packet(uhci_find_device(s, async->packet.devaddr), |
817 | &async->packet); | |
5d808245 AJ |
818 | if (len >= 0) |
819 | len = max_len; | |
54f254f9 AL |
820 | break; |
821 | ||
822 | case USB_TOKEN_IN: | |
461700c1 GH |
823 | len = usb_handle_packet(uhci_find_device(s, async->packet.devaddr), |
824 | &async->packet); | |
54f254f9 AL |
825 | break; |
826 | ||
827 | default: | |
828 | /* invalid pid : frame interrupted */ | |
829 | uhci_async_free(s, async); | |
830 | s->status |= UHCI_STS_HCPERR; | |
831 | uhci_update_irq(s); | |
832 | return -1; | |
833 | } | |
834 | ||
5d808245 | 835 | if (len == USB_RET_ASYNC) { |
54f254f9 AL |
836 | uhci_async_link(s, async); |
837 | return 2; | |
838 | } | |
839 | ||
4f4321c1 | 840 | async->packet.result = len; |
54f254f9 AL |
841 | |
842 | done: | |
5d808245 | 843 | len = uhci_complete_td(s, td, async, int_mask); |
df5e66ee | 844 | usb_packet_unmap(&async->packet); |
54f254f9 | 845 | uhci_async_free(s, async); |
5d808245 | 846 | return len; |
54f254f9 AL |
847 | } |
848 | ||
d47e59b8 | 849 | static void uhci_async_complete(USBPort *port, USBPacket *packet) |
4d611c9a | 850 | { |
7b5a44c5 GH |
851 | UHCIAsync *async = container_of(packet, UHCIAsync, packet); |
852 | UHCIState *s = async->uhci; | |
54f254f9 | 853 | |
d0f2c4c6 | 854 | DPRINTF("uhci: async complete. td 0x%x token 0x%x\n", async->td, async->token); |
54f254f9 | 855 | |
8e65b7c0 DA |
856 | if (async->isoc) { |
857 | UHCI_TD td; | |
858 | uint32_t link = async->td; | |
859 | uint32_t int_mask = 0, val; | |
d4c4e6fd | 860 | |
9fe2fd67 | 861 | pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
8e65b7c0 DA |
862 | le32_to_cpus(&td.link); |
863 | le32_to_cpus(&td.ctrl); | |
864 | le32_to_cpus(&td.token); | |
865 | le32_to_cpus(&td.buffer); | |
866 | ||
867 | uhci_async_unlink(s, async); | |
d4c4e6fd | 868 | uhci_complete_td(s, &td, async, &int_mask); |
8e65b7c0 | 869 | s->pending_int_mask |= int_mask; |
54f254f9 | 870 | |
8e65b7c0 DA |
871 | /* update the status bits of the TD */ |
872 | val = cpu_to_le32(td.ctrl); | |
9fe2fd67 | 873 | pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
8e65b7c0 DA |
874 | uhci_async_free(s, async); |
875 | } else { | |
876 | async->done = 1; | |
877 | uhci_process_frame(s); | |
878 | } | |
54f254f9 AL |
879 | } |
880 | ||
881 | static int is_valid(uint32_t link) | |
882 | { | |
883 | return (link & 1) == 0; | |
884 | } | |
885 | ||
886 | static int is_qh(uint32_t link) | |
887 | { | |
888 | return (link & 2) != 0; | |
889 | } | |
890 | ||
891 | static int depth_first(uint32_t link) | |
892 | { | |
893 | return (link & 4) != 0; | |
894 | } | |
895 | ||
896 | /* QH DB used for detecting QH loops */ | |
897 | #define UHCI_MAX_QUEUES 128 | |
898 | typedef struct { | |
899 | uint32_t addr[UHCI_MAX_QUEUES]; | |
900 | int count; | |
901 | } QhDb; | |
902 | ||
903 | static void qhdb_reset(QhDb *db) | |
904 | { | |
905 | db->count = 0; | |
906 | } | |
907 | ||
908 | /* Add QH to DB. Returns 1 if already present or DB is full. */ | |
909 | static int qhdb_insert(QhDb *db, uint32_t addr) | |
910 | { | |
911 | int i; | |
912 | for (i = 0; i < db->count; i++) | |
913 | if (db->addr[i] == addr) | |
914 | return 1; | |
915 | ||
916 | if (db->count >= UHCI_MAX_QUEUES) | |
917 | return 1; | |
918 | ||
919 | db->addr[db->count++] = addr; | |
920 | return 0; | |
921 | } | |
922 | ||
923 | static void uhci_process_frame(UHCIState *s) | |
924 | { | |
925 | uint32_t frame_addr, link, old_td_ctrl, val, int_mask; | |
3200d108 | 926 | uint32_t curr_qh, td_count = 0, bytes_count = 0; |
54f254f9 | 927 | int cnt, ret; |
4d611c9a | 928 | UHCI_TD td; |
54f254f9 AL |
929 | UHCI_QH qh; |
930 | QhDb qhdb; | |
4d611c9a | 931 | |
54f254f9 AL |
932 | frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
933 | ||
d0f2c4c6 | 934 | DPRINTF("uhci: processing frame %d addr 0x%x\n" , s->frnum, frame_addr); |
54f254f9 | 935 | |
9fe2fd67 | 936 | pci_dma_read(&s->dev, frame_addr, &link, 4); |
54f254f9 | 937 | le32_to_cpus(&link); |
b9dc033c | 938 | |
54f254f9 AL |
939 | int_mask = 0; |
940 | curr_qh = 0; | |
941 | ||
942 | qhdb_reset(&qhdb); | |
943 | ||
944 | for (cnt = FRAME_MAX_LOOPS; is_valid(link) && cnt; cnt--) { | |
945 | if (is_qh(link)) { | |
946 | /* QH */ | |
947 | ||
948 | if (qhdb_insert(&qhdb, link)) { | |
949 | /* | |
950 | * We're going in circles. Which is not a bug because | |
3200d108 GH |
951 | * HCD is allowed to do that as part of the BW management. |
952 | * | |
953 | * Stop processing here if | |
954 | * (a) no transaction has been done since we've been | |
955 | * here last time, or | |
956 | * (b) we've reached the usb 1.1 bandwidth, which is | |
957 | * 1280 bytes/frame. | |
54f254f9 | 958 | */ |
d0f2c4c6 | 959 | DPRINTF("uhci: detected loop. qh 0x%x\n", link); |
3200d108 GH |
960 | if (td_count == 0) { |
961 | DPRINTF("uhci: no transaction last round, stop\n"); | |
962 | break; | |
963 | } else if (bytes_count >= 1280) { | |
964 | DPRINTF("uhci: bandwidth limit reached, stop\n"); | |
965 | break; | |
966 | } else { | |
967 | td_count = 0; | |
968 | qhdb_reset(&qhdb); | |
969 | qhdb_insert(&qhdb, link); | |
970 | } | |
54f254f9 AL |
971 | } |
972 | ||
9fe2fd67 | 973 | pci_dma_read(&s->dev, link & ~0xf, &qh, sizeof(qh)); |
54f254f9 AL |
974 | le32_to_cpus(&qh.link); |
975 | le32_to_cpus(&qh.el_link); | |
976 | ||
d0f2c4c6 | 977 | DPRINTF("uhci: QH 0x%x load. link 0x%x elink 0x%x\n", |
54f254f9 AL |
978 | link, qh.link, qh.el_link); |
979 | ||
980 | if (!is_valid(qh.el_link)) { | |
981 | /* QH w/o elements */ | |
982 | curr_qh = 0; | |
983 | link = qh.link; | |
984 | } else { | |
985 | /* QH with elements */ | |
986 | curr_qh = link; | |
987 | link = qh.el_link; | |
988 | } | |
989 | continue; | |
990 | } | |
991 | ||
992 | /* TD */ | |
9fe2fd67 | 993 | pci_dma_read(&s->dev, link & ~0xf, &td, sizeof(td)); |
b9dc033c AZ |
994 | le32_to_cpus(&td.link); |
995 | le32_to_cpus(&td.ctrl); | |
996 | le32_to_cpus(&td.token); | |
997 | le32_to_cpus(&td.buffer); | |
b9dc033c | 998 | |
d0f2c4c6 | 999 | DPRINTF("uhci: TD 0x%x load. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", |
54f254f9 AL |
1000 | link, td.link, td.ctrl, td.token, curr_qh); |
1001 | ||
1002 | old_td_ctrl = td.ctrl; | |
1003 | ret = uhci_handle_td(s, link, &td, &int_mask); | |
b9dc033c | 1004 | if (old_td_ctrl != td.ctrl) { |
54f254f9 | 1005 | /* update the status bits of the TD */ |
b9dc033c | 1006 | val = cpu_to_le32(td.ctrl); |
9fe2fd67 | 1007 | pci_dma_write(&s->dev, (link & ~0xf) + 4, &val, sizeof(val)); |
b9dc033c | 1008 | } |
54f254f9 AL |
1009 | |
1010 | if (ret < 0) { | |
1011 | /* interrupted frame */ | |
1012 | break; | |
b9dc033c | 1013 | } |
b9dc033c | 1014 | |
54f254f9 | 1015 | if (ret == 2 || ret == 1) { |
d0f2c4c6 | 1016 | DPRINTF("uhci: TD 0x%x %s. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", |
54f254f9 AL |
1017 | link, ret == 2 ? "pend" : "skip", |
1018 | td.link, td.ctrl, td.token, curr_qh); | |
b9dc033c | 1019 | |
54f254f9 AL |
1020 | link = curr_qh ? qh.link : td.link; |
1021 | continue; | |
4d611c9a | 1022 | } |
54f254f9 AL |
1023 | |
1024 | /* completed TD */ | |
1025 | ||
d0f2c4c6 | 1026 | DPRINTF("uhci: TD 0x%x done. link 0x%x ctrl 0x%x token 0x%x qh 0x%x\n", |
54f254f9 AL |
1027 | link, td.link, td.ctrl, td.token, curr_qh); |
1028 | ||
1029 | link = td.link; | |
3200d108 GH |
1030 | td_count++; |
1031 | bytes_count += (td.ctrl & 0x7ff) + 1; | |
54f254f9 AL |
1032 | |
1033 | if (curr_qh) { | |
1034 | /* update QH element link */ | |
1035 | qh.el_link = link; | |
4d611c9a | 1036 | val = cpu_to_le32(qh.el_link); |
9fe2fd67 | 1037 | pci_dma_write(&s->dev, (curr_qh & ~0xf) + 4, &val, sizeof(val)); |
54f254f9 AL |
1038 | |
1039 | if (!depth_first(link)) { | |
1040 | /* done with this QH */ | |
1041 | ||
d0f2c4c6 | 1042 | DPRINTF("uhci: QH 0x%x done. link 0x%x elink 0x%x\n", |
54f254f9 AL |
1043 | curr_qh, qh.link, qh.el_link); |
1044 | ||
1045 | curr_qh = 0; | |
1046 | link = qh.link; | |
1047 | } | |
4d611c9a | 1048 | } |
54f254f9 AL |
1049 | |
1050 | /* go to the next entry */ | |
4d611c9a | 1051 | } |
54f254f9 | 1052 | |
8e65b7c0 | 1053 | s->pending_int_mask |= int_mask; |
4d611c9a PB |
1054 | } |
1055 | ||
bb36d470 FB |
1056 | static void uhci_frame_timer(void *opaque) |
1057 | { | |
1058 | UHCIState *s = opaque; | |
8e65b7c0 DA |
1059 | |
1060 | /* prepare the timer for the next frame */ | |
1061 | s->expire_time += (get_ticks_per_sec() / FRAME_TIMER_FREQ); | |
bb36d470 FB |
1062 | |
1063 | if (!(s->cmd & UHCI_CMD_RS)) { | |
54f254f9 | 1064 | /* Full stop */ |
bb36d470 | 1065 | qemu_del_timer(s->frame_timer); |
52328140 FB |
1066 | /* set hchalted bit in status - UHCI11D 2.1.2 */ |
1067 | s->status |= UHCI_STS_HCHALTED; | |
6f382b5e | 1068 | |
d0f2c4c6 | 1069 | DPRINTF("uhci: halted\n"); |
bb36d470 FB |
1070 | return; |
1071 | } | |
54f254f9 AL |
1072 | |
1073 | /* Complete the previous frame */ | |
4d611c9a PB |
1074 | if (s->pending_int_mask) { |
1075 | s->status2 |= s->pending_int_mask; | |
54f254f9 | 1076 | s->status |= UHCI_STS_USBINT; |
4d611c9a PB |
1077 | uhci_update_irq(s); |
1078 | } | |
8e65b7c0 | 1079 | s->pending_int_mask = 0; |
b9dc033c | 1080 | |
54f254f9 AL |
1081 | /* Start new frame */ |
1082 | s->frnum = (s->frnum + 1) & 0x7ff; | |
1083 | ||
d0f2c4c6 | 1084 | DPRINTF("uhci: new frame #%u\n" , s->frnum); |
54f254f9 AL |
1085 | |
1086 | uhci_async_validate_begin(s); | |
1087 | ||
1088 | uhci_process_frame(s); | |
1089 | ||
1090 | uhci_async_validate_end(s); | |
b9dc033c | 1091 | |
8e65b7c0 | 1092 | qemu_mod_timer(s->frame_timer, s->expire_time); |
bb36d470 FB |
1093 | } |
1094 | ||
a03f66e4 AK |
1095 | static const MemoryRegionPortio uhci_portio[] = { |
1096 | { 0, 32, 2, .write = uhci_ioport_writew, }, | |
1097 | { 0, 32, 2, .read = uhci_ioport_readw, }, | |
1098 | { 0, 32, 4, .write = uhci_ioport_writel, }, | |
1099 | { 0, 32, 4, .read = uhci_ioport_readl, }, | |
1100 | { 0, 32, 1, .write = uhci_ioport_writeb, }, | |
1101 | { 0, 32, 1, .read = uhci_ioport_readb, }, | |
1102 | PORTIO_END_OF_LIST() | |
1103 | }; | |
1104 | ||
1105 | static const MemoryRegionOps uhci_ioport_ops = { | |
1106 | .old_portio = uhci_portio, | |
1107 | }; | |
bb36d470 | 1108 | |
0d86d2be GH |
1109 | static USBPortOps uhci_port_ops = { |
1110 | .attach = uhci_attach, | |
618c169b | 1111 | .detach = uhci_detach, |
4706ab6c | 1112 | .child_detach = uhci_child_detach, |
9159f679 | 1113 | .wakeup = uhci_wakeup, |
13a9a0d3 | 1114 | .complete = uhci_async_complete, |
0d86d2be GH |
1115 | }; |
1116 | ||
07771f6f | 1117 | static USBBusOps uhci_bus_ops = { |
07771f6f GH |
1118 | }; |
1119 | ||
dc638fad | 1120 | static int usb_uhci_common_initfn(PCIDevice *dev) |
bb36d470 | 1121 | { |
dc638fad | 1122 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); |
6cf9b6f1 | 1123 | uint8_t *pci_conf = s->dev.config; |
bb36d470 FB |
1124 | int i; |
1125 | ||
db579e9e | 1126 | pci_conf[PCI_CLASS_PROG] = 0x00; |
db579e9e | 1127 | /* TODO: reset value should be 0. */ |
817e0b6f | 1128 | pci_conf[PCI_INTERRUPT_PIN] = 4; /* interrupt pin D */ |
e59d33a7 | 1129 | pci_conf[USB_SBRN] = USB_RELEASE_1; // release number |
3b46e624 | 1130 | |
35e4977f HG |
1131 | if (s->masterbus) { |
1132 | USBPort *ports[NB_PORTS]; | |
1133 | for(i = 0; i < NB_PORTS; i++) { | |
1134 | ports[i] = &s->ports[i].port; | |
1135 | } | |
1136 | if (usb_register_companion(s->masterbus, ports, NB_PORTS, | |
1137 | s->firstport, s, &uhci_port_ops, | |
1138 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL) != 0) { | |
1139 | return -1; | |
1140 | } | |
1141 | } else { | |
1142 | usb_bus_new(&s->bus, &uhci_bus_ops, &s->dev.qdev); | |
1143 | for (i = 0; i < NB_PORTS; i++) { | |
1144 | usb_register_port(&s->bus, &s->ports[i].port, s, i, &uhci_port_ops, | |
1145 | USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); | |
1146 | } | |
bb36d470 | 1147 | } |
74475455 | 1148 | s->frame_timer = qemu_new_timer_ns(vm_clock, uhci_frame_timer, s); |
64e58fe5 | 1149 | s->num_ports_vmstate = NB_PORTS; |
ddf6583f | 1150 | QTAILQ_INIT(&s->async_pending); |
bb36d470 | 1151 | |
a08d4367 | 1152 | qemu_register_reset(uhci_reset, s); |
bb36d470 | 1153 | |
a03f66e4 | 1154 | memory_region_init_io(&s->io_bar, &uhci_ioport_ops, s, "uhci", 0x20); |
38ca0f6d PB |
1155 | /* Use region 4 for consistency with real hardware. BSD guests seem |
1156 | to rely on this. */ | |
e824b2cc | 1157 | pci_register_bar(&s->dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); |
6f382b5e | 1158 | |
6cf9b6f1 | 1159 | return 0; |
bb36d470 | 1160 | } |
afcc3cdf | 1161 | |
30235a54 HC |
1162 | static int usb_uhci_vt82c686b_initfn(PCIDevice *dev) |
1163 | { | |
1164 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1165 | uint8_t *pci_conf = s->dev.config; | |
1166 | ||
30235a54 HC |
1167 | /* USB misc control 1/2 */ |
1168 | pci_set_long(pci_conf + 0x40,0x00001000); | |
1169 | /* PM capability */ | |
1170 | pci_set_long(pci_conf + 0x80,0x00020001); | |
1171 | /* USB legacy support */ | |
1172 | pci_set_long(pci_conf + 0xc0,0x00002000); | |
1173 | ||
dc638fad | 1174 | return usb_uhci_common_initfn(dev); |
30235a54 HC |
1175 | } |
1176 | ||
a03f66e4 AK |
1177 | static int usb_uhci_exit(PCIDevice *dev) |
1178 | { | |
1179 | UHCIState *s = DO_UPCAST(UHCIState, dev, dev); | |
1180 | ||
1181 | memory_region_destroy(&s->io_bar); | |
1182 | return 0; | |
1183 | } | |
1184 | ||
1b5a7570 GH |
1185 | static Property uhci_properties[] = { |
1186 | DEFINE_PROP_STRING("masterbus", UHCIState, masterbus), | |
1187 | DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), | |
1188 | DEFINE_PROP_END_OF_LIST(), | |
1189 | }; | |
1190 | ||
40021f08 AL |
1191 | static void piix3_uhci_class_init(ObjectClass *klass, void *data) |
1192 | { | |
39bffca2 | 1193 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1194 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1195 | ||
1196 | k->init = usb_uhci_common_initfn; | |
1197 | k->exit = usb_uhci_exit; | |
1198 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1199 | k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; | |
1200 | k->revision = 0x01; | |
1201 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1202 | dc->vmsd = &vmstate_uhci; |
1203 | dc->props = uhci_properties; | |
40021f08 AL |
1204 | } |
1205 | ||
39bffca2 AL |
1206 | static TypeInfo piix3_uhci_info = { |
1207 | .name = "piix3-usb-uhci", | |
1208 | .parent = TYPE_PCI_DEVICE, | |
1209 | .instance_size = sizeof(UHCIState), | |
1210 | .class_init = piix3_uhci_class_init, | |
e855761c AL |
1211 | }; |
1212 | ||
40021f08 AL |
1213 | static void piix4_uhci_class_init(ObjectClass *klass, void *data) |
1214 | { | |
39bffca2 | 1215 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1216 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1217 | ||
1218 | k->init = usb_uhci_common_initfn; | |
1219 | k->exit = usb_uhci_exit; | |
1220 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1221 | k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; | |
1222 | k->revision = 0x01; | |
1223 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1224 | dc->vmsd = &vmstate_uhci; |
1225 | dc->props = uhci_properties; | |
40021f08 AL |
1226 | } |
1227 | ||
39bffca2 AL |
1228 | static TypeInfo piix4_uhci_info = { |
1229 | .name = "piix4-usb-uhci", | |
1230 | .parent = TYPE_PCI_DEVICE, | |
1231 | .instance_size = sizeof(UHCIState), | |
1232 | .class_init = piix4_uhci_class_init, | |
e855761c AL |
1233 | }; |
1234 | ||
40021f08 AL |
1235 | static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) |
1236 | { | |
39bffca2 | 1237 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1238 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1239 | ||
1240 | k->init = usb_uhci_vt82c686b_initfn; | |
1241 | k->exit = usb_uhci_exit; | |
1242 | k->vendor_id = PCI_VENDOR_ID_VIA; | |
1243 | k->device_id = PCI_DEVICE_ID_VIA_UHCI; | |
1244 | k->revision = 0x01; | |
1245 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1246 | dc->vmsd = &vmstate_uhci; |
1247 | dc->props = uhci_properties; | |
40021f08 AL |
1248 | } |
1249 | ||
39bffca2 AL |
1250 | static TypeInfo vt82c686b_uhci_info = { |
1251 | .name = "vt82c686b-usb-uhci", | |
1252 | .parent = TYPE_PCI_DEVICE, | |
1253 | .instance_size = sizeof(UHCIState), | |
1254 | .class_init = vt82c686b_uhci_class_init, | |
e855761c AL |
1255 | }; |
1256 | ||
40021f08 AL |
1257 | static void ich9_uhci1_class_init(ObjectClass *klass, void *data) |
1258 | { | |
39bffca2 | 1259 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1260 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1261 | ||
1262 | k->init = usb_uhci_common_initfn; | |
1263 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1264 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; | |
1265 | k->revision = 0x03; | |
1266 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1267 | dc->vmsd = &vmstate_uhci; |
1268 | dc->props = uhci_properties; | |
40021f08 AL |
1269 | } |
1270 | ||
39bffca2 AL |
1271 | static TypeInfo ich9_uhci1_info = { |
1272 | .name = "ich9-usb-uhci1", | |
1273 | .parent = TYPE_PCI_DEVICE, | |
1274 | .instance_size = sizeof(UHCIState), | |
1275 | .class_init = ich9_uhci1_class_init, | |
e855761c AL |
1276 | }; |
1277 | ||
40021f08 AL |
1278 | static void ich9_uhci2_class_init(ObjectClass *klass, void *data) |
1279 | { | |
39bffca2 | 1280 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1281 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1282 | ||
1283 | k->init = usb_uhci_common_initfn; | |
1284 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1285 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; | |
1286 | k->revision = 0x03; | |
1287 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1288 | dc->vmsd = &vmstate_uhci; |
1289 | dc->props = uhci_properties; | |
40021f08 AL |
1290 | } |
1291 | ||
39bffca2 AL |
1292 | static TypeInfo ich9_uhci2_info = { |
1293 | .name = "ich9-usb-uhci2", | |
1294 | .parent = TYPE_PCI_DEVICE, | |
1295 | .instance_size = sizeof(UHCIState), | |
1296 | .class_init = ich9_uhci2_class_init, | |
e855761c AL |
1297 | }; |
1298 | ||
40021f08 AL |
1299 | static void ich9_uhci3_class_init(ObjectClass *klass, void *data) |
1300 | { | |
39bffca2 | 1301 | DeviceClass *dc = DEVICE_CLASS(klass); |
40021f08 AL |
1302 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1303 | ||
1304 | k->init = usb_uhci_common_initfn; | |
1305 | k->vendor_id = PCI_VENDOR_ID_INTEL; | |
1306 | k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; | |
1307 | k->revision = 0x03; | |
1308 | k->class_id = PCI_CLASS_SERIAL_USB; | |
39bffca2 AL |
1309 | dc->vmsd = &vmstate_uhci; |
1310 | dc->props = uhci_properties; | |
40021f08 AL |
1311 | } |
1312 | ||
39bffca2 AL |
1313 | static TypeInfo ich9_uhci3_info = { |
1314 | .name = "ich9-usb-uhci3", | |
1315 | .parent = TYPE_PCI_DEVICE, | |
1316 | .instance_size = sizeof(UHCIState), | |
1317 | .class_init = ich9_uhci3_class_init, | |
6cf9b6f1 | 1318 | }; |
afcc3cdf | 1319 | |
6cf9b6f1 GH |
1320 | static void uhci_register(void) |
1321 | { | |
39bffca2 AL |
1322 | type_register_static(&piix3_uhci_info); |
1323 | type_register_static(&piix4_uhci_info); | |
1324 | type_register_static(&vt82c686b_uhci_info); | |
1325 | type_register_static(&ich9_uhci1_info); | |
1326 | type_register_static(&ich9_uhci2_info); | |
1327 | type_register_static(&ich9_uhci3_info); | |
6cf9b6f1 GH |
1328 | } |
1329 | device_init(uhci_register); | |
afcc3cdf | 1330 | |
6cf9b6f1 GH |
1331 | void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
1332 | { | |
556cd098 | 1333 | pci_create_simple(bus, devfn, "piix3-usb-uhci"); |
6cf9b6f1 | 1334 | } |
54f254f9 | 1335 | |
6cf9b6f1 GH |
1336 | void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
1337 | { | |
556cd098 | 1338 | pci_create_simple(bus, devfn, "piix4-usb-uhci"); |
afcc3cdf | 1339 | } |
30235a54 HC |
1340 | |
1341 | void usb_uhci_vt82c686b_init(PCIBus *bus, int devfn) | |
1342 | { | |
1343 | pci_create_simple(bus, devfn, "vt82c686b-usb-uhci"); | |
1344 | } |