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report serial devices created with -device in the PIIX4 config space
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5fafdf24 1/*
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2 * ARM Versatile/PB PCI host controller
3 *
0027b06d 4 * Copyright (c) 2006-2009 CodeSourcery.
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5 * Written by Paul Brook
6 *
7 * This code is licenced under the LGPL.
8 */
9
0027b06d 10#include "sysbus.h"
87ecb68b 11#include "pci.h"
b6243d99 12#include "pci_host.h"
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13
14typedef struct {
15 SysBusDevice busdev;
16 qemu_irq irq[4];
17 int realview;
18 int mem_config;
19} PCIVPBState;
502a5395 20
c227f099 21static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
502a5395 22{
80b3ada7 23 return addr & 0xffffff;
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24}
25
c227f099 26static void pci_vpb_config_writeb (void *opaque, target_phys_addr_t addr,
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27 uint32_t val)
28{
29 pci_data_write(opaque, vpb_pci_config_addr (addr), val, 1);
30}
31
c227f099 32static void pci_vpb_config_writew (void *opaque, target_phys_addr_t addr,
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33 uint32_t val)
34{
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35 pci_data_write(opaque, vpb_pci_config_addr (addr), val, 2);
36}
37
c227f099 38static void pci_vpb_config_writel (void *opaque, target_phys_addr_t addr,
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39 uint32_t val)
40{
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41 pci_data_write(opaque, vpb_pci_config_addr (addr), val, 4);
42}
43
c227f099 44static uint32_t pci_vpb_config_readb (void *opaque, target_phys_addr_t addr)
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45{
46 uint32_t val;
47 val = pci_data_read(opaque, vpb_pci_config_addr (addr), 1);
48 return val;
49}
50
c227f099 51static uint32_t pci_vpb_config_readw (void *opaque, target_phys_addr_t addr)
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52{
53 uint32_t val;
54 val = pci_data_read(opaque, vpb_pci_config_addr (addr), 2);
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55 return val;
56}
57
c227f099 58static uint32_t pci_vpb_config_readl (void *opaque, target_phys_addr_t addr)
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59{
60 uint32_t val;
61 val = pci_data_read(opaque, vpb_pci_config_addr (addr), 4);
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62 return val;
63}
64
d60efc6b 65static CPUWriteMemoryFunc * const pci_vpb_config_write[] = {
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66 &pci_vpb_config_writeb,
67 &pci_vpb_config_writew,
68 &pci_vpb_config_writel,
69};
70
d60efc6b 71static CPUReadMemoryFunc * const pci_vpb_config_read[] = {
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72 &pci_vpb_config_readb,
73 &pci_vpb_config_readw,
74 &pci_vpb_config_readl,
75};
76
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77static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
78{
79 return irq_num;
80}
81
5d4e84c8 82static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
502a5395 83{
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84 qemu_irq *pic = opaque;
85
97aff481 86 qemu_set_irq(pic[irq_num], level);
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87}
88
c227f099 89static void pci_vpb_map(SysBusDevice *dev, target_phys_addr_t base)
502a5395 90{
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91 PCIVPBState *s = (PCIVPBState *)dev;
92 /* Selfconfig area. */
93 cpu_register_physical_memory(base + 0x01000000, 0x1000000, s->mem_config);
94 /* Normal config area. */
95 cpu_register_physical_memory(base + 0x02000000, 0x1000000, s->mem_config);
96
97 if (s->realview) {
98 /* IO memory area. */
968d683c 99 isa_mmio_init(base + 0x03000000, 0x00100000);
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100 }
101}
102
81a322d4 103static int pci_vpb_init(SysBusDevice *dev)
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104{
105 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
106 PCIBus *bus;
97aff481 107 int i;
e69954b9 108
97aff481 109 for (i = 0; i < 4; i++) {
0027b06d 110 sysbus_init_irq(dev, &s->irq[i]);
e69954b9 111 }
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112 bus = pci_register_bus(&dev->qdev, "pci",
113 pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
520128bd 114 PCI_DEVFN(11, 0), 4);
0027b06d 115
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116 /* ??? Register memory space. */
117
1eed09cb 118 s->mem_config = cpu_register_io_memory(pci_vpb_config_read,
2507c12a 119 pci_vpb_config_write, bus,
387c3e96 120 DEVICE_LITTLE_ENDIAN);
0027b06d 121 sysbus_init_mmio_cb(dev, 0x04000000, pci_vpb_map);
e69954b9 122
0027b06d 123 pci_create_simple(bus, -1, "versatile_pci_host");
81a322d4 124 return 0;
0027b06d 125}
e69954b9 126
81a322d4 127static int pci_realview_init(SysBusDevice *dev)
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128{
129 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
130 s->realview = 1;
81a322d4 131 return pci_vpb_init(dev);
0027b06d 132}
502a5395 133
81a322d4 134static int versatile_pci_host_init(PCIDevice *d)
0027b06d 135{
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136 pci_set_word(d->config + PCI_STATUS,
137 PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
01764fe0 138 pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
81a322d4 139 return 0;
0027b06d 140}
502a5395 141
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142static PCIDeviceInfo versatile_pci_host_info = {
143 .qdev.name = "versatile_pci_host",
144 .qdev.size = sizeof(PCIDevice),
145 .init = versatile_pci_host_init,
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146 .vendor_id = PCI_VENDOR_ID_XILINX,
147 /* Both boards have the same device ID. Oh well. */
148 .device_id = PCI_DEVICE_ID_XILINX_XC2VP30,
149 .class_id = PCI_CLASS_PROCESSOR_CO,
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150};
151
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152static void versatile_pci_register_devices(void)
153{
154 sysbus_register_dev("versatile_pci", sizeof(PCIVPBState), pci_vpb_init);
155 sysbus_register_dev("realview_pci", sizeof(PCIVPBState),
156 pci_realview_init);
0aab0d3a 157 pci_qdev_register(&versatile_pci_host_info);
502a5395 158}
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159
160device_init(versatile_pci_register_devices)