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5fafdf24 1/*
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2 * ARM Versatile/PB PCI host controller
3 *
0027b06d 4 * Copyright (c) 2006-2009 CodeSourcery.
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5 * Written by Paul Brook
6 *
8e31bf38 7 * This code is licensed under the LGPL.
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8 */
9
0027b06d 10#include "sysbus.h"
87ecb68b 11#include "pci.h"
b6243d99 12#include "pci_host.h"
1e39101c 13#include "exec-memory.h"
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14
15typedef struct {
16 SysBusDevice busdev;
17 qemu_irq irq[4];
18 int realview;
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19 MemoryRegion mem_config;
20 MemoryRegion mem_config2;
21 MemoryRegion isa;
0027b06d 22} PCIVPBState;
502a5395 23
c227f099 24static inline uint32_t vpb_pci_config_addr(target_phys_addr_t addr)
502a5395 25{
80b3ada7 26 return addr & 0xffffff;
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27}
28
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29static void pci_vpb_config_write(void *opaque, target_phys_addr_t addr,
30 uint64_t val, unsigned size)
502a5395 31{
45de094e 32 pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
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33}
34
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35static uint64_t pci_vpb_config_read(void *opaque, target_phys_addr_t addr,
36 unsigned size)
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37{
38 uint32_t val;
45de094e 39 val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
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40 return val;
41}
42
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43static const MemoryRegionOps pci_vpb_config_ops = {
44 .read = pci_vpb_config_read,
45 .write = pci_vpb_config_write,
46 .endianness = DEVICE_NATIVE_ENDIAN,
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47};
48
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49static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
50{
51 return irq_num;
52}
53
5d4e84c8 54static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
502a5395 55{
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56 qemu_irq *pic = opaque;
57
97aff481 58 qemu_set_irq(pic[irq_num], level);
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59}
60
81a322d4 61static int pci_vpb_init(SysBusDevice *dev)
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62{
63 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
64 PCIBus *bus;
97aff481 65 int i;
e69954b9 66
97aff481 67 for (i = 0; i < 4; i++) {
0027b06d 68 sysbus_init_irq(dev, &s->irq[i]);
e69954b9 69 }
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70 bus = pci_register_bus(&dev->qdev, "pci",
71 pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
aee97b84 72 get_system_memory(), get_system_io(),
520128bd 73 PCI_DEVFN(11, 0), 4);
0027b06d 74
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75 /* ??? Register memory space. */
76
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77 /* Our memory regions are:
78 * 0 : PCI self config window
79 * 1 : PCI config window
80 * 2 : PCI IO window (realview_pci only)
81 */
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82 memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
83 "pci-vpb-selfconfig", 0x1000000);
750ecd44 84 sysbus_init_mmio(dev, &s->mem_config);
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85 memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
86 "pci-vpb-config", 0x1000000);
750ecd44 87 sysbus_init_mmio(dev, &s->mem_config2);
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88 if (s->realview) {
89 isa_mmio_setup(&s->isa, 0x0100000);
750ecd44 90 sysbus_init_mmio(dev, &s->isa);
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91 }
92
0027b06d 93 pci_create_simple(bus, -1, "versatile_pci_host");
81a322d4 94 return 0;
0027b06d 95}
e69954b9 96
81a322d4 97static int pci_realview_init(SysBusDevice *dev)
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98{
99 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
100 s->realview = 1;
81a322d4 101 return pci_vpb_init(dev);
0027b06d 102}
502a5395 103
81a322d4 104static int versatile_pci_host_init(PCIDevice *d)
0027b06d 105{
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106 pci_set_word(d->config + PCI_STATUS,
107 PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
01764fe0 108 pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
81a322d4 109 return 0;
0027b06d 110}
502a5395 111
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112static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
113{
114 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
115
116 k->init = versatile_pci_host_init;
117 k->vendor_id = PCI_VENDOR_ID_XILINX;
118 k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30;
119 k->class_id = PCI_CLASS_PROCESSOR_CO;
120}
121
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122static TypeInfo versatile_pci_host_info = {
123 .name = "versatile_pci_host",
124 .parent = TYPE_PCI_DEVICE,
125 .instance_size = sizeof(PCIDevice),
126 .class_init = versatile_pci_host_class_init,
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127};
128
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129static void pci_vpb_class_init(ObjectClass *klass, void *data)
130{
131 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
132
133 sdc->init = pci_vpb_init;
134}
135
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136static TypeInfo pci_vpb_info = {
137 .name = "versatile_pci",
138 .parent = TYPE_SYS_BUS_DEVICE,
139 .instance_size = sizeof(PCIVPBState),
140 .class_init = pci_vpb_class_init,
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141};
142
143static void pci_realview_class_init(ObjectClass *klass, void *data)
144{
145 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
146
147 sdc->init = pci_realview_init;
148}
149
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150static TypeInfo pci_realview_info = {
151 .name = "realview_pci",
152 .parent = TYPE_SYS_BUS_DEVICE,
153 .instance_size = sizeof(PCIVPBState),
154 .class_init = pci_realview_class_init,
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155};
156
83f7d43a 157static void versatile_pci_register_types(void)
0027b06d 158{
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159 type_register_static(&pci_vpb_info);
160 type_register_static(&pci_realview_info);
161 type_register_static(&versatile_pci_host_info);
502a5395 162}
0027b06d 163
83f7d43a 164type_init(versatile_pci_register_types)