[qemu.git] / hw / versatilepb.c

/*
 * ARM Versatile Platform/Application Baseboard System emulation.
 *
 * Copyright (c) 2005-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"
#include "arm-misc.h"
#include "primecell.h"
#include "devices.h"
#include "net.h"
#include "sysemu.h"
#include "pci.h"
#include "usb-ohci.h"
#include "boards.h"
#include "blockdev.h"

/* Primary interrupt controller.  */

typedef struct vpb_sic_state
{
  SysBusDevice busdev;
  uint32_t level;
  uint32_t mask;
  uint32_t pic_enable;
  qemu_irq parent[32];
  int irq;
} vpb_sic_state;

static const VMStateDescription vmstate_vpb_sic = {
    .name = "versatilepb_sic",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(level, vpb_sic_state),
        VMSTATE_UINT32(mask, vpb_sic_state),
        VMSTATE_UINT32(pic_enable, vpb_sic_state),
        VMSTATE_END_OF_LIST()
    }
};

static void vpb_sic_update(vpb_sic_state *s)
{
    uint32_t flags;

    flags = s->level & s->mask;
    qemu_set_irq(s->parent[s->irq], flags != 0);
}

static void vpb_sic_update_pic(vpb_sic_state *s)
{
    int i;
    uint32_t mask;

    for (i = 21; i <= 30; i++) {
        mask = 1u << i;
        if (!(s->pic_enable & mask))
            continue;
        qemu_set_irq(s->parent[i], (s->level & mask) != 0);
    }
}

static void vpb_sic_set_irq(void *opaque, int irq, int level)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;
    if (level)
        s->level |= 1u << irq;
    else
        s->level &= ~(1u << irq);
    if (s->pic_enable & (1u << irq))
        qemu_set_irq(s->parent[irq], level);
    vpb_sic_update(s);
}

static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 0: /* STATUS */
        return s->level & s->mask;
    case 1: /* RAWSTAT */
        return s->level;
    case 2: /* ENABLE */
        return s->mask;
    case 4: /* SOFTINT */
        return s->level & 1;
    case 8: /* PICENABLE */
        return s->pic_enable;
    default:
        printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 2: /* ENSET */
        s->mask |= value;
        break;
    case 3: /* ENCLR */
        s->mask &= ~value;
        break;
    case 4: /* SOFTINTSET */
        if (value)
            s->mask |= 1;
        break;
    case 5: /* SOFTINTCLR */
        if (value)
            s->mask &= ~1u;
        break;
    case 8: /* PICENSET */
        s->pic_enable |= (value & 0x7fe00000);
        vpb_sic_update_pic(s);
        break;
    case 9: /* PICENCLR */
        s->pic_enable &= ~value;
        vpb_sic_update_pic(s);
        break;
    default:
        printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
        return;
    }
    vpb_sic_update(s);
}

static CPUReadMemoryFunc * const vpb_sic_readfn[] = {
   vpb_sic_read,
   vpb_sic_read,
   vpb_sic_read
};

static CPUWriteMemoryFunc * const vpb_sic_writefn[] = {
   vpb_sic_write,
   vpb_sic_write,
   vpb_sic_write
};

static int vpb_sic_init(SysBusDevice *dev)
{
    vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
    int iomemtype;
    int i;

    qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(dev, &s->parent[i]);
    }
    s->irq = 31;
    iomemtype = cpu_register_io_memory(vpb_sic_readfn,
                                       vpb_sic_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    return 0;
}

/* Board init.  */

/* The AB and PB boards both use the same core, just with different
   peripherans and expansion busses.  For now we emulate a subset of the
   PB peripherals and just change the board ID.  */

static struct arm_boot_info versatile_binfo;

static void versatile_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model,
                     int board_id)
{
    CPUState *env;
    ram_addr_t ram_offset;
    qemu_irq *cpu_pic;
    qemu_irq pic[32];
    qemu_irq sic[32];
    DeviceState *dev, *sysctl;
    SysBusDevice *busdev;
    DeviceState *pl041;
    PCIBus *pci_bus;
    NICInfo *nd;
    int n;
    int done_smc = 0;

    if (!cpu_model)
        cpu_model = "arm926";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    ram_offset = qemu_ram_alloc(NULL, "versatile.ram", ram_size);
    /* ??? RAM should repeat to fill physical memory space.  */
    /* SDRAM at address zero.  */
    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);

    sysctl = qdev_create(NULL, "realview_sysctl");
    qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
    qdev_init_nofail(sysctl);
    qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
    sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);

    cpu_pic = arm_pic_init_cpu(env);
    dev = sysbus_create_varargs("pl190", 0x10140000,
                                cpu_pic[0], cpu_pic[1], NULL);
    for (n = 0; n < 32; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }
    dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
    for (n = 0; n < 32; n++) {
        sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
        sic[n] = qdev_get_gpio_in(dev, n);
    }

    sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
    sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);

    dev = qdev_create(NULL, "versatile_pci");
    busdev = sysbus_from_qdev(dev);
    qdev_init_nofail(dev);
    sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
    sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
    sysbus_connect_irq(busdev, 0, sic[27]);
    sysbus_connect_irq(busdev, 1, sic[28]);
    sysbus_connect_irq(busdev, 2, sic[29]);
    sysbus_connect_irq(busdev, 3, sic[30]);
    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");

    /* The Versatile PCI bridge does not provide access to PCI IO space,
       so many of the qemu PCI devices are not useable.  */
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
            smc91c111_init(nd, 0x10010000, sic[25]);
            done_smc = 1;
        } else {
            pci_nic_init_nofail(nd, "rtl8139", NULL);
        }
    }
    if (usb_enabled) {
        usb_ohci_init_pci(pci_bus, -1);
    }
    n = drive_get_max_bus(IF_SCSI);
    while (n >= 0) {
        pci_create_simple(pci_bus, -1, "lsi53c895a");
        n--;
    }

    sysbus_create_simple("pl011", 0x101f1000, pic[12]);
    sysbus_create_simple("pl011", 0x101f2000, pic[13]);
    sysbus_create_simple("pl011", 0x101f3000, pic[14]);
    sysbus_create_simple("pl011", 0x10009000, sic[6]);

    sysbus_create_simple("pl080", 0x10130000, pic[17]);
    sysbus_create_simple("sp804", 0x101e2000, pic[4]);
    sysbus_create_simple("sp804", 0x101e3000, pic[5]);

    /* The versatile/PB actually has a modified Color LCD controller
       that includes hardware cursor support from the PL111.  */
    dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
    /* Wire up the mux control signals from the SYS_CLCD register */
    qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));

    sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
    sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);

    /* Add PL031 Real Time Clock. */
    sysbus_create_simple("pl031", 0x101e8000, pic[10]);

    /* Add PL041 AACI Interface to the LM4549 codec */
    pl041 = qdev_create(NULL, "pl041");
    qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
    qdev_init_nofail(pl041);
    sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
    sysbus_connect_irq(sysbus_from_qdev(pl041), 0, sic[24]);

    /* Memory map for Versatile/PB:  */
    /* 0x10000000 System registers.  */
    /* 0x10001000 PCI controller config registers.  */
    /* 0x10002000 Serial bus interface.  */
    /*  0x10003000 Secondary interrupt controller.  */
    /* 0x10004000 AACI (audio).  */
    /*  0x10005000 MMCI0.  */
    /*  0x10006000 KMI0 (keyboard).  */
    /*  0x10007000 KMI1 (mouse).  */
    /* 0x10008000 Character LCD Interface.  */
    /*  0x10009000 UART3.  */
    /* 0x1000a000 Smart card 1.  */
    /*  0x1000b000 MMCI1.  */
    /*  0x10010000 Ethernet.  */
    /* 0x10020000 USB.  */
    /* 0x10100000 SSMC.  */
    /* 0x10110000 MPMC.  */
    /*  0x10120000 CLCD Controller.  */
    /*  0x10130000 DMA Controller.  */
    /*  0x10140000 Vectored interrupt controller.  */
    /* 0x101d0000 AHB Monitor Interface.  */
    /* 0x101e0000 System Controller.  */
    /* 0x101e1000 Watchdog Interface.  */
    /* 0x101e2000 Timer 0/1.  */
    /* 0x101e3000 Timer 2/3.  */
    /* 0x101e4000 GPIO port 0.  */
    /* 0x101e5000 GPIO port 1.  */
    /* 0x101e6000 GPIO port 2.  */
    /* 0x101e7000 GPIO port 3.  */
    /* 0x101e8000 RTC.  */
    /* 0x101f0000 Smart card 0.  */
    /*  0x101f1000 UART0.  */
    /*  0x101f2000 UART1.  */
    /*  0x101f3000 UART2.  */
    /* 0x101f4000 SSPI.  */

    versatile_binfo.ram_size = ram_size;
    versatile_binfo.kernel_filename = kernel_filename;
    versatile_binfo.kernel_cmdline = kernel_cmdline;
    versatile_binfo.initrd_filename = initrd_filename;
    versatile_binfo.board_id = board_id;
    arm_load_kernel(env, &versatile_binfo);
}

static void vpb_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    versatile_init(ram_size,
                   boot_device,
                   kernel_filename, kernel_cmdline,
                   initrd_filename, cpu_model, 0x183);
}

static void vab_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    versatile_init(ram_size,
                   boot_device,
                   kernel_filename, kernel_cmdline,
                   initrd_filename, cpu_model, 0x25e);
}

static QEMUMachine versatilepb_machine = {
    .name = "versatilepb",
    .desc = "ARM Versatile/PB (ARM926EJ-S)",
    .init = vpb_init,
    .use_scsi = 1,
};

static QEMUMachine versatileab_machine = {
    .name = "versatileab",
    .desc = "ARM Versatile/AB (ARM926EJ-S)",
    .init = vab_init,
    .use_scsi = 1,
};

static void versatile_machine_init(void)
{
    qemu_register_machine(&versatilepb_machine);
    qemu_register_machine(&versatileab_machine);
}

machine_init(versatile_machine_init);

static SysBusDeviceInfo vpb_sic_info = {
    .init = vpb_sic_init,
    .qdev.name = "versatilepb_sic",
    .qdev.size = sizeof(vpb_sic_state),
    .qdev.vmsd = &vmstate_vpb_sic,
    .qdev.no_user = 1,
};

static void versatilepb_register_devices(void)
{
    sysbus_register_withprop(&vpb_sic_info);
}

device_init(versatilepb_register_devices)
Commit	Line	Data
5fafdf24	1	/*
16406950	2	* ARM Versatile Platform/Application Baseboard System emulation.
cdbdb648	3	*
a1bb27b1	4	* Copyright (c) 2005-2007 CodeSourcery.
cdbdb648 PB	5	* Written by Paul Brook
cdbdb648 PB	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
2e9bdce5	10	#include "sysbus.h"
87ecb68b PB	11	#include "arm-misc.h"
	12	#include "primecell.h"
	13	#include "devices.h"
	14	#include "net.h"
	15	#include "sysemu.h"
	16	#include "pci.h"
18e08a55	17	#include "usb-ohci.h"
87ecb68b	18	#include "boards.h"
2446333c	19	#include "blockdev.h"
cdbdb648	20
cdbdb648 PB	21	/* Primary interrupt controller. */
	22
	23	typedef struct vpb_sic_state
	24	{
3950f18b	25	SysBusDevice busdev;
cdbdb648 PB	26	uint32_t level;
	27	uint32_t mask;
	28	uint32_t pic_enable;
97aff481	29	qemu_irq parent[32];
cdbdb648 PB	30	int irq;
	31	} vpb_sic_state;
	32
a796d0ac PM	33	static const VMStateDescription vmstate_vpb_sic = {
	34	.name = "versatilepb_sic",
	35	.version_id = 1,
	36	.minimum_version_id = 1,
	37	.fields = (VMStateField[]) {
	38	VMSTATE_UINT32(level, vpb_sic_state),
	39	VMSTATE_UINT32(mask, vpb_sic_state),
	40	VMSTATE_UINT32(pic_enable, vpb_sic_state),
	41	VMSTATE_END_OF_LIST()
	42	}
	43	};
	44
cdbdb648 PB	45	static void vpb_sic_update(vpb_sic_state *s)
	46	{
	47	uint32_t flags;
	48
	49	flags = s->level & s->mask;
d537cf6c	50	qemu_set_irq(s->parent[s->irq], flags != 0);
cdbdb648 PB	51	}
	52
	53	static void vpb_sic_update_pic(vpb_sic_state *s)
	54	{
	55	int i;
	56	uint32_t mask;
	57
	58	for (i = 21; i <= 30; i++) {
	59	mask = 1u << i;
	60	if (!(s->pic_enable & mask))
	61	continue;
d537cf6c	62	qemu_set_irq(s->parent[i], (s->level & mask) != 0);
cdbdb648 PB	63	}
	64	}
	65
	66	static void vpb_sic_set_irq(void *opaque, int irq, int level)
	67	{
	68	vpb_sic_state s = (vpb_sic_state )opaque;
	69	if (level)
	70	s->level \|= 1u << irq;
	71	else
	72	s->level &= ~(1u << irq);
	73	if (s->pic_enable & (1u << irq))
d537cf6c	74	qemu_set_irq(s->parent[irq], level);
cdbdb648 PB	75	vpb_sic_update(s);
	76	}
	77
c227f099	78	static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	79	{
	80	vpb_sic_state s = (vpb_sic_state )opaque;
	81
cdbdb648 PB	82	switch (offset >> 2) {
	83	case 0: /* STATUS */
	84	return s->level & s->mask;
	85	case 1: /* RAWSTAT */
	86	return s->level;
	87	case 2: /* ENABLE */
	88	return s->mask;
	89	case 4: /* SOFTINT */
	90	return s->level & 1;
	91	case 8: /* PICENABLE */
	92	return s->pic_enable;
	93	default:
e69954b9	94	printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	95	return 0;
	96	}
	97	}
	98
c227f099	99	static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	100	uint32_t value)
	101	{
	102	vpb_sic_state s = (vpb_sic_state )opaque;
cdbdb648 PB	103
	104	switch (offset >> 2) {
	105	case 2: /* ENSET */
	106	s->mask \|= value;
	107	break;
	108	case 3: /* ENCLR */
	109	s->mask &= ~value;
	110	break;
	111	case 4: /* SOFTINTSET */
	112	if (value)
	113	s->mask \|= 1;
	114	break;
	115	case 5: /* SOFTINTCLR */
	116	if (value)
	117	s->mask &= ~1u;
	118	break;
	119	case 8: /* PICENSET */
	120	s->pic_enable \|= (value & 0x7fe00000);
	121	vpb_sic_update_pic(s);
	122	break;
	123	case 9: /* PICENCLR */
	124	s->pic_enable &= ~value;
	125	vpb_sic_update_pic(s);
	126	break;
	127	default:
e69954b9	128	printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	129	return;
	130	}
	131	vpb_sic_update(s);
	132	}
	133
d60efc6b	134	static CPUReadMemoryFunc * const vpb_sic_readfn[] = {
cdbdb648 PB	135	vpb_sic_read,
	136	vpb_sic_read,
	137	vpb_sic_read
	138	};
	139
d60efc6b	140	static CPUWriteMemoryFunc * const vpb_sic_writefn[] = {
cdbdb648 PB	141	vpb_sic_write,
	142	vpb_sic_write,
	143	vpb_sic_write
	144	};
	145
81a322d4	146	static int vpb_sic_init(SysBusDevice *dev)
cdbdb648	147	{
3950f18b	148	vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
cdbdb648	149	int iomemtype;
97aff481	150	int i;
cdbdb648	151
067a3ddc	152	qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
97aff481	153	for (i = 0; i < 32; i++) {
3950f18b	154	sysbus_init_irq(dev, &s->parent[i]);
97aff481	155	}
3950f18b	156	s->irq = 31;
1eed09cb	157	iomemtype = cpu_register_io_memory(vpb_sic_readfn,
2507c12a AG	158	vpb_sic_writefn, s,
2507c12a AG	159	DEVICE_NATIVE_ENDIAN);
3950f18b	160	sysbus_init_mmio(dev, 0x1000, iomemtype);
81a322d4	161	return 0;
cdbdb648 PB	162	}
	163
	164	/* Board init. */
	165
16406950 PB	166	/* The AB and PB boards both use the same core, just with different
	167	peripherans and expansion busses. For now we emulate a subset of the
	168	PB peripherals and just change the board ID. */
cdbdb648	169
f93eb9ff AZ	170	static struct arm_boot_info versatile_binfo;
f93eb9ff AZ	171
c227f099	172	static void versatile_init(ram_addr_t ram_size,
3023f332	173	const char *boot_device,
cdbdb648	174	const char kernel_filename, const char kernel_cmdline,
3371d272 PB	175	const char initrd_filename, const char cpu_model,
3371d272 PB	176	int board_id)
cdbdb648 PB	177	{
cdbdb648 PB	178	CPUState *env;
c227f099	179	ram_addr_t ram_offset;
97aff481 PB	180	qemu_irq *cpu_pic;
97aff481 PB	181	qemu_irq pic[32];
3950f18b	182	qemu_irq sic[32];
242ea2c6	183	DeviceState dev, sysctl;
7d6e771f	184	SysBusDevice *busdev;
d028d02d	185	DeviceState *pl041;
502a5395 PB	186	PCIBus *pci_bus;
	187	NICInfo *nd;
	188	int n;
	189	int done_smc = 0;
cdbdb648	190
3371d272 PB	191	if (!cpu_model)
3371d272 PB	192	cpu_model = "arm926";
aaed909a FB	193	env = cpu_init(cpu_model);
	194	if (!env) {
	195	fprintf(stderr, "Unable to find CPU definition\n");
	196	exit(1);
	197	}
1724f049	198	ram_offset = qemu_ram_alloc(NULL, "versatile.ram", ram_size);
1235fc06	199	/* ??? RAM should repeat to fill physical memory space. */
cdbdb648	200	/* SDRAM at address zero. */
7ffab4d7	201	cpu_register_physical_memory(0, ram_size, ram_offset \| IO_MEM_RAM);
cdbdb648	202
242ea2c6 PM	203	sysctl = qdev_create(NULL, "realview_sysctl");
	204	qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
	205	qdev_init_nofail(sysctl);
	206	qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
	207	sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
	208
97aff481 PB	209	cpu_pic = arm_pic_init_cpu(env);
	210	dev = sysbus_create_varargs("pl190", 0x10140000,
	211	cpu_pic[0], cpu_pic[1], NULL);
	212	for (n = 0; n < 32; n++) {
067a3ddc	213	pic[n] = qdev_get_gpio_in(dev, n);
97aff481	214	}
3950f18b PB	215	dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
	216	for (n = 0; n < 32; n++) {
	217	sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
067a3ddc	218	sic[n] = qdev_get_gpio_in(dev, n);
3950f18b	219	}
86394e96 PB	220
	221	sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
	222	sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
cdbdb648	223
7d6e771f PM	224	dev = qdev_create(NULL, "versatile_pci");
	225	busdev = sysbus_from_qdev(dev);
	226	qdev_init_nofail(dev);
	227	sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
	228	sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
	229	sysbus_connect_irq(busdev, 0, sic[27]);
	230	sysbus_connect_irq(busdev, 1, sic[28]);
	231	sysbus_connect_irq(busdev, 2, sic[29]);
	232	sysbus_connect_irq(busdev, 3, sic[30]);
02e2da45	233	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
0027b06d	234
502a5395 PB	235	/* The Versatile PCI bridge does not provide access to PCI IO space,
	236	so many of the qemu PCI devices are not useable. */
	237	for(n = 0; n < nb_nics; n++) {
	238	nd = &nd_table[n];
0ae18cee	239
e6b3c8ca	240	if (!done_smc && (!nd->model \|\| strcmp(nd->model, "smc91c111") == 0)) {
d537cf6c	241	smc91c111_init(nd, 0x10010000, sic[25]);
0ae18cee	242	done_smc = 1;
cdbdb648	243	} else {
07caea31	244	pci_nic_init_nofail(nd, "rtl8139", NULL);
cdbdb648 PB	245	}
cdbdb648 PB	246	}
0d92ed30	247	if (usb_enabled) {
a67ba3b6	248	usb_ohci_init_pci(pci_bus, -1);
0d92ed30	249	}
9be5dafe PB	250	n = drive_get_max_bus(IF_SCSI);
	251	while (n >= 0) {
	252	pci_create_simple(pci_bus, -1, "lsi53c895a");
	253	n--;
7d8406be	254	}
cdbdb648	255
a7d518a6 PB	256	sysbus_create_simple("pl011", 0x101f1000, pic[12]);
	257	sysbus_create_simple("pl011", 0x101f2000, pic[13]);
	258	sysbus_create_simple("pl011", 0x101f3000, pic[14]);
	259	sysbus_create_simple("pl011", 0x10009000, sic[6]);
cdbdb648	260
b4496b13	261	sysbus_create_simple("pl080", 0x10130000, pic[17]);
6a824ec3 PB	262	sysbus_create_simple("sp804", 0x101e2000, pic[4]);
6a824ec3 PB	263	sysbus_create_simple("sp804", 0x101e3000, pic[5]);
cdbdb648 PB	264
	265	/* The versatile/PB actually has a modified Color LCD controller
	266	that includes hardware cursor support from the PL111. */
242ea2c6 PM	267	dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
	268	/* Wire up the mux control signals from the SYS_CLCD register */
	269	qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
cdbdb648	270
aa9311d8 PB	271	sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
aa9311d8 PB	272	sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
a1bb27b1	273
7e1543c2	274	/* Add PL031 Real Time Clock. */
a63bdb31	275	sysbus_create_simple("pl031", 0x101e8000, pic[10]);
7e1543c2	276
d028d02d MS	277	/* Add PL041 AACI Interface to the LM4549 codec */
	278	pl041 = qdev_create(NULL, "pl041");
	279	qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
	280	qdev_init_nofail(pl041);
	281	sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
	282	sysbus_connect_irq(sysbus_from_qdev(pl041), 0, sic[24]);
	283
16406950	284	/* Memory map for Versatile/PB: */
cdbdb648 PB	285	/* 0x10000000 System registers. */
	286	/* 0x10001000 PCI controller config registers. */
	287	/* 0x10002000 Serial bus interface. */
	288	/* 0x10003000 Secondary interrupt controller. */
	289	/* 0x10004000 AACI (audio). */
a1bb27b1	290	/* 0x10005000 MMCI0. */
cdbdb648 PB	291	/* 0x10006000 KMI0 (keyboard). */
	292	/* 0x10007000 KMI1 (mouse). */
	293	/* 0x10008000 Character LCD Interface. */
	294	/* 0x10009000 UART3. */
	295	/* 0x1000a000 Smart card 1. */
a1bb27b1	296	/* 0x1000b000 MMCI1. */
cdbdb648 PB	297	/* 0x10010000 Ethernet. */
	298	/* 0x10020000 USB. */
	299	/* 0x10100000 SSMC. */
	300	/* 0x10110000 MPMC. */
	301	/* 0x10120000 CLCD Controller. */
	302	/* 0x10130000 DMA Controller. */
	303	/* 0x10140000 Vectored interrupt controller. */
	304	/* 0x101d0000 AHB Monitor Interface. */
	305	/* 0x101e0000 System Controller. */
	306	/* 0x101e1000 Watchdog Interface. */
	307	/* 0x101e2000 Timer 0/1. */
	308	/* 0x101e3000 Timer 2/3. */
	309	/* 0x101e4000 GPIO port 0. */
	310	/* 0x101e5000 GPIO port 1. */
	311	/* 0x101e6000 GPIO port 2. */
	312	/* 0x101e7000 GPIO port 3. */
	313	/* 0x101e8000 RTC. */
	314	/* 0x101f0000 Smart card 0. */
	315	/* 0x101f1000 UART0. */
	316	/* 0x101f2000 UART1. */
	317	/* 0x101f3000 UART2. */
	318	/* 0x101f4000 SSPI. */
	319
f93eb9ff AZ	320	versatile_binfo.ram_size = ram_size;
	321	versatile_binfo.kernel_filename = kernel_filename;
	322	versatile_binfo.kernel_cmdline = kernel_cmdline;
	323	versatile_binfo.initrd_filename = initrd_filename;
	324	versatile_binfo.board_id = board_id;
	325	arm_load_kernel(env, &versatile_binfo);
16406950 PB	326	}
16406950 PB	327
c227f099	328	static void vpb_init(ram_addr_t ram_size,
3023f332	329	const char *boot_device,
16406950	330	const char kernel_filename, const char kernel_cmdline,
94fc95cd	331	const char initrd_filename, const char cpu_model)
16406950	332	{
fbe1b595	333	versatile_init(ram_size,
3023f332	334	boot_device,
16406950	335	kernel_filename, kernel_cmdline,
3371d272	336	initrd_filename, cpu_model, 0x183);
16406950 PB	337	}
16406950 PB	338
c227f099	339	static void vab_init(ram_addr_t ram_size,
3023f332	340	const char *boot_device,
16406950	341	const char kernel_filename, const char kernel_cmdline,
94fc95cd	342	const char initrd_filename, const char cpu_model)
16406950	343	{
fbe1b595	344	versatile_init(ram_size,
3023f332	345	boot_device,
16406950	346	kernel_filename, kernel_cmdline,
3371d272	347	initrd_filename, cpu_model, 0x25e);
cdbdb648 PB	348	}
cdbdb648 PB	349
f80f9ec9	350	static QEMUMachine versatilepb_machine = {
c9b1ae2c BS	351	.name = "versatilepb",
	352	.desc = "ARM Versatile/PB (ARM926EJ-S)",
	353	.init = vpb_init,
	354	.use_scsi = 1,
cdbdb648	355	};
16406950	356
f80f9ec9	357	static QEMUMachine versatileab_machine = {
c9b1ae2c BS	358	.name = "versatileab",
	359	.desc = "ARM Versatile/AB (ARM926EJ-S)",
	360	.init = vab_init,
	361	.use_scsi = 1,
16406950	362	};
3950f18b	363
f80f9ec9 AL	364	static void versatile_machine_init(void)
	365	{
	366	qemu_register_machine(&versatilepb_machine);
	367	qemu_register_machine(&versatileab_machine);
	368	}
	369
	370	machine_init(versatile_machine_init);
	371
a796d0ac PM	372	static SysBusDeviceInfo vpb_sic_info = {
	373	.init = vpb_sic_init,
	374	.qdev.name = "versatilepb_sic",
	375	.qdev.size = sizeof(vpb_sic_state),
	376	.qdev.vmsd = &vmstate_vpb_sic,
	377	.qdev.no_user = 1,
	378	};
	379
3950f18b PB	380	static void versatilepb_register_devices(void)
3950f18b PB	381	{
a796d0ac	382	sysbus_register_withprop(&vpb_sic_info);
3950f18b PB	383	}
	384
	385	device_init(versatilepb_register_devices)