[qemu.git] / hw / versatilepb.c

/*
 * ARM Versatile Platform/Application Baseboard System emulation.
 *
 * Copyright (c) 2005-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licenced under the GPL.
 */

#include "sysbus.h"
#include "arm-misc.h"
#include "primecell.h"
#include "devices.h"
#include "net.h"
#include "sysemu.h"
#include "pci.h"
#include "boards.h"

/* Primary interrupt controller.  */

typedef struct vpb_sic_state
{
  SysBusDevice busdev;
  uint32_t level;
  uint32_t mask;
  uint32_t pic_enable;
  qemu_irq parent[32];
  int irq;
} vpb_sic_state;

static void vpb_sic_update(vpb_sic_state *s)
{
    uint32_t flags;

    flags = s->level & s->mask;
    qemu_set_irq(s->parent[s->irq], flags != 0);
}

static void vpb_sic_update_pic(vpb_sic_state *s)
{
    int i;
    uint32_t mask;

    for (i = 21; i <= 30; i++) {
        mask = 1u << i;
        if (!(s->pic_enable & mask))
            continue;
        qemu_set_irq(s->parent[i], (s->level & mask) != 0);
    }
}

static void vpb_sic_set_irq(void *opaque, int irq, int level)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;
    if (level)
        s->level |= 1u << irq;
    else
        s->level &= ~(1u << irq);
    if (s->pic_enable & (1u << irq))
        qemu_set_irq(s->parent[irq], level);
    vpb_sic_update(s);
}

static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 0: /* STATUS */
        return s->level & s->mask;
    case 1: /* RAWSTAT */
        return s->level;
    case 2: /* ENABLE */
        return s->mask;
    case 4: /* SOFTINT */
        return s->level & 1;
    case 8: /* PICENABLE */
        return s->pic_enable;
    default:
        printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
        return 0;
    }
}

static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    vpb_sic_state *s = (vpb_sic_state *)opaque;

    switch (offset >> 2) {
    case 2: /* ENSET */
        s->mask |= value;
        break;
    case 3: /* ENCLR */
        s->mask &= ~value;
        break;
    case 4: /* SOFTINTSET */
        if (value)
            s->mask |= 1;
        break;
    case 5: /* SOFTINTCLR */
        if (value)
            s->mask &= ~1u;
        break;
    case 8: /* PICENSET */
        s->pic_enable |= (value & 0x7fe00000);
        vpb_sic_update_pic(s);
        break;
    case 9: /* PICENCLR */
        s->pic_enable &= ~value;
        vpb_sic_update_pic(s);
        break;
    default:
        printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
        return;
    }
    vpb_sic_update(s);
}

static CPUReadMemoryFunc *vpb_sic_readfn[] = {
   vpb_sic_read,
   vpb_sic_read,
   vpb_sic_read
};

static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
   vpb_sic_write,
   vpb_sic_write,
   vpb_sic_write
};

static void vpb_sic_init(SysBusDevice *dev)
{
    vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
    int iomemtype;
    int i;

    qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
    for (i = 0; i < 32; i++) {
        sysbus_init_irq(dev, &s->parent[i]);
    }
    s->irq = 31;
    iomemtype = cpu_register_io_memory(vpb_sic_readfn,
                                       vpb_sic_writefn, s);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    /* ??? Save/restore.  */
}

/* Board init.  */

/* The AB and PB boards both use the same core, just with different
   peripherans and expansion busses.  For now we emulate a subset of the
   PB peripherals and just change the board ID.  */

static struct arm_boot_info versatile_binfo;

static void versatile_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model,
                     int board_id)
{
    CPUState *env;
    ram_addr_t ram_offset;
    qemu_irq *cpu_pic;
    qemu_irq pic[32];
    qemu_irq sic[32];
    DeviceState *dev;
    PCIBus *pci_bus;
    NICInfo *nd;
    int n;
    int done_smc = 0;

    if (!cpu_model)
        cpu_model = "arm926";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    ram_offset = qemu_ram_alloc(ram_size);
    /* ??? RAM should repeat to fill physical memory space.  */
    /* SDRAM at address zero.  */
    cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);

    arm_sysctl_init(0x10000000, 0x41007004);
    cpu_pic = arm_pic_init_cpu(env);
    dev = sysbus_create_varargs("pl190", 0x10140000,
                                cpu_pic[0], cpu_pic[1], NULL);
    for (n = 0; n < 32; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }
    dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
    for (n = 0; n < 32; n++) {
        sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
        sic[n] = qdev_get_gpio_in(dev, n);
    }

    sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
    sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);

    dev = sysbus_create_varargs("versatile_pci", 0x40000000,
                                sic[27], sic[28], sic[29], sic[30], NULL);
    pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");

    /* The Versatile PCI bridge does not provide access to PCI IO space,
       so many of the qemu PCI devices are not useable.  */
    for(n = 0; n < nb_nics; n++) {
        nd = &nd_table[n];

        if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) {
            smc91c111_init(nd, 0x10010000, sic[25]);
            done_smc = 1;
        } else {
            pci_nic_init(pci_bus, nd, -1, "rtl8139");
        }
    }
    if (usb_enabled) {
        usb_ohci_init_pci(pci_bus, 3, -1);
    }
    n = drive_get_max_bus(IF_SCSI);
    while (n >= 0) {
        pci_create_simple(pci_bus, -1, "lsi53c895a");
        n--;
    }

    sysbus_create_simple("pl011", 0x101f1000, pic[12]);
    sysbus_create_simple("pl011", 0x101f2000, pic[13]);
    sysbus_create_simple("pl011", 0x101f3000, pic[14]);
    sysbus_create_simple("pl011", 0x10009000, sic[6]);

    sysbus_create_simple("pl080", 0x10130000, pic[17]);
    sysbus_create_simple("sp804", 0x101e2000, pic[4]);
    sysbus_create_simple("sp804", 0x101e3000, pic[5]);

    /* The versatile/PB actually has a modified Color LCD controller
       that includes hardware cursor support from the PL111.  */
    sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);

    sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
    sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);

    /* Add PL031 Real Time Clock. */
    sysbus_create_simple("pl031", 0x101e8000, pic[10]);

    /* Memory map for Versatile/PB:  */
    /* 0x10000000 System registers.  */
    /* 0x10001000 PCI controller config registers.  */
    /* 0x10002000 Serial bus interface.  */
    /*  0x10003000 Secondary interrupt controller.  */
    /* 0x10004000 AACI (audio).  */
    /*  0x10005000 MMCI0.  */
    /*  0x10006000 KMI0 (keyboard).  */
    /*  0x10007000 KMI1 (mouse).  */
    /* 0x10008000 Character LCD Interface.  */
    /*  0x10009000 UART3.  */
    /* 0x1000a000 Smart card 1.  */
    /*  0x1000b000 MMCI1.  */
    /*  0x10010000 Ethernet.  */
    /* 0x10020000 USB.  */
    /* 0x10100000 SSMC.  */
    /* 0x10110000 MPMC.  */
    /*  0x10120000 CLCD Controller.  */
    /*  0x10130000 DMA Controller.  */
    /*  0x10140000 Vectored interrupt controller.  */
    /* 0x101d0000 AHB Monitor Interface.  */
    /* 0x101e0000 System Controller.  */
    /* 0x101e1000 Watchdog Interface.  */
    /* 0x101e2000 Timer 0/1.  */
    /* 0x101e3000 Timer 2/3.  */
    /* 0x101e4000 GPIO port 0.  */
    /* 0x101e5000 GPIO port 1.  */
    /* 0x101e6000 GPIO port 2.  */
    /* 0x101e7000 GPIO port 3.  */
    /* 0x101e8000 RTC.  */
    /* 0x101f0000 Smart card 0.  */
    /*  0x101f1000 UART0.  */
    /*  0x101f2000 UART1.  */
    /*  0x101f3000 UART2.  */
    /* 0x101f4000 SSPI.  */

    versatile_binfo.ram_size = ram_size;
    versatile_binfo.kernel_filename = kernel_filename;
    versatile_binfo.kernel_cmdline = kernel_cmdline;
    versatile_binfo.initrd_filename = initrd_filename;
    versatile_binfo.board_id = board_id;
    arm_load_kernel(env, &versatile_binfo);
}

static void vpb_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    versatile_init(ram_size,
                   boot_device,
                   kernel_filename, kernel_cmdline,
                   initrd_filename, cpu_model, 0x183);
}

static void vab_init(ram_addr_t ram_size,
                     const char *boot_device,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    versatile_init(ram_size,
                   boot_device,
                   kernel_filename, kernel_cmdline,
                   initrd_filename, cpu_model, 0x25e);
}

static QEMUMachine versatilepb_machine = {
    .name = "versatilepb",
    .desc = "ARM Versatile/PB (ARM926EJ-S)",
    .init = vpb_init,
    .use_scsi = 1,
};

static QEMUMachine versatileab_machine = {
    .name = "versatileab",
    .desc = "ARM Versatile/AB (ARM926EJ-S)",
    .init = vab_init,
    .use_scsi = 1,
};

static void versatile_machine_init(void)
{
    qemu_register_machine(&versatilepb_machine);
    qemu_register_machine(&versatileab_machine);
}

machine_init(versatile_machine_init);

static void versatilepb_register_devices(void)
{
    sysbus_register_dev("versatilepb_sic", sizeof(vpb_sic_state),
                        vpb_sic_init);
}

device_init(versatilepb_register_devices)
Commit	Line	Data
5fafdf24	1	/*
16406950	2	* ARM Versatile Platform/Application Baseboard System emulation.
cdbdb648	3	*
a1bb27b1	4	* Copyright (c) 2005-2007 CodeSourcery.
cdbdb648 PB	5	* Written by Paul Brook
	6	*
	7	* This code is licenced under the GPL.
	8	*/
	9
2e9bdce5	10	#include "sysbus.h"
87ecb68b PB	11	#include "arm-misc.h"
	12	#include "primecell.h"
	13	#include "devices.h"
	14	#include "net.h"
	15	#include "sysemu.h"
	16	#include "pci.h"
	17	#include "boards.h"
cdbdb648	18
cdbdb648 PB	19	/* Primary interrupt controller. */
	20
	21	typedef struct vpb_sic_state
	22	{
3950f18b	23	SysBusDevice busdev;
cdbdb648 PB	24	uint32_t level;
	25	uint32_t mask;
	26	uint32_t pic_enable;
97aff481	27	qemu_irq parent[32];
cdbdb648 PB	28	int irq;
	29	} vpb_sic_state;
	30
	31	static void vpb_sic_update(vpb_sic_state *s)
	32	{
	33	uint32_t flags;
	34
	35	flags = s->level & s->mask;
d537cf6c	36	qemu_set_irq(s->parent[s->irq], flags != 0);
cdbdb648 PB	37	}
	38
	39	static void vpb_sic_update_pic(vpb_sic_state *s)
	40	{
	41	int i;
	42	uint32_t mask;
	43
	44	for (i = 21; i <= 30; i++) {
	45	mask = 1u << i;
	46	if (!(s->pic_enable & mask))
	47	continue;
d537cf6c	48	qemu_set_irq(s->parent[i], (s->level & mask) != 0);
cdbdb648 PB	49	}
	50	}
	51
	52	static void vpb_sic_set_irq(void *opaque, int irq, int level)
	53	{
	54	vpb_sic_state s = (vpb_sic_state )opaque;
	55	if (level)
	56	s->level \|= 1u << irq;
	57	else
	58	s->level &= ~(1u << irq);
	59	if (s->pic_enable & (1u << irq))
d537cf6c	60	qemu_set_irq(s->parent[irq], level);
cdbdb648 PB	61	vpb_sic_update(s);
	62	}
	63
	64	static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
	65	{
	66	vpb_sic_state s = (vpb_sic_state )opaque;
	67
cdbdb648 PB	68	switch (offset >> 2) {
	69	case 0: /* STATUS */
	70	return s->level & s->mask;
	71	case 1: /* RAWSTAT */
	72	return s->level;
	73	case 2: /* ENABLE */
	74	return s->mask;
	75	case 4: /* SOFTINT */
	76	return s->level & 1;
	77	case 8: /* PICENABLE */
	78	return s->pic_enable;
	79	default:
e69954b9	80	printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	81	return 0;
	82	}
	83	}
	84
	85	static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
	86	uint32_t value)
	87	{
	88	vpb_sic_state s = (vpb_sic_state )opaque;
cdbdb648 PB	89
	90	switch (offset >> 2) {
	91	case 2: /* ENSET */
	92	s->mask \|= value;
	93	break;
	94	case 3: /* ENCLR */
	95	s->mask &= ~value;
	96	break;
	97	case 4: /* SOFTINTSET */
	98	if (value)
	99	s->mask \|= 1;
	100	break;
	101	case 5: /* SOFTINTCLR */
	102	if (value)
	103	s->mask &= ~1u;
	104	break;
	105	case 8: /* PICENSET */
	106	s->pic_enable \|= (value & 0x7fe00000);
	107	vpb_sic_update_pic(s);
	108	break;
	109	case 9: /* PICENCLR */
	110	s->pic_enable &= ~value;
	111	vpb_sic_update_pic(s);
	112	break;
	113	default:
e69954b9	114	printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
cdbdb648 PB	115	return;
	116	}
	117	vpb_sic_update(s);
	118	}
	119
	120	static CPUReadMemoryFunc *vpb_sic_readfn[] = {
	121	vpb_sic_read,
	122	vpb_sic_read,
	123	vpb_sic_read
	124	};
	125
	126	static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
	127	vpb_sic_write,
	128	vpb_sic_write,
	129	vpb_sic_write
	130	};
	131
3950f18b	132	static void vpb_sic_init(SysBusDevice *dev)
cdbdb648	133	{
3950f18b	134	vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
cdbdb648	135	int iomemtype;
97aff481	136	int i;
cdbdb648	137
067a3ddc	138	qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
97aff481	139	for (i = 0; i < 32; i++) {
3950f18b	140	sysbus_init_irq(dev, &s->parent[i]);
97aff481	141	}
3950f18b	142	s->irq = 31;
1eed09cb	143	iomemtype = cpu_register_io_memory(vpb_sic_readfn,
cdbdb648	144	vpb_sic_writefn, s);
3950f18b	145	sysbus_init_mmio(dev, 0x1000, iomemtype);
cdbdb648	146	/* ??? Save/restore. */
cdbdb648 PB	147	}
	148
	149	/* Board init. */
	150
16406950 PB	151	/* The AB and PB boards both use the same core, just with different
	152	peripherans and expansion busses. For now we emulate a subset of the
	153	PB peripherals and just change the board ID. */
cdbdb648	154
f93eb9ff AZ	155	static struct arm_boot_info versatile_binfo;
f93eb9ff AZ	156
fbe1b595	157	static void versatile_init(ram_addr_t ram_size,
3023f332	158	const char *boot_device,
cdbdb648	159	const char kernel_filename, const char kernel_cmdline,
3371d272 PB	160	const char initrd_filename, const char cpu_model,
3371d272 PB	161	int board_id)
cdbdb648 PB	162	{
cdbdb648 PB	163	CPUState *env;
7ffab4d7	164	ram_addr_t ram_offset;
97aff481 PB	165	qemu_irq *cpu_pic;
97aff481 PB	166	qemu_irq pic[32];
3950f18b	167	qemu_irq sic[32];
97aff481	168	DeviceState *dev;
502a5395 PB	169	PCIBus *pci_bus;
	170	NICInfo *nd;
	171	int n;
	172	int done_smc = 0;
cdbdb648	173
3371d272 PB	174	if (!cpu_model)
3371d272 PB	175	cpu_model = "arm926";
aaed909a FB	176	env = cpu_init(cpu_model);
	177	if (!env) {
	178	fprintf(stderr, "Unable to find CPU definition\n");
	179	exit(1);
	180	}
7ffab4d7	181	ram_offset = qemu_ram_alloc(ram_size);
1235fc06	182	/* ??? RAM should repeat to fill physical memory space. */
cdbdb648	183	/* SDRAM at address zero. */
7ffab4d7	184	cpu_register_physical_memory(0, ram_size, ram_offset \| IO_MEM_RAM);
cdbdb648	185
e69954b9	186	arm_sysctl_init(0x10000000, 0x41007004);
97aff481 PB	187	cpu_pic = arm_pic_init_cpu(env);
	188	dev = sysbus_create_varargs("pl190", 0x10140000,
	189	cpu_pic[0], cpu_pic[1], NULL);
	190	for (n = 0; n < 32; n++) {
067a3ddc	191	pic[n] = qdev_get_gpio_in(dev, n);
97aff481	192	}
3950f18b PB	193	dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
	194	for (n = 0; n < 32; n++) {
	195	sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
067a3ddc	196	sic[n] = qdev_get_gpio_in(dev, n);
3950f18b	197	}
86394e96 PB	198
	199	sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
	200	sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
cdbdb648	201
0027b06d PB	202	dev = sysbus_create_varargs("versatile_pci", 0x40000000,
0027b06d PB	203	sic[27], sic[28], sic[29], sic[30], NULL);
02e2da45	204	pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
0027b06d	205
502a5395 PB	206	/* The Versatile PCI bridge does not provide access to PCI IO space,
	207	so many of the qemu PCI devices are not useable. */
	208	for(n = 0; n < nb_nics; n++) {
	209	nd = &nd_table[n];
0ae18cee AL	210
0ae18cee AL	211	if ((!nd->model && !done_smc) \|\| strcmp(nd->model, "smc91c111") == 0) {
d537cf6c	212	smc91c111_init(nd, 0x10010000, sic[25]);
0ae18cee	213	done_smc = 1;
cdbdb648	214	} else {
cb457d76	215	pci_nic_init(pci_bus, nd, -1, "rtl8139");
cdbdb648 PB	216	}
cdbdb648 PB	217	}
0d92ed30	218	if (usb_enabled) {
e24ad6f1	219	usb_ohci_init_pci(pci_bus, 3, -1);
0d92ed30	220	}
9be5dafe PB	221	n = drive_get_max_bus(IF_SCSI);
	222	while (n >= 0) {
	223	pci_create_simple(pci_bus, -1, "lsi53c895a");
	224	n--;
7d8406be	225	}
cdbdb648	226
a7d518a6 PB	227	sysbus_create_simple("pl011", 0x101f1000, pic[12]);
	228	sysbus_create_simple("pl011", 0x101f2000, pic[13]);
	229	sysbus_create_simple("pl011", 0x101f3000, pic[14]);
	230	sysbus_create_simple("pl011", 0x10009000, sic[6]);
cdbdb648	231
b4496b13	232	sysbus_create_simple("pl080", 0x10130000, pic[17]);
6a824ec3 PB	233	sysbus_create_simple("sp804", 0x101e2000, pic[4]);
6a824ec3 PB	234	sysbus_create_simple("sp804", 0x101e3000, pic[5]);
cdbdb648 PB	235
	236	/* The versatile/PB actually has a modified Color LCD controller
	237	that includes hardware cursor support from the PL111. */
2e9bdce5	238	sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
cdbdb648	239
aa9311d8 PB	240	sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
aa9311d8 PB	241	sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
a1bb27b1	242
7e1543c2	243	/* Add PL031 Real Time Clock. */
a63bdb31	244	sysbus_create_simple("pl031", 0x101e8000, pic[10]);
7e1543c2	245
16406950	246	/* Memory map for Versatile/PB: */
cdbdb648 PB	247	/* 0x10000000 System registers. */
	248	/* 0x10001000 PCI controller config registers. */
	249	/* 0x10002000 Serial bus interface. */
	250	/* 0x10003000 Secondary interrupt controller. */
	251	/* 0x10004000 AACI (audio). */
a1bb27b1	252	/* 0x10005000 MMCI0. */
cdbdb648 PB	253	/* 0x10006000 KMI0 (keyboard). */
	254	/* 0x10007000 KMI1 (mouse). */
	255	/* 0x10008000 Character LCD Interface. */
	256	/* 0x10009000 UART3. */
	257	/* 0x1000a000 Smart card 1. */
a1bb27b1	258	/* 0x1000b000 MMCI1. */
cdbdb648 PB	259	/* 0x10010000 Ethernet. */
	260	/* 0x10020000 USB. */
	261	/* 0x10100000 SSMC. */
	262	/* 0x10110000 MPMC. */
	263	/* 0x10120000 CLCD Controller. */
	264	/* 0x10130000 DMA Controller. */
	265	/* 0x10140000 Vectored interrupt controller. */
	266	/* 0x101d0000 AHB Monitor Interface. */
	267	/* 0x101e0000 System Controller. */
	268	/* 0x101e1000 Watchdog Interface. */
	269	/* 0x101e2000 Timer 0/1. */
	270	/* 0x101e3000 Timer 2/3. */
	271	/* 0x101e4000 GPIO port 0. */
	272	/* 0x101e5000 GPIO port 1. */
	273	/* 0x101e6000 GPIO port 2. */
	274	/* 0x101e7000 GPIO port 3. */
	275	/* 0x101e8000 RTC. */
	276	/* 0x101f0000 Smart card 0. */
	277	/* 0x101f1000 UART0. */
	278	/* 0x101f2000 UART1. */
	279	/* 0x101f3000 UART2. */
	280	/* 0x101f4000 SSPI. */
	281
f93eb9ff AZ	282	versatile_binfo.ram_size = ram_size;
	283	versatile_binfo.kernel_filename = kernel_filename;
	284	versatile_binfo.kernel_cmdline = kernel_cmdline;
	285	versatile_binfo.initrd_filename = initrd_filename;
	286	versatile_binfo.board_id = board_id;
	287	arm_load_kernel(env, &versatile_binfo);
16406950 PB	288	}
16406950 PB	289
fbe1b595	290	static void vpb_init(ram_addr_t ram_size,
3023f332	291	const char *boot_device,
16406950	292	const char kernel_filename, const char kernel_cmdline,
94fc95cd	293	const char initrd_filename, const char cpu_model)
16406950	294	{
fbe1b595	295	versatile_init(ram_size,
3023f332	296	boot_device,
16406950	297	kernel_filename, kernel_cmdline,
3371d272	298	initrd_filename, cpu_model, 0x183);
16406950 PB	299	}
16406950 PB	300
fbe1b595	301	static void vab_init(ram_addr_t ram_size,
3023f332	302	const char *boot_device,
16406950	303	const char kernel_filename, const char kernel_cmdline,
94fc95cd	304	const char initrd_filename, const char cpu_model)
16406950	305	{
fbe1b595	306	versatile_init(ram_size,
3023f332	307	boot_device,
16406950	308	kernel_filename, kernel_cmdline,
3371d272	309	initrd_filename, cpu_model, 0x25e);
cdbdb648 PB	310	}
cdbdb648 PB	311
f80f9ec9	312	static QEMUMachine versatilepb_machine = {
c9b1ae2c BS	313	.name = "versatilepb",
	314	.desc = "ARM Versatile/PB (ARM926EJ-S)",
	315	.init = vpb_init,
	316	.use_scsi = 1,
cdbdb648	317	};
16406950	318
f80f9ec9	319	static QEMUMachine versatileab_machine = {
c9b1ae2c BS	320	.name = "versatileab",
	321	.desc = "ARM Versatile/AB (ARM926EJ-S)",
	322	.init = vab_init,
	323	.use_scsi = 1,
16406950	324	};
3950f18b	325
f80f9ec9 AL	326	static void versatile_machine_init(void)
	327	{
	328	qemu_register_machine(&versatilepb_machine);
	329	qemu_register_machine(&versatileab_machine);
	330	}
	331
	332	machine_init(versatile_machine_init);
	333
3950f18b PB	334	static void versatilepb_register_devices(void)
	335	{
	336	sysbus_register_dev("versatilepb_sic", sizeof(vpb_sic_state),
	337	vpb_sic_init);
	338	}
	339
	340	device_init(versatilepb_register_devices)