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Commit | Line | Data |
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5fafdf24 | 1 | /* |
16406950 | 2 | * ARM Versatile Platform/Application Baseboard System emulation. |
cdbdb648 | 3 | * |
a1bb27b1 | 4 | * Copyright (c) 2005-2007 CodeSourcery. |
cdbdb648 PB |
5 | * Written by Paul Brook |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
cdbdb648 PB |
8 | */ |
9 | ||
2e9bdce5 | 10 | #include "sysbus.h" |
87ecb68b | 11 | #include "arm-misc.h" |
87ecb68b PB |
12 | #include "devices.h" |
13 | #include "net.h" | |
14 | #include "sysemu.h" | |
15 | #include "pci.h" | |
16 | #include "boards.h" | |
2446333c | 17 | #include "blockdev.h" |
62ceeb2c | 18 | #include "exec-memory.h" |
cdbdb648 | 19 | |
cdbdb648 PB |
20 | /* Primary interrupt controller. */ |
21 | ||
22 | typedef struct vpb_sic_state | |
23 | { | |
3950f18b | 24 | SysBusDevice busdev; |
62ceeb2c | 25 | MemoryRegion iomem; |
cdbdb648 PB |
26 | uint32_t level; |
27 | uint32_t mask; | |
28 | uint32_t pic_enable; | |
97aff481 | 29 | qemu_irq parent[32]; |
cdbdb648 PB |
30 | int irq; |
31 | } vpb_sic_state; | |
32 | ||
a796d0ac PM |
33 | static const VMStateDescription vmstate_vpb_sic = { |
34 | .name = "versatilepb_sic", | |
35 | .version_id = 1, | |
36 | .minimum_version_id = 1, | |
37 | .fields = (VMStateField[]) { | |
38 | VMSTATE_UINT32(level, vpb_sic_state), | |
39 | VMSTATE_UINT32(mask, vpb_sic_state), | |
40 | VMSTATE_UINT32(pic_enable, vpb_sic_state), | |
41 | VMSTATE_END_OF_LIST() | |
42 | } | |
43 | }; | |
44 | ||
cdbdb648 PB |
45 | static void vpb_sic_update(vpb_sic_state *s) |
46 | { | |
47 | uint32_t flags; | |
48 | ||
49 | flags = s->level & s->mask; | |
d537cf6c | 50 | qemu_set_irq(s->parent[s->irq], flags != 0); |
cdbdb648 PB |
51 | } |
52 | ||
53 | static void vpb_sic_update_pic(vpb_sic_state *s) | |
54 | { | |
55 | int i; | |
56 | uint32_t mask; | |
57 | ||
58 | for (i = 21; i <= 30; i++) { | |
59 | mask = 1u << i; | |
60 | if (!(s->pic_enable & mask)) | |
61 | continue; | |
d537cf6c | 62 | qemu_set_irq(s->parent[i], (s->level & mask) != 0); |
cdbdb648 PB |
63 | } |
64 | } | |
65 | ||
66 | static void vpb_sic_set_irq(void *opaque, int irq, int level) | |
67 | { | |
68 | vpb_sic_state *s = (vpb_sic_state *)opaque; | |
69 | if (level) | |
70 | s->level |= 1u << irq; | |
71 | else | |
72 | s->level &= ~(1u << irq); | |
73 | if (s->pic_enable & (1u << irq)) | |
d537cf6c | 74 | qemu_set_irq(s->parent[irq], level); |
cdbdb648 PB |
75 | vpb_sic_update(s); |
76 | } | |
77 | ||
62ceeb2c AK |
78 | static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t offset, |
79 | unsigned size) | |
cdbdb648 PB |
80 | { |
81 | vpb_sic_state *s = (vpb_sic_state *)opaque; | |
82 | ||
cdbdb648 PB |
83 | switch (offset >> 2) { |
84 | case 0: /* STATUS */ | |
85 | return s->level & s->mask; | |
86 | case 1: /* RAWSTAT */ | |
87 | return s->level; | |
88 | case 2: /* ENABLE */ | |
89 | return s->mask; | |
90 | case 4: /* SOFTINT */ | |
91 | return s->level & 1; | |
92 | case 8: /* PICENABLE */ | |
93 | return s->pic_enable; | |
94 | default: | |
e69954b9 | 95 | printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset); |
cdbdb648 PB |
96 | return 0; |
97 | } | |
98 | } | |
99 | ||
c227f099 | 100 | static void vpb_sic_write(void *opaque, target_phys_addr_t offset, |
62ceeb2c | 101 | uint64_t value, unsigned size) |
cdbdb648 PB |
102 | { |
103 | vpb_sic_state *s = (vpb_sic_state *)opaque; | |
cdbdb648 PB |
104 | |
105 | switch (offset >> 2) { | |
106 | case 2: /* ENSET */ | |
107 | s->mask |= value; | |
108 | break; | |
109 | case 3: /* ENCLR */ | |
110 | s->mask &= ~value; | |
111 | break; | |
112 | case 4: /* SOFTINTSET */ | |
113 | if (value) | |
114 | s->mask |= 1; | |
115 | break; | |
116 | case 5: /* SOFTINTCLR */ | |
117 | if (value) | |
118 | s->mask &= ~1u; | |
119 | break; | |
120 | case 8: /* PICENSET */ | |
121 | s->pic_enable |= (value & 0x7fe00000); | |
122 | vpb_sic_update_pic(s); | |
123 | break; | |
124 | case 9: /* PICENCLR */ | |
125 | s->pic_enable &= ~value; | |
126 | vpb_sic_update_pic(s); | |
127 | break; | |
128 | default: | |
e69954b9 | 129 | printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset); |
cdbdb648 PB |
130 | return; |
131 | } | |
132 | vpb_sic_update(s); | |
133 | } | |
134 | ||
62ceeb2c AK |
135 | static const MemoryRegionOps vpb_sic_ops = { |
136 | .read = vpb_sic_read, | |
137 | .write = vpb_sic_write, | |
138 | .endianness = DEVICE_NATIVE_ENDIAN, | |
cdbdb648 PB |
139 | }; |
140 | ||
81a322d4 | 141 | static int vpb_sic_init(SysBusDevice *dev) |
cdbdb648 | 142 | { |
3950f18b | 143 | vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev); |
97aff481 | 144 | int i; |
cdbdb648 | 145 | |
067a3ddc | 146 | qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32); |
97aff481 | 147 | for (i = 0; i < 32; i++) { |
3950f18b | 148 | sysbus_init_irq(dev, &s->parent[i]); |
97aff481 | 149 | } |
3950f18b | 150 | s->irq = 31; |
62ceeb2c | 151 | memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000); |
750ecd44 | 152 | sysbus_init_mmio(dev, &s->iomem); |
81a322d4 | 153 | return 0; |
cdbdb648 PB |
154 | } |
155 | ||
156 | /* Board init. */ | |
157 | ||
16406950 PB |
158 | /* The AB and PB boards both use the same core, just with different |
159 | peripherans and expansion busses. For now we emulate a subset of the | |
160 | PB peripherals and just change the board ID. */ | |
cdbdb648 | 161 | |
f93eb9ff AZ |
162 | static struct arm_boot_info versatile_binfo; |
163 | ||
c227f099 | 164 | static void versatile_init(ram_addr_t ram_size, |
3023f332 | 165 | const char *boot_device, |
cdbdb648 | 166 | const char *kernel_filename, const char *kernel_cmdline, |
3371d272 PB |
167 | const char *initrd_filename, const char *cpu_model, |
168 | int board_id) | |
cdbdb648 PB |
169 | { |
170 | CPUState *env; | |
62ceeb2c AK |
171 | MemoryRegion *sysmem = get_system_memory(); |
172 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
97aff481 PB |
173 | qemu_irq *cpu_pic; |
174 | qemu_irq pic[32]; | |
3950f18b | 175 | qemu_irq sic[32]; |
242ea2c6 | 176 | DeviceState *dev, *sysctl; |
7d6e771f | 177 | SysBusDevice *busdev; |
d028d02d | 178 | DeviceState *pl041; |
502a5395 PB |
179 | PCIBus *pci_bus; |
180 | NICInfo *nd; | |
181 | int n; | |
182 | int done_smc = 0; | |
cdbdb648 | 183 | |
3371d272 PB |
184 | if (!cpu_model) |
185 | cpu_model = "arm926"; | |
aaed909a FB |
186 | env = cpu_init(cpu_model); |
187 | if (!env) { | |
188 | fprintf(stderr, "Unable to find CPU definition\n"); | |
189 | exit(1); | |
190 | } | |
c5705a77 AK |
191 | memory_region_init_ram(ram, "versatile.ram", ram_size); |
192 | vmstate_register_ram_global(ram); | |
1235fc06 | 193 | /* ??? RAM should repeat to fill physical memory space. */ |
cdbdb648 | 194 | /* SDRAM at address zero. */ |
62ceeb2c | 195 | memory_region_add_subregion(sysmem, 0, ram); |
cdbdb648 | 196 | |
242ea2c6 PM |
197 | sysctl = qdev_create(NULL, "realview_sysctl"); |
198 | qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); | |
242ea2c6 | 199 | qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000); |
7a65c8cc | 200 | qdev_init_nofail(sysctl); |
242ea2c6 PM |
201 | sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000); |
202 | ||
97aff481 PB |
203 | cpu_pic = arm_pic_init_cpu(env); |
204 | dev = sysbus_create_varargs("pl190", 0x10140000, | |
205 | cpu_pic[0], cpu_pic[1], NULL); | |
206 | for (n = 0; n < 32; n++) { | |
067a3ddc | 207 | pic[n] = qdev_get_gpio_in(dev, n); |
97aff481 | 208 | } |
3950f18b PB |
209 | dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL); |
210 | for (n = 0; n < 32; n++) { | |
211 | sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]); | |
067a3ddc | 212 | sic[n] = qdev_get_gpio_in(dev, n); |
3950f18b | 213 | } |
86394e96 PB |
214 | |
215 | sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]); | |
216 | sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]); | |
cdbdb648 | 217 | |
7d6e771f PM |
218 | dev = qdev_create(NULL, "versatile_pci"); |
219 | busdev = sysbus_from_qdev(dev); | |
220 | qdev_init_nofail(dev); | |
221 | sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */ | |
222 | sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */ | |
223 | sysbus_connect_irq(busdev, 0, sic[27]); | |
224 | sysbus_connect_irq(busdev, 1, sic[28]); | |
225 | sysbus_connect_irq(busdev, 2, sic[29]); | |
226 | sysbus_connect_irq(busdev, 3, sic[30]); | |
02e2da45 | 227 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci"); |
0027b06d | 228 | |
502a5395 PB |
229 | /* The Versatile PCI bridge does not provide access to PCI IO space, |
230 | so many of the qemu PCI devices are not useable. */ | |
231 | for(n = 0; n < nb_nics; n++) { | |
232 | nd = &nd_table[n]; | |
0ae18cee | 233 | |
e6b3c8ca | 234 | if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) { |
d537cf6c | 235 | smc91c111_init(nd, 0x10010000, sic[25]); |
0ae18cee | 236 | done_smc = 1; |
cdbdb648 | 237 | } else { |
07caea31 | 238 | pci_nic_init_nofail(nd, "rtl8139", NULL); |
cdbdb648 PB |
239 | } |
240 | } | |
0d92ed30 | 241 | if (usb_enabled) { |
afb9a60e | 242 | pci_create_simple(pci_bus, -1, "pci-ohci"); |
0d92ed30 | 243 | } |
9be5dafe PB |
244 | n = drive_get_max_bus(IF_SCSI); |
245 | while (n >= 0) { | |
246 | pci_create_simple(pci_bus, -1, "lsi53c895a"); | |
247 | n--; | |
7d8406be | 248 | } |
cdbdb648 | 249 | |
a7d518a6 PB |
250 | sysbus_create_simple("pl011", 0x101f1000, pic[12]); |
251 | sysbus_create_simple("pl011", 0x101f2000, pic[13]); | |
252 | sysbus_create_simple("pl011", 0x101f3000, pic[14]); | |
253 | sysbus_create_simple("pl011", 0x10009000, sic[6]); | |
cdbdb648 | 254 | |
b4496b13 | 255 | sysbus_create_simple("pl080", 0x10130000, pic[17]); |
6a824ec3 PB |
256 | sysbus_create_simple("sp804", 0x101e2000, pic[4]); |
257 | sysbus_create_simple("sp804", 0x101e3000, pic[5]); | |
cdbdb648 PB |
258 | |
259 | /* The versatile/PB actually has a modified Color LCD controller | |
260 | that includes hardware cursor support from the PL111. */ | |
242ea2c6 PM |
261 | dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]); |
262 | /* Wire up the mux control signals from the SYS_CLCD register */ | |
263 | qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0)); | |
cdbdb648 | 264 | |
aa9311d8 PB |
265 | sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL); |
266 | sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL); | |
a1bb27b1 | 267 | |
7e1543c2 | 268 | /* Add PL031 Real Time Clock. */ |
a63bdb31 | 269 | sysbus_create_simple("pl031", 0x101e8000, pic[10]); |
7e1543c2 | 270 | |
d028d02d MS |
271 | /* Add PL041 AACI Interface to the LM4549 codec */ |
272 | pl041 = qdev_create(NULL, "pl041"); | |
273 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); | |
274 | qdev_init_nofail(pl041); | |
275 | sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000); | |
276 | sysbus_connect_irq(sysbus_from_qdev(pl041), 0, sic[24]); | |
277 | ||
16406950 | 278 | /* Memory map for Versatile/PB: */ |
cdbdb648 PB |
279 | /* 0x10000000 System registers. */ |
280 | /* 0x10001000 PCI controller config registers. */ | |
281 | /* 0x10002000 Serial bus interface. */ | |
282 | /* 0x10003000 Secondary interrupt controller. */ | |
283 | /* 0x10004000 AACI (audio). */ | |
a1bb27b1 | 284 | /* 0x10005000 MMCI0. */ |
cdbdb648 PB |
285 | /* 0x10006000 KMI0 (keyboard). */ |
286 | /* 0x10007000 KMI1 (mouse). */ | |
287 | /* 0x10008000 Character LCD Interface. */ | |
288 | /* 0x10009000 UART3. */ | |
289 | /* 0x1000a000 Smart card 1. */ | |
a1bb27b1 | 290 | /* 0x1000b000 MMCI1. */ |
cdbdb648 PB |
291 | /* 0x10010000 Ethernet. */ |
292 | /* 0x10020000 USB. */ | |
293 | /* 0x10100000 SSMC. */ | |
294 | /* 0x10110000 MPMC. */ | |
295 | /* 0x10120000 CLCD Controller. */ | |
296 | /* 0x10130000 DMA Controller. */ | |
297 | /* 0x10140000 Vectored interrupt controller. */ | |
298 | /* 0x101d0000 AHB Monitor Interface. */ | |
299 | /* 0x101e0000 System Controller. */ | |
300 | /* 0x101e1000 Watchdog Interface. */ | |
301 | /* 0x101e2000 Timer 0/1. */ | |
302 | /* 0x101e3000 Timer 2/3. */ | |
303 | /* 0x101e4000 GPIO port 0. */ | |
304 | /* 0x101e5000 GPIO port 1. */ | |
305 | /* 0x101e6000 GPIO port 2. */ | |
306 | /* 0x101e7000 GPIO port 3. */ | |
307 | /* 0x101e8000 RTC. */ | |
308 | /* 0x101f0000 Smart card 0. */ | |
309 | /* 0x101f1000 UART0. */ | |
310 | /* 0x101f2000 UART1. */ | |
311 | /* 0x101f3000 UART2. */ | |
312 | /* 0x101f4000 SSPI. */ | |
313 | ||
f93eb9ff AZ |
314 | versatile_binfo.ram_size = ram_size; |
315 | versatile_binfo.kernel_filename = kernel_filename; | |
316 | versatile_binfo.kernel_cmdline = kernel_cmdline; | |
317 | versatile_binfo.initrd_filename = initrd_filename; | |
318 | versatile_binfo.board_id = board_id; | |
319 | arm_load_kernel(env, &versatile_binfo); | |
16406950 PB |
320 | } |
321 | ||
c227f099 | 322 | static void vpb_init(ram_addr_t ram_size, |
3023f332 | 323 | const char *boot_device, |
16406950 | 324 | const char *kernel_filename, const char *kernel_cmdline, |
94fc95cd | 325 | const char *initrd_filename, const char *cpu_model) |
16406950 | 326 | { |
fbe1b595 | 327 | versatile_init(ram_size, |
3023f332 | 328 | boot_device, |
16406950 | 329 | kernel_filename, kernel_cmdline, |
3371d272 | 330 | initrd_filename, cpu_model, 0x183); |
16406950 PB |
331 | } |
332 | ||
c227f099 | 333 | static void vab_init(ram_addr_t ram_size, |
3023f332 | 334 | const char *boot_device, |
16406950 | 335 | const char *kernel_filename, const char *kernel_cmdline, |
94fc95cd | 336 | const char *initrd_filename, const char *cpu_model) |
16406950 | 337 | { |
fbe1b595 | 338 | versatile_init(ram_size, |
3023f332 | 339 | boot_device, |
16406950 | 340 | kernel_filename, kernel_cmdline, |
3371d272 | 341 | initrd_filename, cpu_model, 0x25e); |
cdbdb648 PB |
342 | } |
343 | ||
f80f9ec9 | 344 | static QEMUMachine versatilepb_machine = { |
c9b1ae2c BS |
345 | .name = "versatilepb", |
346 | .desc = "ARM Versatile/PB (ARM926EJ-S)", | |
347 | .init = vpb_init, | |
348 | .use_scsi = 1, | |
cdbdb648 | 349 | }; |
16406950 | 350 | |
f80f9ec9 | 351 | static QEMUMachine versatileab_machine = { |
c9b1ae2c BS |
352 | .name = "versatileab", |
353 | .desc = "ARM Versatile/AB (ARM926EJ-S)", | |
354 | .init = vab_init, | |
355 | .use_scsi = 1, | |
16406950 | 356 | }; |
3950f18b | 357 | |
f80f9ec9 AL |
358 | static void versatile_machine_init(void) |
359 | { | |
360 | qemu_register_machine(&versatilepb_machine); | |
361 | qemu_register_machine(&versatileab_machine); | |
362 | } | |
363 | ||
364 | machine_init(versatile_machine_init); | |
365 | ||
999e12bb AL |
366 | static void vpb_sic_class_init(ObjectClass *klass, void *data) |
367 | { | |
39bffca2 | 368 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
369 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
370 | ||
371 | k->init = vpb_sic_init; | |
39bffca2 AL |
372 | dc->no_user = 1; |
373 | dc->vmsd = &vmstate_vpb_sic; | |
999e12bb AL |
374 | } |
375 | ||
39bffca2 AL |
376 | static TypeInfo vpb_sic_info = { |
377 | .name = "versatilepb_sic", | |
378 | .parent = TYPE_SYS_BUS_DEVICE, | |
379 | .instance_size = sizeof(vpb_sic_state), | |
380 | .class_init = vpb_sic_class_init, | |
a796d0ac PM |
381 | }; |
382 | ||
83f7d43a | 383 | static void versatilepb_register_types(void) |
3950f18b | 384 | { |
39bffca2 | 385 | type_register_static(&vpb_sic_info); |
3950f18b PB |
386 | } |
387 | ||
83f7d43a | 388 | type_init(versatilepb_register_types) |