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2055283b PM |
1 | /* |
2 | * ARM Versatile Express emulation. | |
3 | * | |
4 | * Copyright (c) 2010 - 2011 B Labs Ltd. | |
5 | * Copyright (c) 2011 Linaro Limited | |
6 | * Written by Bahadir Balban, Amit Mahajan, Peter Maydell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
6b620ca3 PB |
19 | * |
20 | * Contributions after 2012-01-13 are licensed under the terms of the | |
21 | * GNU GPL, version 2 or (at your option) any later version. | |
2055283b PM |
22 | */ |
23 | ||
24 | #include "sysbus.h" | |
25 | #include "arm-misc.h" | |
26 | #include "primecell.h" | |
27 | #include "devices.h" | |
28 | #include "net.h" | |
29 | #include "sysemu.h" | |
30 | #include "boards.h" | |
e6d17b05 | 31 | #include "exec-memory.h" |
2055283b | 32 | |
2055283b PM |
33 | #define VEXPRESS_BOARD_ID 0x8e0 |
34 | ||
aac1e02c | 35 | static struct arm_boot_info vexpress_binfo; |
2558e0a6 PM |
36 | |
37 | /* Address maps for peripherals: | |
38 | * the Versatile Express motherboard has two possible maps, | |
39 | * the "legacy" one (used for A9) and the "Cortex-A Series" | |
40 | * map (used for newer cores). | |
41 | * Individual daughterboards can also have different maps for | |
42 | * their peripherals. | |
43 | */ | |
44 | ||
45 | enum { | |
46 | VE_SYSREGS, | |
47 | VE_SP810, | |
48 | VE_SERIALPCI, | |
49 | VE_PL041, | |
50 | VE_MMCI, | |
51 | VE_KMI0, | |
52 | VE_KMI1, | |
53 | VE_UART0, | |
54 | VE_UART1, | |
55 | VE_UART2, | |
56 | VE_UART3, | |
57 | VE_WDT, | |
58 | VE_TIMER01, | |
59 | VE_TIMER23, | |
60 | VE_SERIALDVI, | |
61 | VE_RTC, | |
62 | VE_COMPACTFLASH, | |
63 | VE_CLCD, | |
64 | VE_NORFLASH0, | |
65 | VE_NORFLASH0ALIAS, | |
66 | VE_NORFLASH1, | |
67 | VE_SRAM, | |
68 | VE_VIDEORAM, | |
69 | VE_ETHERNET, | |
70 | VE_USB, | |
71 | VE_DAPROM, | |
72 | }; | |
73 | ||
74 | static target_phys_addr_t motherboard_legacy_map[] = { | |
75 | /* CS7: 0x10000000 .. 0x10020000 */ | |
76 | [VE_SYSREGS] = 0x10000000, | |
77 | [VE_SP810] = 0x10001000, | |
78 | [VE_SERIALPCI] = 0x10002000, | |
79 | [VE_PL041] = 0x10004000, | |
80 | [VE_MMCI] = 0x10005000, | |
81 | [VE_KMI0] = 0x10006000, | |
82 | [VE_KMI1] = 0x10007000, | |
83 | [VE_UART0] = 0x10009000, | |
84 | [VE_UART1] = 0x1000a000, | |
85 | [VE_UART2] = 0x1000b000, | |
86 | [VE_UART3] = 0x1000c000, | |
87 | [VE_WDT] = 0x1000f000, | |
88 | [VE_TIMER01] = 0x10011000, | |
89 | [VE_TIMER23] = 0x10012000, | |
90 | [VE_SERIALDVI] = 0x10016000, | |
91 | [VE_RTC] = 0x10017000, | |
92 | [VE_COMPACTFLASH] = 0x1001a000, | |
93 | [VE_CLCD] = 0x1001f000, | |
94 | /* CS0: 0x40000000 .. 0x44000000 */ | |
95 | [VE_NORFLASH0] = 0x40000000, | |
96 | /* CS1: 0x44000000 .. 0x48000000 */ | |
97 | [VE_NORFLASH1] = 0x44000000, | |
98 | /* CS2: 0x48000000 .. 0x4a000000 */ | |
99 | [VE_SRAM] = 0x48000000, | |
100 | /* CS3: 0x4c000000 .. 0x50000000 */ | |
101 | [VE_VIDEORAM] = 0x4c000000, | |
102 | [VE_ETHERNET] = 0x4e000000, | |
103 | [VE_USB] = 0x4f000000, | |
2055283b PM |
104 | }; |
105 | ||
106 | static void vexpress_a9_init(ram_addr_t ram_size, | |
107 | const char *boot_device, | |
108 | const char *kernel_filename, const char *kernel_cmdline, | |
109 | const char *initrd_filename, const char *cpu_model) | |
110 | { | |
111 | CPUState *env = NULL; | |
e6d17b05 AK |
112 | MemoryRegion *sysmem = get_system_memory(); |
113 | MemoryRegion *ram = g_new(MemoryRegion, 1); | |
114 | MemoryRegion *lowram = g_new(MemoryRegion, 1); | |
115 | MemoryRegion *vram = g_new(MemoryRegion, 1); | |
116 | MemoryRegion *sram = g_new(MemoryRegion, 1); | |
03a0e944 | 117 | DeviceState *dev, *sysctl, *pl041; |
2055283b PM |
118 | SysBusDevice *busdev; |
119 | qemu_irq *irqp; | |
120 | qemu_irq pic[64]; | |
121 | int n; | |
122 | qemu_irq cpu_irq[4]; | |
123 | uint32_t proc_id; | |
124 | uint32_t sys_id; | |
125 | ram_addr_t low_ram_size, vram_size, sram_size; | |
2558e0a6 | 126 | target_phys_addr_t *map = motherboard_legacy_map; |
2055283b PM |
127 | |
128 | if (!cpu_model) { | |
129 | cpu_model = "cortex-a9"; | |
130 | } | |
131 | ||
132 | for (n = 0; n < smp_cpus; n++) { | |
133 | env = cpu_init(cpu_model); | |
134 | if (!env) { | |
135 | fprintf(stderr, "Unable to find CPU definition\n"); | |
136 | exit(1); | |
137 | } | |
138 | irqp = arm_pic_init_cpu(env); | |
139 | cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ]; | |
140 | } | |
141 | ||
142 | if (ram_size > 0x40000000) { | |
143 | /* 1GB is the maximum the address space permits */ | |
144 | fprintf(stderr, "vexpress: cannot model more than 1GB RAM\n"); | |
145 | exit(1); | |
146 | } | |
147 | ||
c5705a77 AK |
148 | memory_region_init_ram(ram, "vexpress.highmem", ram_size); |
149 | vmstate_register_ram_global(ram); | |
2055283b PM |
150 | low_ram_size = ram_size; |
151 | if (low_ram_size > 0x4000000) { | |
152 | low_ram_size = 0x4000000; | |
153 | } | |
154 | /* RAM is from 0x60000000 upwards. The bottom 64MB of the | |
155 | * address space should in theory be remappable to various | |
156 | * things including ROM or RAM; we always map the RAM there. | |
157 | */ | |
e6d17b05 AK |
158 | memory_region_init_alias(lowram, "vexpress.lowmem", ram, 0, low_ram_size); |
159 | memory_region_add_subregion(sysmem, 0x0, lowram); | |
160 | memory_region_add_subregion(sysmem, 0x60000000, ram); | |
2055283b PM |
161 | |
162 | /* 0x1e000000 A9MPCore (SCU) private memory region */ | |
163 | dev = qdev_create(NULL, "a9mpcore_priv"); | |
164 | qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); | |
165 | qdev_init_nofail(dev); | |
166 | busdev = sysbus_from_qdev(dev); | |
167 | vexpress_binfo.smp_priv_base = 0x1e000000; | |
168 | sysbus_mmio_map(busdev, 0, vexpress_binfo.smp_priv_base); | |
169 | for (n = 0; n < smp_cpus; n++) { | |
170 | sysbus_connect_irq(busdev, n, cpu_irq[n]); | |
171 | } | |
172 | /* Interrupts [42:0] are from the motherboard; | |
173 | * [47:43] are reserved; [63:48] are daughterboard | |
174 | * peripherals. Note that some documentation numbers | |
175 | * external interrupts starting from 32 (because the | |
176 | * A9MP has internal interrupts 0..31). | |
177 | */ | |
178 | for (n = 0; n < 64; n++) { | |
179 | pic[n] = qdev_get_gpio_in(dev, n); | |
180 | } | |
181 | ||
2558e0a6 PM |
182 | /* Motherboard peripherals: the wiring is the same but the |
183 | * addresses vary between the legacy and A-Series memory maps. | |
184 | */ | |
185 | ||
2055283b PM |
186 | sys_id = 0x1190f500; |
187 | proc_id = 0x0c000191; | |
188 | ||
2055283b PM |
189 | sysctl = qdev_create(NULL, "realview_sysctl"); |
190 | qdev_prop_set_uint32(sysctl, "sys_id", sys_id); | |
2055283b | 191 | qdev_prop_set_uint32(sysctl, "proc_id", proc_id); |
7a65c8cc | 192 | qdev_init_nofail(sysctl); |
2558e0a6 PM |
193 | sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, map[VE_SYSREGS]); |
194 | ||
195 | /* VE_SP810: not modelled */ | |
196 | /* VE_SERIALPCI: not modelled */ | |
2055283b | 197 | |
03a0e944 PM |
198 | pl041 = qdev_create(NULL, "pl041"); |
199 | qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512); | |
200 | qdev_init_nofail(pl041); | |
2558e0a6 | 201 | sysbus_mmio_map(sysbus_from_qdev(pl041), 0, map[VE_PL041]); |
03a0e944 | 202 | sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[11]); |
2055283b | 203 | |
2558e0a6 | 204 | dev = sysbus_create_varargs("pl181", map[VE_MMCI], pic[9], pic[10], NULL); |
2055283b PM |
205 | /* Wire up MMC card detect and read-only signals */ |
206 | qdev_connect_gpio_out(dev, 0, | |
207 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT)); | |
208 | qdev_connect_gpio_out(dev, 1, | |
209 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN)); | |
210 | ||
2558e0a6 PM |
211 | sysbus_create_simple("pl050_keyboard", map[VE_KMI0], pic[12]); |
212 | sysbus_create_simple("pl050_mouse", map[VE_KMI1], pic[13]); | |
2055283b | 213 | |
2558e0a6 PM |
214 | sysbus_create_simple("pl011", map[VE_UART0], pic[5]); |
215 | sysbus_create_simple("pl011", map[VE_UART1], pic[6]); | |
216 | sysbus_create_simple("pl011", map[VE_UART2], pic[7]); | |
217 | sysbus_create_simple("pl011", map[VE_UART3], pic[8]); | |
2055283b | 218 | |
2558e0a6 PM |
219 | sysbus_create_simple("sp804", map[VE_TIMER01], pic[2]); |
220 | sysbus_create_simple("sp804", map[VE_TIMER23], pic[3]); | |
2055283b | 221 | |
2558e0a6 | 222 | /* VE_SERIALDVI: not modelled */ |
2055283b | 223 | |
2558e0a6 | 224 | sysbus_create_simple("pl031", map[VE_RTC], pic[4]); /* RTC */ |
2055283b | 225 | |
2558e0a6 | 226 | /* VE_COMPACTFLASH: not modelled */ |
2055283b | 227 | |
2558e0a6 | 228 | /* VE_CLCD: not modelled (we use the daughterboard CLCD only) */ |
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229 | |
230 | /* Daughterboard peripherals : 0x10020000 .. 0x20000000 */ | |
231 | ||
232 | /* 0x10020000 PL111 CLCD (daughterboard) */ | |
acb9b722 | 233 | sysbus_create_simple("pl111", 0x10020000, pic[44]); |
2055283b PM |
234 | |
235 | /* 0x10060000 AXI RAM */ | |
236 | /* 0x100e0000 PL341 Dynamic Memory Controller */ | |
237 | /* 0x100e1000 PL354 Static Memory Controller */ | |
238 | /* 0x100e2000 System Configuration Controller */ | |
239 | ||
240 | sysbus_create_simple("sp804", 0x100e4000, pic[48]); | |
241 | /* 0x100e5000 SP805 Watchdog module */ | |
242 | /* 0x100e6000 BP147 TrustZone Protection Controller */ | |
243 | /* 0x100e9000 PL301 'Fast' AXI matrix */ | |
244 | /* 0x100ea000 PL301 'Slow' AXI matrix */ | |
245 | /* 0x100ec000 TrustZone Address Space Controller */ | |
246 | /* 0x10200000 CoreSight debug APB */ | |
247 | /* 0x1e00a000 PL310 L2 Cache Controller */ | |
5a157588 | 248 | sysbus_create_varargs("l2x0", 0x1e00a000, NULL); |
2055283b | 249 | |
2558e0a6 PM |
250 | /* VE_NORFLASH0: not modelled */ |
251 | /* VE_NORFLASH0ALIAS: not modelled */ | |
252 | /* VE_NORFLASH1: not modelled */ | |
253 | ||
2055283b | 254 | sram_size = 0x2000000; |
c5705a77 AK |
255 | memory_region_init_ram(sram, "vexpress.sram", sram_size); |
256 | vmstate_register_ram_global(sram); | |
2558e0a6 | 257 | memory_region_add_subregion(sysmem, map[VE_SRAM], sram); |
2055283b | 258 | |
2055283b | 259 | vram_size = 0x800000; |
c5705a77 AK |
260 | memory_region_init_ram(vram, "vexpress.vram", vram_size); |
261 | vmstate_register_ram_global(vram); | |
2558e0a6 | 262 | memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); |
2055283b PM |
263 | |
264 | /* 0x4e000000 LAN9118 Ethernet */ | |
265 | if (nd_table[0].vlan) { | |
2558e0a6 | 266 | lan9118_init(&nd_table[0], map[VE_ETHERNET], pic[15]); |
2055283b PM |
267 | } |
268 | ||
2558e0a6 PM |
269 | /* VE_USB: not modelled */ |
270 | ||
271 | /* VE_DAPROM: not modelled */ | |
2055283b | 272 | |
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273 | vexpress_binfo.ram_size = ram_size; |
274 | vexpress_binfo.kernel_filename = kernel_filename; | |
275 | vexpress_binfo.kernel_cmdline = kernel_cmdline; | |
276 | vexpress_binfo.initrd_filename = initrd_filename; | |
277 | vexpress_binfo.nb_cpus = smp_cpus; | |
278 | vexpress_binfo.board_id = VEXPRESS_BOARD_ID; | |
279 | vexpress_binfo.loader_start = 0x60000000; | |
aac1e02c | 280 | vexpress_binfo.smp_loader_start = map[VE_SRAM]; |
2558e0a6 | 281 | vexpress_binfo.smp_bootreg_addr = map[VE_SYSREGS] + 0x30; |
2055283b PM |
282 | arm_load_kernel(first_cpu, &vexpress_binfo); |
283 | } | |
284 | ||
285 | ||
286 | static QEMUMachine vexpress_a9_machine = { | |
287 | .name = "vexpress-a9", | |
288 | .desc = "ARM Versatile Express for Cortex-A9", | |
289 | .init = vexpress_a9_init, | |
290 | .use_scsi = 1, | |
291 | .max_cpus = 4, | |
292 | }; | |
293 | ||
294 | static void vexpress_machine_init(void) | |
295 | { | |
296 | qemu_register_machine(&vexpress_a9_machine); | |
297 | } | |
298 | ||
299 | machine_init(vexpress_machine_init); |