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target-mips: Remove unused inline function
[qemu.git] / hw / vga.c
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e89f66ec 1/*
4fa0f5d2 2 * QEMU VGA Emulator.
5fafdf24 3 *
e89f66ec 4 * Copyright (c) 2003 Fabrice Bellard
5fafdf24 5 *
e89f66ec
FB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b 24#include "hw.h"
5e55efc9 25#include "vga.h"
87ecb68b
PB		 26#include "console.h"
27#include "pc.h"
28#include "pci.h"
798b0c25 29#include "vga_int.h"
94470844 30#include "pixel_ops.h"
cb5a7aa8 31#include "qemu-timer.h"
c65adf9b 32#include "xen.h"
72750018 33#include "trace.h"
e89f66ec 34
e89f66ec 35//#define DEBUG_VGA
17b0018b 36//#define DEBUG_VGA_MEM
a41bc9af
FB		 37//#define DEBUG_VGA_REG
38
4fa0f5d2
FB		 39//#define DEBUG_BOCHS_VBE
40
47c012e2
BS		 41/*
42 * Video Graphics Array (VGA)
43 *
44 * Chipset docs for original IBM VGA:
45 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
46 *
47 * FreeVGA site:
48 * http://www.osdever.net/FreeVGA/home.htm
49 *
50 * Standard VGA features and Bochs VBE extensions are implemented.
51 */
52
e89f66ec 53/* force some bits to zero */
798b0c25 54const uint8_t sr_mask[8] = {
9e622b15
BS		 55 0x03,
56 0x3d,
57 0x0f,
58 0x3f,
59 0x0e,
60 0x00,
61 0x00,
62 0xff,
e89f66ec
FB		 63};
64
798b0c25 65const uint8_t gr_mask[16] = {
9e622b15
BS		 66 0x0f, /* 0x00 */
67 0x0f, /* 0x01 */
68 0x0f, /* 0x02 */
69 0x1f, /* 0x03 */
70 0x03, /* 0x04 */
71 0x7b, /* 0x05 */
72 0x0f, /* 0x06 */
73 0x0f, /* 0x07 */
74 0xff, /* 0x08 */
75 0x00, /* 0x09 */
76 0x00, /* 0x0a */
77 0x00, /* 0x0b */
78 0x00, /* 0x0c */
79 0x00, /* 0x0d */
80 0x00, /* 0x0e */
81 0x00, /* 0x0f */
e89f66ec
FB		 82};
83
84#define cbswap_32(__x) \
85((uint32_t)( \
86 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
87 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
88 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
89 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
90
e2542fe2 91#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 92#define PAT(x) cbswap_32(x)
93#else
94#define PAT(x) (x)
95#endif
96
e2542fe2 97#ifdef HOST_WORDS_BIGENDIAN
b8ed223b
FB		 98#define BIG 1
99#else
100#define BIG 0
101#endif
102
e2542fe2 103#ifdef HOST_WORDS_BIGENDIAN
b8ed223b
FB		 104#define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
105#else
106#define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
107#endif
108
e89f66ec
FB		 109static const uint32_t mask16[16] = {
110 PAT(0x00000000),
111 PAT(0x000000ff),
112 PAT(0x0000ff00),
113 PAT(0x0000ffff),
114 PAT(0x00ff0000),
115 PAT(0x00ff00ff),
116 PAT(0x00ffff00),
117 PAT(0x00ffffff),
118 PAT(0xff000000),
119 PAT(0xff0000ff),
120 PAT(0xff00ff00),
121 PAT(0xff00ffff),
122 PAT(0xffff0000),
123 PAT(0xffff00ff),
124 PAT(0xffffff00),
125 PAT(0xffffffff),
126};
127
128#undef PAT
129
e2542fe2 130#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 131#define PAT(x) (x)
132#else
133#define PAT(x) cbswap_32(x)
134#endif
135
136static const uint32_t dmask16[16] = {
137 PAT(0x00000000),
138 PAT(0x000000ff),
139 PAT(0x0000ff00),
140 PAT(0x0000ffff),
141 PAT(0x00ff0000),
142 PAT(0x00ff00ff),
143 PAT(0x00ffff00),
144 PAT(0x00ffffff),
145 PAT(0xff000000),
146 PAT(0xff0000ff),
147 PAT(0xff00ff00),
148 PAT(0xff00ffff),
149 PAT(0xffff0000),
150 PAT(0xffff00ff),
151 PAT(0xffffff00),
152 PAT(0xffffffff),
153};
154
155static const uint32_t dmask4[4] = {
156 PAT(0x00000000),
157 PAT(0x0000ffff),
158 PAT(0xffff0000),
159 PAT(0xffffffff),
160};
161
162static uint32_t expand4[256];
163static uint16_t expand2[256];
17b0018b 164static uint8_t expand4to8[16];
e89f66ec 165
45efb161 166static void vga_screen_dump(void *opaque, const char *filename, bool cswitch);
95219897 167
80763888
JK		 168static void vga_update_memory_access(VGACommonState *s)
169{
170 MemoryRegion *region, *old_region = s->chain4_alias;
171 target_phys_addr_t base, offset, size;
172
173 s->chain4_alias = NULL;
174
5e55efc9
BS		 175 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
176 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
80763888 177 offset = 0;
5e55efc9 178 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
80763888
JK		 179 case 0:
180 base = 0xa0000;
181 size = 0x20000;
182 break;
183 case 1:
184 base = 0xa0000;
185 size = 0x10000;
186 offset = s->bank_offset;
187 break;
188 case 2:
189 base = 0xb0000;
190 size = 0x8000;
191 break;
192 case 3:
f065aa0a 193 default:
80763888
JK		 194 base = 0xb8000;
195 size = 0x8000;
196 break;
197 }
71579cae 198 base += isa_mem_base;
80763888
JK		 199 region = g_malloc(sizeof(*region));
200 memory_region_init_alias(region, "vga.chain4", &s->vram, offset, size);
201 memory_region_add_subregion_overlap(s->legacy_address_space, base,
202 region, 2);
203 s->chain4_alias = region;
204 }
205 if (old_region) {
206 memory_region_del_subregion(s->legacy_address_space, old_region);
207 memory_region_destroy(old_region);
208 g_free(old_region);
209 s->plane_updated = 0xf;
210 }
211}
212
cedd91d2 213static void vga_dumb_update_retrace_info(VGACommonState *s)
cb5a7aa8 214{
215 (void) s;
216}
217
cedd91d2 218static void vga_precise_update_retrace_info(VGACommonState *s)
cb5a7aa8 219{
220 int htotal_chars;
221 int hretr_start_char;
222 int hretr_skew_chars;
223 int hretr_end_char;
224
225 int vtotal_lines;
226 int vretr_start_line;
227 int vretr_end_line;
228
7f5b7d3e
BS		 229 int dots;
230#if 0
231 int div2, sldiv2;
232#endif
cb5a7aa8 233 int clocking_mode;
234 int clock_sel;
b0f74c87 235 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
cb5a7aa8 236 int64_t chars_per_sec;
237 struct vga_precise_retrace *r = &s->retrace_info.precise;
238
5e55efc9
BS		 239 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
240 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
241 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
242 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
cb5a7aa8 243
5e55efc9
BS		 244 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
245 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
246 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
247 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
248 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
249 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
250 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
cb5a7aa8 251
5e55efc9 252 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
cb5a7aa8 253 clock_sel = (s->msr >> 2) & 3;
f87fc09b 254 dots = (s->msr & 1) ? 8 : 9;
cb5a7aa8 255
b0f74c87 256 chars_per_sec = clk_hz[clock_sel] / dots;
cb5a7aa8 257
258 htotal_chars <<= clocking_mode;
259
260 r->total_chars = vtotal_lines * htotal_chars;
cb5a7aa8 261 if (r->freq) {
6ee093c9 262 r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
cb5a7aa8 263 } else {
6ee093c9 264 r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
cb5a7aa8 265 }
266
267 r->vstart = vretr_start_line;
268 r->vend = r->vstart + vretr_end_line + 1;
269
270 r->hstart = hretr_start_char + hretr_skew_chars;
271 r->hend = r->hstart + hretr_end_char + 1;
272 r->htotal = htotal_chars;
273
f87fc09b 274#if 0
5e55efc9
BS		 275 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
276 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
cb5a7aa8 277 printf (
f87fc09b 278 "hz=%f\n"
cb5a7aa8 279 "htotal = %d\n"
280 "hretr_start = %d\n"
281 "hretr_skew = %d\n"
282 "hretr_end = %d\n"
283 "vtotal = %d\n"
284 "vretr_start = %d\n"
285 "vretr_end = %d\n"
286 "div2 = %d sldiv2 = %d\n"
287 "clocking_mode = %d\n"
288 "clock_sel = %d %d\n"
289 "dots = %d\n"
0bfcd599 290 "ticks/char = %" PRId64 "\n"
cb5a7aa8 291 "\n",
6ee093c9 292 (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
cb5a7aa8 293 htotal_chars,
294 hretr_start_char,
295 hretr_skew_chars,
296 hretr_end_char,
297 vtotal_lines,
298 vretr_start_line,
299 vretr_end_line,
300 div2, sldiv2,
301 clocking_mode,
302 clock_sel,
b0f74c87 303 clk_hz[clock_sel],
cb5a7aa8 304 dots,
305 r->ticks_per_char
306 );
307#endif
308}
309
cedd91d2 310static uint8_t vga_precise_retrace(VGACommonState *s)
cb5a7aa8 311{
312 struct vga_precise_retrace *r = &s->retrace_info.precise;
313 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
314
315 if (r->total_chars) {
316 int cur_line, cur_line_char, cur_char;
317 int64_t cur_tick;
318
74475455 319 cur_tick = qemu_get_clock_ns(vm_clock);
cb5a7aa8 320
321 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
322 cur_line = cur_char / r->htotal;
323
324 if (cur_line >= r->vstart && cur_line <= r->vend) {
325 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
f87fc09b 326 } else {
327 cur_line_char = cur_char % r->htotal;
328 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
329 val |= ST01_DISP_ENABLE;
330 }
cb5a7aa8 331 }
332
333 return val;
334 } else {
335 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
336 }
337}
338
cedd91d2 339static uint8_t vga_dumb_retrace(VGACommonState *s)
cb5a7aa8 340{
341 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
342}
343
25a18cbd
JQ		 344int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
345{
5e55efc9 346 if (s->msr & VGA_MIS_COLOR) {
25a18cbd
JQ		 347 /* Color */
348 return (addr >= 0x3b0 && addr <= 0x3bf);
349 } else {
350 /* Monochrome */
351 return (addr >= 0x3d0 && addr <= 0x3df);
352 }
353}
354
43bf782b 355uint32_t vga_ioport_read(void *opaque, uint32_t addr)
e89f66ec 356{
43bf782b 357 VGACommonState *s = opaque;
e89f66ec
FB		 358 int val, index;
359
25a18cbd 360 if (vga_ioport_invalid(s, addr)) {
e89f66ec
FB		 361 val = 0xff;
362 } else {
363 switch(addr) {
5e55efc9 364 case VGA_ATT_W:
e89f66ec
FB		 365 if (s->ar_flip_flop == 0) {
366 val = s->ar_index;
367 } else {
368 val = 0;
369 }
370 break;
5e55efc9 371 case VGA_ATT_R:
e89f66ec 372 index = s->ar_index & 0x1f;
5e55efc9 373 if (index < VGA_ATT_C) {
e89f66ec 374 val = s->ar[index];
5e55efc9 375 } else {
e89f66ec 376 val = 0;
5e55efc9 377 }
e89f66ec 378 break;
5e55efc9 379 case VGA_MIS_W:
e89f66ec
FB		 380 val = s->st00;
381 break;
5e55efc9 382 case VGA_SEQ_I:
e89f66ec
FB		 383 val = s->sr_index;
384 break;
5e55efc9 385 case VGA_SEQ_D:
e89f66ec 386 val = s->sr[s->sr_index];
a41bc9af
FB		 387#ifdef DEBUG_VGA_REG
388 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
389#endif
e89f66ec 390 break;
5e55efc9 391 case VGA_PEL_IR:
e89f66ec
FB		 392 val = s->dac_state;
393 break;
5e55efc9 394 case VGA_PEL_IW:
e9b43ea3
JQ		 395 val = s->dac_write_index;
396 break;
5e55efc9 397 case VGA_PEL_D:
e89f66ec
FB		 398 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
399 if (++s->dac_sub_index == 3) {
400 s->dac_sub_index = 0;
401 s->dac_read_index++;
402 }
403 break;
5e55efc9 404 case VGA_FTC_R:
e89f66ec
FB		 405 val = s->fcr;
406 break;
5e55efc9 407 case VGA_MIS_R:
e89f66ec
FB		 408 val = s->msr;
409 break;
5e55efc9 410 case VGA_GFX_I:
e89f66ec
FB		 411 val = s->gr_index;
412 break;
5e55efc9 413 case VGA_GFX_D:
e89f66ec 414 val = s->gr[s->gr_index];
a41bc9af
FB		 415#ifdef DEBUG_VGA_REG
416 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
417#endif
e89f66ec 418 break;
5e55efc9
BS		 419 case VGA_CRT_IM:
420 case VGA_CRT_IC:
e89f66ec
FB		 421 val = s->cr_index;
422 break;
5e55efc9
BS		 423 case VGA_CRT_DM:
424 case VGA_CRT_DC:
e89f66ec 425 val = s->cr[s->cr_index];
a41bc9af
FB		 426#ifdef DEBUG_VGA_REG
427 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
a41bc9af 428#endif
e89f66ec 429 break;
5e55efc9
BS		 430 case VGA_IS1_RM:
431 case VGA_IS1_RC:
e89f66ec 432 /* just toggle to fool polling */
cb5a7aa8 433 val = s->st01 = s->retrace(s);
e89f66ec
FB		 434 s->ar_flip_flop = 0;
435 break;
436 default:
437 val = 0x00;
438 break;
439 }
440 }
4fa0f5d2 441#if defined(DEBUG_VGA)
e89f66ec
FB		 442 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
443#endif
444 return val;
445}
446
43bf782b 447void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
e89f66ec 448{
43bf782b 449 VGACommonState *s = opaque;
5467a722 450 int index;
e89f66ec
FB		 451
452 /* check port range access depending on color/monochrome mode */
25a18cbd 453 if (vga_ioport_invalid(s, addr)) {
e89f66ec 454 return;
25a18cbd 455 }
e89f66ec
FB		 456#ifdef DEBUG_VGA
457 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
458#endif
459
460 switch(addr) {
5e55efc9 461 case VGA_ATT_W:
e89f66ec
FB		 462 if (s->ar_flip_flop == 0) {
463 val &= 0x3f;
464 s->ar_index = val;
465 } else {
466 index = s->ar_index & 0x1f;
467 switch(index) {
5e55efc9 468 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
e89f66ec
FB		 469 s->ar[index] = val & 0x3f;
470 break;
5e55efc9 471 case VGA_ATC_MODE:
e89f66ec
FB		 472 s->ar[index] = val & ~0x10;
473 break;
5e55efc9 474 case VGA_ATC_OVERSCAN:
e89f66ec
FB		 475 s->ar[index] = val;
476 break;
5e55efc9 477 case VGA_ATC_PLANE_ENABLE:
e89f66ec
FB		 478 s->ar[index] = val & ~0xc0;
479 break;
5e55efc9 480 case VGA_ATC_PEL:
e89f66ec
FB		 481 s->ar[index] = val & ~0xf0;
482 break;
5e55efc9 483 case VGA_ATC_COLOR_PAGE:
e89f66ec
FB		 484 s->ar[index] = val & ~0xf0;
485 break;
486 default:
487 break;
488 }
489 }
490 s->ar_flip_flop ^= 1;
491 break;
5e55efc9 492 case VGA_MIS_W:
e89f66ec 493 s->msr = val & ~0x10;
cb5a7aa8 494 s->update_retrace_info(s);
e89f66ec 495 break;
5e55efc9 496 case VGA_SEQ_I:
e89f66ec
FB		 497 s->sr_index = val & 7;
498 break;
5e55efc9 499 case VGA_SEQ_D:
a41bc9af
FB		 500#ifdef DEBUG_VGA_REG
501 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
502#endif
e89f66ec 503 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
5e55efc9
BS		 504 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
505 s->update_retrace_info(s);
506 }
80763888 507 vga_update_memory_access(s);
e89f66ec 508 break;
5e55efc9 509 case VGA_PEL_IR:
e89f66ec
FB		 510 s->dac_read_index = val;
511 s->dac_sub_index = 0;
512 s->dac_state = 3;
513 break;
5e55efc9 514 case VGA_PEL_IW:
e89f66ec
FB		 515 s->dac_write_index = val;
516 s->dac_sub_index = 0;
517 s->dac_state = 0;
518 break;
5e55efc9 519 case VGA_PEL_D:
e89f66ec
FB		 520 s->dac_cache[s->dac_sub_index] = val;
521 if (++s->dac_sub_index == 3) {
522 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
523 s->dac_sub_index = 0;
524 s->dac_write_index++;
525 }
526 break;
5e55efc9 527 case VGA_GFX_I:
e89f66ec
FB		 528 s->gr_index = val & 0x0f;
529 break;
5e55efc9 530 case VGA_GFX_D:
a41bc9af
FB		 531#ifdef DEBUG_VGA_REG
532 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
533#endif
e89f66ec 534 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
80763888 535 vga_update_memory_access(s);
e89f66ec 536 break;
5e55efc9
BS		 537 case VGA_CRT_IM:
538 case VGA_CRT_IC:
e89f66ec
FB		 539 s->cr_index = val;
540 break;
5e55efc9
BS		 541 case VGA_CRT_DM:
542 case VGA_CRT_DC:
a41bc9af
FB		 543#ifdef DEBUG_VGA_REG
544 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
545#endif
e89f66ec 546 /* handle CR0-7 protection */
5e55efc9
BS		 547 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
548 s->cr_index <= VGA_CRTC_OVERFLOW) {
e89f66ec 549 /* can always write bit 4 of CR7 */
5e55efc9
BS		 550 if (s->cr_index == VGA_CRTC_OVERFLOW) {
551 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
552 (val & 0x10);
553 }
e89f66ec
FB		 554 return;
555 }
a46007a0 556 s->cr[s->cr_index] = val;
cb5a7aa8 557
558 switch(s->cr_index) {
5e55efc9
BS		 559 case VGA_CRTC_H_TOTAL:
560 case VGA_CRTC_H_SYNC_START:
561 case VGA_CRTC_H_SYNC_END:
562 case VGA_CRTC_V_TOTAL:
563 case VGA_CRTC_OVERFLOW:
564 case VGA_CRTC_V_SYNC_END:
565 case VGA_CRTC_MODE:
cb5a7aa8 566 s->update_retrace_info(s);
567 break;
568 }
e89f66ec 569 break;
5e55efc9
BS		 570 case VGA_IS1_RM:
571 case VGA_IS1_RC:
e89f66ec
FB		 572 s->fcr = val & 0x10;
573 break;
574 }
575}
576
4fa0f5d2 577#ifdef CONFIG_BOCHS_VBE
09a79b49 578static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
4fa0f5d2 579{
cedd91d2 580 VGACommonState *s = opaque;
4fa0f5d2 581 uint32_t val;
09a79b49
FB		 582 val = s->vbe_index;
583 return val;
584}
4fa0f5d2 585
09a79b49
FB		 586static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
587{
cedd91d2 588 VGACommonState *s = opaque;
09a79b49
FB		 589 uint32_t val;
590
af92284b 591 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
8454df8b
FB		 592 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
593 switch(s->vbe_index) {
594 /* XXX: do not hardcode ? */
595 case VBE_DISPI_INDEX_XRES:
596 val = VBE_DISPI_MAX_XRES;
597 break;
598 case VBE_DISPI_INDEX_YRES:
599 val = VBE_DISPI_MAX_YRES;
600 break;
601 case VBE_DISPI_INDEX_BPP:
602 val = VBE_DISPI_MAX_BPP;
603 break;
604 default:
5fafdf24 605 val = s->vbe_regs[s->vbe_index];
8454df8b
FB		 606 break;
607 }
608 } else {
5fafdf24 609 val = s->vbe_regs[s->vbe_index];
8454df8b 610 }
af92284b
GH		 611 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
612 val = s->vram_size / (64 * 1024);
8454df8b 613 } else {
09a79b49 614 val = 0;
8454df8b 615 }
4fa0f5d2 616#ifdef DEBUG_BOCHS_VBE
09a79b49 617 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
4fa0f5d2 618#endif
4fa0f5d2
FB		 619 return val;
620}
621
09a79b49
FB		 622static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
623{
cedd91d2 624 VGACommonState *s = opaque;
09a79b49
FB		 625 s->vbe_index = val;
626}
627
628static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
4fa0f5d2 629{
cedd91d2 630 VGACommonState *s = opaque;
4fa0f5d2 631
09a79b49 632 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
4fa0f5d2
FB		 633#ifdef DEBUG_BOCHS_VBE
634 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
635#endif
636 switch(s->vbe_index) {
637 case VBE_DISPI_INDEX_ID:
cae61cef
FB		 638 if (val == VBE_DISPI_ID0 ||
639 val == VBE_DISPI_ID1 ||
37dd208d
FB		 640 val == VBE_DISPI_ID2 ||
641 val == VBE_DISPI_ID3 ||
642 val == VBE_DISPI_ID4) {
cae61cef
FB		 643 s->vbe_regs[s->vbe_index] = val;
644 }
4fa0f5d2
FB		 645 break;
646 case VBE_DISPI_INDEX_XRES:
cae61cef
FB		 647 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
648 s->vbe_regs[s->vbe_index] = val;
649 }
4fa0f5d2
FB		 650 break;
651 case VBE_DISPI_INDEX_YRES:
cae61cef
FB		 652 if (val <= VBE_DISPI_MAX_YRES) {
653 s->vbe_regs[s->vbe_index] = val;
654 }
4fa0f5d2
FB		 655 break;
656 case VBE_DISPI_INDEX_BPP:
657 if (val == 0)
658 val = 8;
5fafdf24 659 if (val == 4 || val == 8 || val == 15 ||
cae61cef
FB		 660 val == 16 || val == 24 || val == 32) {
661 s->vbe_regs[s->vbe_index] = val;
662 }
4fa0f5d2
FB		 663 break;
664 case VBE_DISPI_INDEX_BANK:
42fc925e
FB		 665 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
666 val &= (s->vbe_bank_mask >> 2);
667 } else {
668 val &= s->vbe_bank_mask;
669 }
cae61cef 670 s->vbe_regs[s->vbe_index] = val;
26aa7d72 671 s->bank_offset = (val << 16);
80763888 672 vga_update_memory_access(s);
4fa0f5d2
FB		 673 break;
674 case VBE_DISPI_INDEX_ENABLE:
8454df8b
FB		 675 if ((val & VBE_DISPI_ENABLED) &&
676 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
4fa0f5d2
FB		 677 int h, shift_control;
678
5fafdf24 679 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
4fa0f5d2 680 s->vbe_regs[VBE_DISPI_INDEX_XRES];
5fafdf24 681 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
4fa0f5d2
FB		 682 s->vbe_regs[VBE_DISPI_INDEX_YRES];
683 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
684 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
3b46e624 685
4fa0f5d2
FB		 686 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
687 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
688 else
5fafdf24 689 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
4fa0f5d2
FB		 690 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
691 s->vbe_start_addr = 0;
8454df8b 692
4fa0f5d2
FB		 693 /* clear the screen (should be done in BIOS) */
694 if (!(val & VBE_DISPI_NOCLEARMEM)) {
5fafdf24 695 memset(s->vram_ptr, 0,
4fa0f5d2
FB		 696 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
697 }
3b46e624 698
cae61cef
FB		 699 /* we initialize the VGA graphic mode (should be done
700 in BIOS) */
5e55efc9
BS		 701 /* graphic mode + memory map 1 */
702 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
703 VGA_GR06_GRAPHICS_MODE;
704 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
705 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
4fa0f5d2 706 /* width */
5e55efc9
BS		 707 s->cr[VGA_CRTC_H_DISP] =
708 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
8454df8b 709 /* height (only meaningful if < 1024) */
4fa0f5d2 710 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
5e55efc9
BS		 711 s->cr[VGA_CRTC_V_DISP_END] = h;
712 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
4fa0f5d2
FB		 713 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
714 /* line compare to 1023 */
5e55efc9
BS		 715 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
716 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
717 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
3b46e624 718
4fa0f5d2
FB		 719 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
720 shift_control = 0;
5e55efc9 721 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
4fa0f5d2
FB		 722 } else {
723 shift_control = 2;
5e55efc9
BS		 724 /* set chain 4 mode */
725 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
726 /* activate all planes */
727 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
4fa0f5d2 728 }
5e55efc9
BS		 729 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
730 (shift_control << 5);
731 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
cae61cef
FB		 732 } else {
733 /* XXX: the bios should do that */
26aa7d72 734 s->bank_offset = 0;
cae61cef 735 }
37dd208d 736 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
141253b2 737 s->vbe_regs[s->vbe_index] = val;
80763888 738 vga_update_memory_access(s);
cae61cef
FB		 739 break;
740 case VBE_DISPI_INDEX_VIRT_WIDTH:
741 {
742 int w, h, line_offset;
743
744 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
745 return;
746 w = val;
747 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
748 line_offset = w >> 1;
749 else
750 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
751 h = s->vram_size / line_offset;
752 /* XXX: support weird bochs semantics ? */
753 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
754 return;
755 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
756 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
757 s->vbe_line_offset = line_offset;
758 }
759 break;
760 case VBE_DISPI_INDEX_X_OFFSET:
761 case VBE_DISPI_INDEX_Y_OFFSET:
762 {
763 int x;
764 s->vbe_regs[s->vbe_index] = val;
765 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
766 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
767 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
768 s->vbe_start_addr += x >> 1;
769 else
770 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
771 s->vbe_start_addr >>= 2;
4fa0f5d2
FB		 772 }
773 break;
774 default:
775 break;
776 }
4fa0f5d2
FB		 777 }
778}
779#endif
780
e89f66ec 781/* called for accesses between 0xa0000 and 0xc0000 */
b2a5e761 782uint32_t vga_mem_readb(VGACommonState *s, target_phys_addr_t addr)
e89f66ec 783{
e89f66ec
FB		 784 int memory_map_mode, plane;
785 uint32_t ret;
3b46e624 786
e89f66ec 787 /* convert to VGA memory offset */
5e55efc9 788 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
26aa7d72 789 addr &= 0x1ffff;
e89f66ec
FB		 790 switch(memory_map_mode) {
791 case 0:
e89f66ec
FB		 792 break;
793 case 1:
26aa7d72 794 if (addr >= 0x10000)
e89f66ec 795 return 0xff;
cae61cef 796 addr += s->bank_offset;
e89f66ec
FB		 797 break;
798 case 2:
26aa7d72 799 addr -= 0x10000;
e89f66ec
FB		 800 if (addr >= 0x8000)
801 return 0xff;
802 break;
803 default:
804 case 3:
26aa7d72 805 addr -= 0x18000;
c92b2e84
FB		 806 if (addr >= 0x8000)
807 return 0xff;
e89f66ec
FB		 808 break;
809 }
3b46e624 810
5e55efc9 811 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
e89f66ec
FB		 812 /* chain 4 mode : simplest access */
813 ret = s->vram_ptr[addr];
5e55efc9 814 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
e89f66ec 815 /* odd/even mode (aka text mode mapping) */
5e55efc9 816 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
e89f66ec
FB		 817 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
818 } else {
819 /* standard VGA latched access */
820 s->latch = ((uint32_t *)s->vram_ptr)[addr];
821
5e55efc9 822 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
e89f66ec 823 /* read mode 0 */
5e55efc9 824 plane = s->gr[VGA_GFX_PLANE_READ];
b8ed223b 825 ret = GET_PLANE(s->latch, plane);
e89f66ec
FB		 826 } else {
827 /* read mode 1 */
5e55efc9
BS		 828 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
829 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
e89f66ec
FB		 830 ret |= ret >> 16;
831 ret |= ret >> 8;
832 ret = (~ret) & 0xff;
833 }
834 }
835 return ret;
836}
837
e89f66ec 838/* called for accesses between 0xa0000 and 0xc0000 */
b2a5e761 839void vga_mem_writeb(VGACommonState *s, target_phys_addr_t addr, uint32_t val)
e89f66ec 840{
546fa6ab 841 int memory_map_mode, plane, write_mode, b, func_select, mask;
e89f66ec
FB		 842 uint32_t write_mask, bit_mask, set_mask;
843
17b0018b 844#ifdef DEBUG_VGA_MEM
0bf9e31a 845 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
e89f66ec
FB		 846#endif
847 /* convert to VGA memory offset */
5e55efc9 848 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
26aa7d72 849 addr &= 0x1ffff;
e89f66ec
FB		 850 switch(memory_map_mode) {
851 case 0:
e89f66ec
FB		 852 break;
853 case 1:
26aa7d72 854 if (addr >= 0x10000)
e89f66ec 855 return;
cae61cef 856 addr += s->bank_offset;
e89f66ec
FB		 857 break;
858 case 2:
26aa7d72 859 addr -= 0x10000;
e89f66ec
FB		 860 if (addr >= 0x8000)
861 return;
862 break;
863 default:
864 case 3:
26aa7d72 865 addr -= 0x18000;
c92b2e84
FB		 866 if (addr >= 0x8000)
867 return;
e89f66ec
FB		 868 break;
869 }
3b46e624 870
5e55efc9 871 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
e89f66ec
FB		 872 /* chain 4 mode : simplest access */
873 plane = addr & 3;
546fa6ab 874 mask = (1 << plane);
5e55efc9 875 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
e89f66ec 876 s->vram_ptr[addr] = val;
17b0018b 877#ifdef DEBUG_VGA_MEM
0bf9e31a 878 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
e89f66ec 879#endif
546fa6ab 880 s->plane_updated |= mask; /* only used to detect font change */
fd4aa979 881 memory_region_set_dirty(&s->vram, addr, 1);
e89f66ec 882 }
5e55efc9 883 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
e89f66ec 884 /* odd/even mode (aka text mode mapping) */
5e55efc9 885 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
546fa6ab 886 mask = (1 << plane);
5e55efc9 887 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
e89f66ec
FB		 888 addr = ((addr & ~1) << 1) | plane;
889 s->vram_ptr[addr] = val;
17b0018b 890#ifdef DEBUG_VGA_MEM
0bf9e31a 891 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
e89f66ec 892#endif
546fa6ab 893 s->plane_updated |= mask; /* only used to detect font change */
fd4aa979 894 memory_region_set_dirty(&s->vram, addr, 1);
e89f66ec
FB		 895 }
896 } else {
897 /* standard VGA latched access */
5e55efc9 898 write_mode = s->gr[VGA_GFX_MODE] & 3;
e89f66ec
FB		 899 switch(write_mode) {
900 default:
901 case 0:
902 /* rotate */
5e55efc9 903 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
e89f66ec
FB		 904 val = ((val >> b) | (val << (8 - b))) & 0xff;
905 val |= val << 8;
906 val |= val << 16;
907
908 /* apply set/reset mask */
5e55efc9
BS		 909 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
910 val = (val & ~set_mask) |
911 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
912 bit_mask = s->gr[VGA_GFX_BIT_MASK];
e89f66ec
FB		 913 break;
914 case 1:
915 val = s->latch;
916 goto do_write;
917 case 2:
918 val = mask16[val & 0x0f];
5e55efc9 919 bit_mask = s->gr[VGA_GFX_BIT_MASK];
e89f66ec
FB		 920 break;
921 case 3:
922 /* rotate */
5e55efc9 923 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
a41bc9af 924 val = (val >> b) | (val << (8 - b));
e89f66ec 925
5e55efc9
BS		 926 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
927 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
e89f66ec
FB		 928 break;
929 }
930
931 /* apply logical operation */
5e55efc9 932 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
e89f66ec
FB		 933 switch(func_select) {
934 case 0:
935 default:
936 /* nothing to do */
937 break;
938 case 1:
939 /* and */
940 val &= s->latch;
941 break;
942 case 2:
943 /* or */
944 val |= s->latch;
945 break;
946 case 3:
947 /* xor */
948 val ^= s->latch;
949 break;
950 }
951
952 /* apply bit mask */
953 bit_mask |= bit_mask << 8;
954 bit_mask |= bit_mask << 16;
955 val = (val & bit_mask) | (s->latch & ~bit_mask);
956
957 do_write:
958 /* mask data according to sr[2] */
5e55efc9 959 mask = s->sr[VGA_SEQ_PLANE_WRITE];
546fa6ab
FB		 960 s->plane_updated |= mask; /* only used to detect font change */
961 write_mask = mask16[mask];
5fafdf24
TS		 962 ((uint32_t *)s->vram_ptr)[addr] =
963 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
e89f66ec 964 (val & write_mask);
17b0018b 965#ifdef DEBUG_VGA_MEM
0bf9e31a
BS		 966 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
967 addr * 4, write_mask, val);
e89f66ec 968#endif
fd4aa979 969 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
e89f66ec
FB		 970 }
971}
972
e89f66ec
FB		 973typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
974 const uint8_t *font_ptr, int h,
975 uint32_t fgcol, uint32_t bgcol);
976typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
5fafdf24 977 const uint8_t *font_ptr, int h,
e89f66ec 978 uint32_t fgcol, uint32_t bgcol, int dup9);
cedd91d2 979typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
e89f66ec
FB		 980 const uint8_t *s, int width);
981
e89f66ec
FB		 982#define DEPTH 8
983#include "vga_template.h"
984
985#define DEPTH 15
986#include "vga_template.h"
987
a2502b58
BS		 988#define BGR_FORMAT
989#define DEPTH 15
990#include "vga_template.h"
991
992#define DEPTH 16
993#include "vga_template.h"
994
995#define BGR_FORMAT
e89f66ec
FB		 996#define DEPTH 16
997#include "vga_template.h"
998
999#define DEPTH 32
1000#include "vga_template.h"
1001
d3079cd2
FB		 1002#define BGR_FORMAT
1003#define DEPTH 32
1004#include "vga_template.h"
1005
17b0018b
FB		 1006static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
1007{
1008 unsigned int col;
1009 col = rgb_to_pixel8(r, g, b);
1010 col |= col << 8;
1011 col |= col << 16;
1012 return col;
1013}
1014
1015static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
1016{
1017 unsigned int col;
1018 col = rgb_to_pixel15(r, g, b);
1019 col |= col << 16;
1020 return col;
1021}
1022
b29169d2
BS		 1023static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1024 unsigned int b)
1025{
1026 unsigned int col;
1027 col = rgb_to_pixel15bgr(r, g, b);
1028 col |= col << 16;
1029 return col;
1030}
1031
17b0018b
FB		 1032static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1033{
1034 unsigned int col;
1035 col = rgb_to_pixel16(r, g, b);
1036 col |= col << 16;
1037 return col;
1038}
1039
b29169d2
BS		 1040static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1041 unsigned int b)
1042{
1043 unsigned int col;
1044 col = rgb_to_pixel16bgr(r, g, b);
1045 col |= col << 16;
1046 return col;
1047}
1048
17b0018b
FB		 1049static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1050{
1051 unsigned int col;
1052 col = rgb_to_pixel32(r, g, b);
1053 return col;
1054}
1055
d3079cd2
FB		 1056static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1057{
1058 unsigned int col;
1059 col = rgb_to_pixel32bgr(r, g, b);
1060 return col;
1061}
1062
e89f66ec 1063/* return true if the palette was modified */
cedd91d2 1064static int update_palette16(VGACommonState *s)
e89f66ec 1065{
17b0018b 1066 int full_update, i;
e89f66ec 1067 uint32_t v, col, *palette;
e89f66ec
FB		 1068
1069 full_update = 0;
1070 palette = s->last_palette;
1071 for(i = 0; i < 16; i++) {
1072 v = s->ar[i];
5e55efc9
BS		 1073 if (s->ar[VGA_ATC_MODE] & 0x80) {
1074 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1075 } else {
1076 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1077 }
e89f66ec 1078 v = v * 3;
5fafdf24
TS		 1079 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1080 c6_to_8(s->palette[v + 1]),
17b0018b
FB		 1081 c6_to_8(s->palette[v + 2]));
1082 if (col != palette[i]) {
1083 full_update = 1;
1084 palette[i] = col;
e89f66ec 1085 }
17b0018b
FB		 1086 }
1087 return full_update;
1088}
1089
1090/* return true if the palette was modified */
cedd91d2 1091static int update_palette256(VGACommonState *s)
17b0018b
FB		 1092{
1093 int full_update, i;
1094 uint32_t v, col, *palette;
1095
1096 full_update = 0;
1097 palette = s->last_palette;
1098 v = 0;
1099 for(i = 0; i < 256; i++) {
37dd208d 1100 if (s->dac_8bit) {
5fafdf24
TS		 1101 col = s->rgb_to_pixel(s->palette[v],
1102 s->palette[v + 1],
37dd208d
FB		 1103 s->palette[v + 2]);
1104 } else {
5fafdf24
TS		 1105 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1106 c6_to_8(s->palette[v + 1]),
37dd208d
FB		 1107 c6_to_8(s->palette[v + 2]));
1108 }
e89f66ec
FB		 1109 if (col != palette[i]) {
1110 full_update = 1;
1111 palette[i] = col;
1112 }
17b0018b 1113 v += 3;
e89f66ec
FB		 1114 }
1115 return full_update;
1116}
1117
cedd91d2 1118static void vga_get_offsets(VGACommonState *s,
5fafdf24 1119 uint32_t *pline_offset,
83acc96b
FB		 1120 uint32_t *pstart_addr,
1121 uint32_t *pline_compare)
e89f66ec 1122{
83acc96b 1123 uint32_t start_addr, line_offset, line_compare;
4fa0f5d2
FB		 1124#ifdef CONFIG_BOCHS_VBE
1125 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1126 line_offset = s->vbe_line_offset;
1127 start_addr = s->vbe_start_addr;
83acc96b 1128 line_compare = 65535;
4fa0f5d2
FB		 1129 } else
1130#endif
3b46e624 1131 {
4fa0f5d2 1132 /* compute line_offset in bytes */
5e55efc9 1133 line_offset = s->cr[VGA_CRTC_OFFSET];
4fa0f5d2 1134 line_offset <<= 3;
08e48902 1135
4fa0f5d2 1136 /* starting address */
5e55efc9
BS		 1137 start_addr = s->cr[VGA_CRTC_START_LO] |
1138 (s->cr[VGA_CRTC_START_HI] << 8);
83acc96b
FB		 1139
1140 /* line compare */
5e55efc9
BS		 1141 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1142 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1143 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
4fa0f5d2 1144 }
798b0c25
FB		 1145 *pline_offset = line_offset;
1146 *pstart_addr = start_addr;
83acc96b 1147 *pline_compare = line_compare;
798b0c25
FB		 1148}
1149
1150/* update start_addr and line_offset. Return TRUE if modified */
cedd91d2 1151static int update_basic_params(VGACommonState *s)
798b0c25
FB		 1152{
1153 int full_update;
1154 uint32_t start_addr, line_offset, line_compare;
3b46e624 1155
798b0c25
FB		 1156 full_update = 0;
1157
83acc96b 1158 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
e89f66ec
FB		 1159
1160 if (line_offset != s->line_offset ||
1161 start_addr != s->start_addr ||
1162 line_compare != s->line_compare) {
1163 s->line_offset = line_offset;
1164 s->start_addr = start_addr;
1165 s->line_compare = line_compare;
1166 full_update = 1;
1167 }
1168 return full_update;
1169}
1170
b29169d2 1171#define NB_DEPTHS 7
d3079cd2
FB		 1172
1173static inline int get_depth_index(DisplayState *s)
e89f66ec 1174{
0e1f5a0c 1175 switch(ds_get_bits_per_pixel(s)) {
e89f66ec
FB		 1176 default:
1177 case 8:
1178 return 0;
1179 case 15:
8927bcfd 1180 return 1;
e89f66ec 1181 case 16:
8927bcfd 1182 return 2;
e89f66ec 1183 case 32:
7b5d76da
AL		 1184 if (is_surface_bgr(s->surface))
1185 return 4;
1186 else
1187 return 3;
e89f66ec
FB		 1188 }
1189}
1190
68f04a3c 1191static vga_draw_glyph8_func * const vga_draw_glyph8_table[NB_DEPTHS] = {
e89f66ec
FB		 1192 vga_draw_glyph8_8,
1193 vga_draw_glyph8_16,
1194 vga_draw_glyph8_16,
1195 vga_draw_glyph8_32,
d3079cd2 1196 vga_draw_glyph8_32,
b29169d2
BS		 1197 vga_draw_glyph8_16,
1198 vga_draw_glyph8_16,
e89f66ec
FB		 1199};
1200
68f04a3c 1201static vga_draw_glyph8_func * const vga_draw_glyph16_table[NB_DEPTHS] = {
17b0018b
FB		 1202 vga_draw_glyph16_8,
1203 vga_draw_glyph16_16,
1204 vga_draw_glyph16_16,
1205 vga_draw_glyph16_32,
d3079cd2 1206 vga_draw_glyph16_32,
b29169d2
BS		 1207 vga_draw_glyph16_16,
1208 vga_draw_glyph16_16,
17b0018b
FB		 1209};
1210
68f04a3c 1211static vga_draw_glyph9_func * const vga_draw_glyph9_table[NB_DEPTHS] = {
e89f66ec
FB		 1212 vga_draw_glyph9_8,
1213 vga_draw_glyph9_16,
1214 vga_draw_glyph9_16,
1215 vga_draw_glyph9_32,
d3079cd2 1216 vga_draw_glyph9_32,
b29169d2
BS		 1217 vga_draw_glyph9_16,
1218 vga_draw_glyph9_16,
e89f66ec 1219};
3b46e624 1220
e89f66ec
FB		 1221static const uint8_t cursor_glyph[32 * 4] = {
1222 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1223 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1224 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1225 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1226 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1227 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1228 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1229 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1230 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1231 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1232 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1233 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1234 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1235 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1236 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1237 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
3b46e624 1238};
e89f66ec 1239
cedd91d2 1240static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
4c5e8c5c
BS		 1241 int *pcwidth, int *pcheight)
1242{
1243 int width, cwidth, height, cheight;
1244
1245 /* total width & height */
5e55efc9 1246 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
4c5e8c5c 1247 cwidth = 8;
5e55efc9 1248 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
4c5e8c5c 1249 cwidth = 9;
5e55efc9
BS		 1250 }
1251 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
4c5e8c5c 1252 cwidth = 16; /* NOTE: no 18 pixel wide */
5e55efc9
BS		 1253 }
1254 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1255 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
4c5e8c5c
BS		 1256 /* ugly hack for CGA 160x100x16 - explain me the logic */
1257 height = 100;
1258 } else {
5e55efc9
BS		 1259 height = s->cr[VGA_CRTC_V_DISP_END] |
1260 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1261 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
4c5e8c5c
BS		 1262 height = (height + 1) / cheight;
1263 }
1264
1265 *pwidth = width;
1266 *pheight = height;
1267 *pcwidth = cwidth;
1268 *pcheight = cheight;
1269}
1270
7d957bd8
AL		 1271typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1272
68f04a3c 1273static rgb_to_pixel_dup_func * const rgb_to_pixel_dup_table[NB_DEPTHS] = {
bdb19571
AL		 1274 rgb_to_pixel8_dup,
1275 rgb_to_pixel15_dup,
1276 rgb_to_pixel16_dup,
1277 rgb_to_pixel32_dup,
1278 rgb_to_pixel32bgr_dup,
1279 rgb_to_pixel15bgr_dup,
1280 rgb_to_pixel16bgr_dup,
1281};
7d957bd8 1282
5fafdf24
TS		 1283/*
1284 * Text mode update
e89f66ec
FB		 1285 * Missing:
1286 * - double scan
5fafdf24 1287 * - double width
e89f66ec
FB		 1288 * - underline
1289 * - flashing
1290 */
cedd91d2 1291static void vga_draw_text(VGACommonState *s, int full_update)
e89f66ec
FB		 1292{
1293 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
cae334cd 1294 int cx_min, cx_max, linesize, x_incr, line, line1;
e89f66ec 1295 uint32_t offset, fgcol, bgcol, v, cursor_offset;
d1984194 1296 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
e89f66ec
FB		 1297 const uint8_t *font_ptr, *font_base[2];
1298 int dup9, line_offset, depth_index;
1299 uint32_t *palette;
1300 uint32_t *ch_attr_ptr;
1301 vga_draw_glyph8_func *vga_draw_glyph8;
1302 vga_draw_glyph9_func *vga_draw_glyph9;
1303
e89f66ec 1304 /* compute font data address (in plane 2) */
5e55efc9 1305 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1078f663 1306 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1307 if (offset != s->font_offsets[0]) {
1308 s->font_offsets[0] = offset;
1309 full_update = 1;
1310 }
1311 font_base[0] = s->vram_ptr + offset;
1312
1078f663 1313 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
e89f66ec
FB		 1314 font_base[1] = s->vram_ptr + offset;
1315 if (offset != s->font_offsets[1]) {
1316 s->font_offsets[1] = offset;
1317 full_update = 1;
1318 }
80763888 1319 if (s->plane_updated & (1 << 2) || s->chain4_alias) {
546fa6ab
FB		 1320 /* if the plane 2 was modified since the last display, it
1321 indicates the font may have been modified */
1322 s->plane_updated = 0;
1323 full_update = 1;
1324 }
799e709b 1325 full_update |= update_basic_params(s);
e89f66ec
FB		 1326
1327 line_offset = s->line_offset;
e89f66ec 1328
4c5e8c5c 1329 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1b296044
SW		 1330 if ((height * width) <= 1) {
1331 /* better than nothing: exit if transient size is too small */
1332 return;
1333 }
3294b949
FB		 1334 if ((height * width) > CH_ATTR_SIZE) {
1335 /* better than nothing: exit if transient size is too big */
1336 return;
1337 }
1338
799e709b
AL		 1339 if (width != s->last_width || height != s->last_height ||
1340 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1341 s->last_scr_width = width * cw;
1342 s->last_scr_height = height * cheight;
1343 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1344 s->last_depth = 0;
1345 s->last_width = width;
1346 s->last_height = height;
1347 s->last_ch = cheight;
1348 s->last_cw = cw;
1349 full_update = 1;
1350 }
7d957bd8
AL		 1351 s->rgb_to_pixel =
1352 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1353 full_update |= update_palette16(s);
1354 palette = s->last_palette;
1355 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1356
5e55efc9
BS		 1357 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1358 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
e89f66ec 1359 if (cursor_offset != s->cursor_offset ||
5e55efc9
BS		 1360 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1361 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
e89f66ec
FB		 1362 /* if the cursor position changed, we update the old and new
1363 chars */
1364 if (s->cursor_offset < CH_ATTR_SIZE)
1365 s->last_ch_attr[s->cursor_offset] = -1;
1366 if (cursor_offset < CH_ATTR_SIZE)
1367 s->last_ch_attr[cursor_offset] = -1;
1368 s->cursor_offset = cursor_offset;
5e55efc9
BS		 1369 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1370 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
e89f66ec 1371 }
39cf7803 1372 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
3b46e624 1373
d3079cd2 1374 depth_index = get_depth_index(s->ds);
17b0018b
FB		 1375 if (cw == 16)
1376 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1377 else
1378 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
e89f66ec 1379 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
3b46e624 1380
0e1f5a0c
AL		 1381 dest = ds_get_data(s->ds);
1382 linesize = ds_get_linesize(s->ds);
e89f66ec 1383 ch_attr_ptr = s->last_ch_attr;
d1984194 1384 line = 0;
1385 offset = s->start_addr * 4;
e89f66ec
FB		 1386 for(cy = 0; cy < height; cy++) {
1387 d1 = dest;
d1984194 1388 src = s->vram_ptr + offset;
e89f66ec
FB		 1389 cx_min = width;
1390 cx_max = -1;
1391 for(cx = 0; cx < width; cx++) {
1392 ch_attr = *(uint16_t *)src;
1393 if (full_update || ch_attr != *ch_attr_ptr) {
1394 if (cx < cx_min)
1395 cx_min = cx;
1396 if (cx > cx_max)
1397 cx_max = cx;
1398 *ch_attr_ptr = ch_attr;
e2542fe2 1399#ifdef HOST_WORDS_BIGENDIAN
e89f66ec
FB		 1400 ch = ch_attr >> 8;
1401 cattr = ch_attr & 0xff;
1402#else
1403 ch = ch_attr & 0xff;
1404 cattr = ch_attr >> 8;
1405#endif
1406 font_ptr = font_base[(cattr >> 3) & 1];
1407 font_ptr += 32 * 4 * ch;
1408 bgcol = palette[cattr >> 4];
1409 fgcol = palette[cattr & 0x0f];
17b0018b 1410 if (cw != 9) {
5fafdf24 1411 vga_draw_glyph8(d1, linesize,
e89f66ec
FB		 1412 font_ptr, cheight, fgcol, bgcol);
1413 } else {
1414 dup9 = 0;
5e55efc9
BS		 1415 if (ch >= 0xb0 && ch <= 0xdf &&
1416 (s->ar[VGA_ATC_MODE] & 0x04)) {
e89f66ec 1417 dup9 = 1;
5e55efc9 1418 }
5fafdf24 1419 vga_draw_glyph9(d1, linesize,
e89f66ec
FB		 1420 font_ptr, cheight, fgcol, bgcol, dup9);
1421 }
1422 if (src == cursor_ptr &&
5e55efc9 1423 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20)) {
e89f66ec
FB		 1424 int line_start, line_last, h;
1425 /* draw the cursor */
5e55efc9
BS		 1426 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1427 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
e89f66ec
FB		 1428 /* XXX: check that */
1429 if (line_last > cheight - 1)
1430 line_last = cheight - 1;
1431 if (line_last >= line_start && line_start < cheight) {
1432 h = line_last - line_start + 1;
1433 d = d1 + linesize * line_start;
17b0018b 1434 if (cw != 9) {
5fafdf24 1435 vga_draw_glyph8(d, linesize,
e89f66ec
FB		 1436 cursor_glyph, h, fgcol, bgcol);
1437 } else {
5fafdf24 1438 vga_draw_glyph9(d, linesize,
e89f66ec
FB		 1439 cursor_glyph, h, fgcol, bgcol, 1);
1440 }
1441 }
1442 }
1443 }
1444 d1 += x_incr;
1445 src += 4;
1446 ch_attr_ptr++;
1447 }
1448 if (cx_max != -1) {
5fafdf24 1449 dpy_update(s->ds, cx_min * cw, cy * cheight,
e89f66ec
FB		 1450 (cx_max - cx_min + 1) * cw, cheight);
1451 }
1452 dest += linesize * cheight;
cae334cd 1453 line1 = line + cheight;
1454 offset += line_offset;
1455 if (line < s->line_compare && line1 >= s->line_compare) {
d1984194 1456 offset = 0;
1457 }
cae334cd 1458 line = line1;
e89f66ec
FB		 1459 }
1460}
1461
17b0018b
FB		 1462enum {
1463 VGA_DRAW_LINE2,
1464 VGA_DRAW_LINE2D2,
1465 VGA_DRAW_LINE4,
1466 VGA_DRAW_LINE4D2,
1467 VGA_DRAW_LINE8D2,
1468 VGA_DRAW_LINE8,
1469 VGA_DRAW_LINE15,
1470 VGA_DRAW_LINE16,
4fa0f5d2 1471 VGA_DRAW_LINE24,
17b0018b
FB		 1472 VGA_DRAW_LINE32,
1473 VGA_DRAW_LINE_NB,
1474};
1475
68f04a3c 1476static vga_draw_line_func * const vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
e89f66ec
FB		 1477 vga_draw_line2_8,
1478 vga_draw_line2_16,
1479 vga_draw_line2_16,
1480 vga_draw_line2_32,
d3079cd2 1481 vga_draw_line2_32,
b29169d2
BS		 1482 vga_draw_line2_16,
1483 vga_draw_line2_16,
e89f66ec 1484
17b0018b
FB		 1485 vga_draw_line2d2_8,
1486 vga_draw_line2d2_16,
1487 vga_draw_line2d2_16,
1488 vga_draw_line2d2_32,
d3079cd2 1489 vga_draw_line2d2_32,
b29169d2
BS		 1490 vga_draw_line2d2_16,
1491 vga_draw_line2d2_16,
17b0018b 1492
e89f66ec
FB		 1493 vga_draw_line4_8,
1494 vga_draw_line4_16,
1495 vga_draw_line4_16,
1496 vga_draw_line4_32,
d3079cd2 1497 vga_draw_line4_32,
b29169d2
BS		 1498 vga_draw_line4_16,
1499 vga_draw_line4_16,
e89f66ec 1500
17b0018b
FB		 1501 vga_draw_line4d2_8,
1502 vga_draw_line4d2_16,
1503 vga_draw_line4d2_16,
1504 vga_draw_line4d2_32,
d3079cd2 1505 vga_draw_line4d2_32,
b29169d2
BS		 1506 vga_draw_line4d2_16,
1507 vga_draw_line4d2_16,
17b0018b
FB		 1508
1509 vga_draw_line8d2_8,
1510 vga_draw_line8d2_16,
1511 vga_draw_line8d2_16,
1512 vga_draw_line8d2_32,
d3079cd2 1513 vga_draw_line8d2_32,
b29169d2
BS		 1514 vga_draw_line8d2_16,
1515 vga_draw_line8d2_16,
17b0018b 1516
e89f66ec
FB		 1517 vga_draw_line8_8,
1518 vga_draw_line8_16,
1519 vga_draw_line8_16,
1520 vga_draw_line8_32,
d3079cd2 1521 vga_draw_line8_32,
b29169d2
BS		 1522 vga_draw_line8_16,
1523 vga_draw_line8_16,
e89f66ec
FB		 1524
1525 vga_draw_line15_8,
1526 vga_draw_line15_15,
1527 vga_draw_line15_16,
1528 vga_draw_line15_32,
d3079cd2 1529 vga_draw_line15_32bgr,
b29169d2
BS		 1530 vga_draw_line15_15bgr,
1531 vga_draw_line15_16bgr,
e89f66ec
FB		 1532
1533 vga_draw_line16_8,
1534 vga_draw_line16_15,
1535 vga_draw_line16_16,
1536 vga_draw_line16_32,
d3079cd2 1537 vga_draw_line16_32bgr,
b29169d2
BS		 1538 vga_draw_line16_15bgr,
1539 vga_draw_line16_16bgr,
e89f66ec 1540
4fa0f5d2
FB		 1541 vga_draw_line24_8,
1542 vga_draw_line24_15,
1543 vga_draw_line24_16,
1544 vga_draw_line24_32,
d3079cd2 1545 vga_draw_line24_32bgr,
b29169d2
BS		 1546 vga_draw_line24_15bgr,
1547 vga_draw_line24_16bgr,
4fa0f5d2 1548
e89f66ec
FB		 1549 vga_draw_line32_8,
1550 vga_draw_line32_15,
1551 vga_draw_line32_16,
1552 vga_draw_line32_32,
d3079cd2 1553 vga_draw_line32_32bgr,
b29169d2
BS		 1554 vga_draw_line32_15bgr,
1555 vga_draw_line32_16bgr,
d3079cd2
FB		 1556};
1557
cedd91d2 1558static int vga_get_bpp(VGACommonState *s)
798b0c25
FB		 1559{
1560 int ret;
1561#ifdef CONFIG_BOCHS_VBE
1562 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1563 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
5fafdf24 1564 } else
798b0c25
FB		 1565#endif
1566 {
1567 ret = 0;
1568 }
1569 return ret;
1570}
1571
cedd91d2 1572static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
a130a41e
FB		 1573{
1574 int width, height;
3b46e624 1575
8454df8b
FB		 1576#ifdef CONFIG_BOCHS_VBE
1577 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1578 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1579 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
5fafdf24 1580 } else
8454df8b
FB		 1581#endif
1582 {
5e55efc9
BS		 1583 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1584 height = s->cr[VGA_CRTC_V_DISP_END] |
1585 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1586 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
8454df8b
FB		 1587 height = (height + 1);
1588 }
a130a41e
FB		 1589 *pwidth = width;
1590 *pheight = height;
1591}
1592
cedd91d2 1593void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
a8aa669b
FB		 1594{
1595 int y;
1596 if (y1 >= VGA_MAX_HEIGHT)
1597 return;
1598 if (y2 >= VGA_MAX_HEIGHT)
1599 y2 = VGA_MAX_HEIGHT;
1600 for(y = y1; y < y2; y++) {
1601 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1602 }
1603}
1604
cedd91d2 1605static void vga_sync_dirty_bitmap(VGACommonState *s)
2bec46dc 1606{
b1950430 1607 memory_region_sync_dirty_bitmap(&s->vram);
2bec46dc
AL		 1608}
1609
50af3246
JQ		 1610void vga_dirty_log_start(VGACommonState *s)
1611{
b1950430 1612 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
b5cc6e32
AL		 1613}
1614
1615void vga_dirty_log_stop(VGACommonState *s)
1616{
b1950430 1617 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
b5cc6e32
AL		 1618}
1619
799e709b
AL		 1620/*
1621 * graphic modes
1622 */
cedd91d2 1623static void vga_draw_graphic(VGACommonState *s, int full_update)
e89f66ec 1624{
12c7e75a
AK		 1625 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1626 int width, height, shift_control, line_offset, bwidth, bits;
c227f099 1627 ram_addr_t page0, page1, page_min, page_max;
a07cf92a 1628 int disp_width, multi_scan, multi_run;
799e709b
AL		 1629 uint8_t *d;
1630 uint32_t v, addr1, addr;
1631 vga_draw_line_func *vga_draw_line;
1632
1633 full_update |= update_basic_params(s);
1634
1635 if (!full_update)
1636 vga_sync_dirty_bitmap(s);
2bec46dc 1637
a130a41e 1638 s->get_resolution(s, &width, &height);
17b0018b 1639 disp_width = width;
09a79b49 1640
5e55efc9
BS		 1641 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1642 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
799e709b 1643 if (shift_control != 1) {
5e55efc9
BS		 1644 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1645 - 1;
799e709b
AL		 1646 } else {
1647 /* in CGA modes, multi_scan is ignored */
1648 /* XXX: is it correct ? */
1649 multi_scan = double_scan;
1650 }
1651 multi_run = multi_scan;
17b0018b
FB		 1652 if (shift_control != s->shift_control ||
1653 double_scan != s->double_scan) {
799e709b 1654 full_update = 1;
e89f66ec 1655 s->shift_control = shift_control;
17b0018b 1656 s->double_scan = double_scan;
e89f66ec 1657 }
3b46e624 1658
aba35a6c 1659 if (shift_control == 0) {
5e55efc9 1660 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
aba35a6c 1661 disp_width <<= 1;
1662 }
1663 } else if (shift_control == 1) {
5e55efc9 1664 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
aba35a6c 1665 disp_width <<= 1;
1666 }
1667 }
1668
799e709b 1669 depth = s->get_bpp(s);
e3697092
AJ		 1670 if (s->line_offset != s->last_line_offset ||
1671 disp_width != s->last_width ||
1672 height != s->last_height ||
799e709b 1673 s->last_depth != depth) {
e2542fe2 1674#if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
e3697092 1675 if (depth == 16 || depth == 32) {
0da2ea1b 1676#else
1677 if (depth == 32) {
1678#endif
b8c18e4c
AL		 1679 qemu_free_displaysurface(s->ds);
1680 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1681 s->line_offset,
1682 s->vram_ptr + (s->start_addr * 4));
e2542fe2 1683#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
b8c18e4c 1684 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
0da2ea1b 1685#endif
b8c18e4c 1686 dpy_resize(s->ds);
e3697092
AJ		 1687 } else {
1688 qemu_console_resize(s->ds, disp_width, height);
1689 }
1690 s->last_scr_width = disp_width;
1691 s->last_scr_height = height;
1692 s->last_width = disp_width;
1693 s->last_height = height;
1694 s->last_line_offset = s->line_offset;
1695 s->last_depth = depth;
799e709b
AL		 1696 full_update = 1;
1697 } else if (is_buffer_shared(s->ds->surface) &&
e3697092
AJ		 1698 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1699 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1700 dpy_setdata(s->ds);
1701 }
1702
1703 s->rgb_to_pixel =
1704 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1705
799e709b 1706 if (shift_control == 0) {
17b0018b 1707 full_update |= update_palette16(s);
5e55efc9 1708 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
17b0018b 1709 v = VGA_DRAW_LINE4D2;
17b0018b
FB		 1710 } else {
1711 v = VGA_DRAW_LINE4;
1712 }
15342721 1713 bits = 4;
799e709b 1714 } else if (shift_control == 1) {
17b0018b 1715 full_update |= update_palette16(s);
5e55efc9 1716 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
17b0018b 1717 v = VGA_DRAW_LINE2D2;
17b0018b
FB		 1718 } else {
1719 v = VGA_DRAW_LINE2;
1720 }
15342721 1721 bits = 4;
17b0018b 1722 } else {
798b0c25
FB		 1723 switch(s->get_bpp(s)) {
1724 default:
1725 case 0:
4fa0f5d2
FB		 1726 full_update |= update_palette256(s);
1727 v = VGA_DRAW_LINE8D2;
15342721 1728 bits = 4;
798b0c25
FB		 1729 break;
1730 case 8:
1731 full_update |= update_palette256(s);
1732 v = VGA_DRAW_LINE8;
15342721 1733 bits = 8;
798b0c25
FB		 1734 break;
1735 case 15:
1736 v = VGA_DRAW_LINE15;
15342721 1737 bits = 16;
798b0c25
FB		 1738 break;
1739 case 16:
1740 v = VGA_DRAW_LINE16;
15342721 1741 bits = 16;
798b0c25
FB		 1742 break;
1743 case 24:
1744 v = VGA_DRAW_LINE24;
15342721 1745 bits = 24;
798b0c25
FB		 1746 break;
1747 case 32:
1748 v = VGA_DRAW_LINE32;
15342721 1749 bits = 32;
798b0c25 1750 break;
4fa0f5d2 1751 }
17b0018b 1752 }
d3079cd2 1753 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
17b0018b 1754
7d957bd8 1755 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
a8aa669b 1756 s->cursor_invalidate(s);
3b46e624 1757
e89f66ec 1758 line_offset = s->line_offset;
17b0018b 1759#if 0
f6c958c8 1760 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
5e55efc9
BS		 1761 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1762 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
17b0018b 1763#endif
e89f66ec 1764 addr1 = (s->start_addr * 4);
15342721 1765 bwidth = (width * bits + 7) / 8;
39cf7803 1766 y_start = -1;
12c7e75a
AK		 1767 page_min = -1;
1768 page_max = 0;
0e1f5a0c
AL		 1769 d = ds_get_data(s->ds);
1770 linesize = ds_get_linesize(s->ds);
17b0018b 1771 y1 = 0;
e89f66ec
FB		 1772 for(y = 0; y < height; y++) {
1773 addr = addr1;
5e55efc9 1774 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
17b0018b 1775 int shift;
e89f66ec 1776 /* CGA compatibility handling */
5e55efc9 1777 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
17b0018b 1778 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
e89f66ec 1779 }
5e55efc9 1780 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
17b0018b 1781 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
e89f66ec 1782 }
734781c9 1783 update = full_update;
cd7a45c9
BS		 1784 page0 = addr;
1785 page1 = addr + bwidth - 1;
734781c9
JK		 1786 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1787 DIRTY_MEMORY_VGA);
a8aa669b
FB		 1788 /* explicit invalidation for the hardware cursor */
1789 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
e89f66ec 1790 if (update) {
39cf7803
FB		 1791 if (y_start < 0)
1792 y_start = y;
e89f66ec
FB		 1793 if (page0 < page_min)
1794 page_min = page0;
1795 if (page1 > page_max)
1796 page_max = page1;
7d957bd8
AL		 1797 if (!(is_buffer_shared(s->ds->surface))) {
1798 vga_draw_line(s, d, s->vram_ptr + addr, width);
1799 if (s->cursor_draw_line)
1800 s->cursor_draw_line(s, d, y);
1801 }
39cf7803
FB		 1802 } else {
1803 if (y_start >= 0) {
1804 /* flush to display */
5fafdf24 1805 dpy_update(s->ds, 0, y_start,
799e709b 1806 disp_width, y - y_start);
39cf7803
FB		 1807 y_start = -1;
1808 }
e89f66ec 1809 }
a07cf92a 1810 if (!multi_run) {
5e55efc9 1811 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
f6c958c8
FB		 1812 if ((y1 & mask) == mask)
1813 addr1 += line_offset;
1814 y1++;
799e709b 1815 multi_run = multi_scan;
a07cf92a
FB		 1816 } else {
1817 multi_run--;
e89f66ec 1818 }
f6c958c8
FB		 1819 /* line compare acts on the displayed lines */
1820 if (y == s->line_compare)
1821 addr1 = 0;
e89f66ec
FB		 1822 d += linesize;
1823 }
39cf7803
FB		 1824 if (y_start >= 0) {
1825 /* flush to display */
5fafdf24 1826 dpy_update(s->ds, 0, y_start,
799e709b 1827 disp_width, y - y_start);
39cf7803 1828 }
e89f66ec 1829 /* reset modified pages */
12c7e75a 1830 if (page_max >= page_min) {
b1950430
AK		 1831 memory_region_reset_dirty(&s->vram,
1832 page_min,
cd7a45c9 1833 page_max - page_min,
b1950430 1834 DIRTY_MEMORY_VGA);
e89f66ec 1835 }
a8aa669b 1836 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
e89f66ec
FB		 1837}
1838
cedd91d2 1839static void vga_draw_blank(VGACommonState *s, int full_update)
2aebb3eb
FB		 1840{
1841 int i, w, val;
1842 uint8_t *d;
1843
1844 if (!full_update)
1845 return;
1846 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1847 return;
2bec46dc 1848
7d957bd8
AL		 1849 s->rgb_to_pixel =
1850 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
0e1f5a0c 1851 if (ds_get_bits_per_pixel(s->ds) == 8)
2aebb3eb
FB		 1852 val = s->rgb_to_pixel(0, 0, 0);
1853 else
1854 val = 0;
0e1f5a0c
AL		 1855 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1856 d = ds_get_data(s->ds);
2aebb3eb
FB		 1857 for(i = 0; i < s->last_scr_height; i++) {
1858 memset(d, val, w);
0e1f5a0c 1859 d += ds_get_linesize(s->ds);
2aebb3eb 1860 }
5fafdf24 1861 dpy_update(s->ds, 0, 0,
2aebb3eb
FB		 1862 s->last_scr_width, s->last_scr_height);
1863}
1864
799e709b
AL		 1865#define GMODE_TEXT 0
1866#define GMODE_GRAPH 1
1867#define GMODE_BLANK 2
1868
95219897 1869static void vga_update_display(void *opaque)
e89f66ec 1870{
cedd91d2 1871 VGACommonState *s = opaque;
799e709b 1872 int full_update, graphic_mode;
e89f66ec 1873
e9a07334
JK		 1874 qemu_flush_coalesced_mmio_buffer();
1875
0e1f5a0c 1876 if (ds_get_bits_per_pixel(s->ds) == 0) {
0f35920c 1877 /* nothing to do */
59a983b9 1878 } else {
3098b9fd 1879 full_update = 0;
799e709b
AL		 1880 if (!(s->ar_index & 0x20)) {
1881 graphic_mode = GMODE_BLANK;
1882 } else {
5e55efc9 1883 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
799e709b
AL		 1884 }
1885 if (graphic_mode != s->graphic_mode) {
1886 s->graphic_mode = graphic_mode;
1887 full_update = 1;
1888 }
1889 switch(graphic_mode) {
2aebb3eb 1890 case GMODE_TEXT:
e89f66ec 1891 vga_draw_text(s, full_update);
2aebb3eb
FB		 1892 break;
1893 case GMODE_GRAPH:
1894 vga_draw_graphic(s, full_update);
1895 break;
1896 case GMODE_BLANK:
1897 default:
1898 vga_draw_blank(s, full_update);
1899 break;
1900 }
e89f66ec
FB		 1901 }
1902}
1903
a130a41e 1904/* force a full display refresh */
95219897 1905static void vga_invalidate_display(void *opaque)
a130a41e 1906{
cedd91d2 1907 VGACommonState *s = opaque;
3b46e624 1908
3098b9fd
AJ		 1909 s->last_width = -1;
1910 s->last_height = -1;
a130a41e
FB		 1911}
1912
03a3e7ba 1913void vga_common_reset(VGACommonState *s)
e89f66ec 1914{
6e6b7363
BS		 1915 s->sr_index = 0;
1916 memset(s->sr, '\0', sizeof(s->sr));
1917 s->gr_index = 0;
1918 memset(s->gr, '\0', sizeof(s->gr));
1919 s->ar_index = 0;
1920 memset(s->ar, '\0', sizeof(s->ar));
1921 s->ar_flip_flop = 0;
1922 s->cr_index = 0;
1923 memset(s->cr, '\0', sizeof(s->cr));
1924 s->msr = 0;
1925 s->fcr = 0;
1926 s->st00 = 0;
1927 s->st01 = 0;
1928 s->dac_state = 0;
1929 s->dac_sub_index = 0;
1930 s->dac_read_index = 0;
1931 s->dac_write_index = 0;
1932 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1933 s->dac_8bit = 0;
1934 memset(s->palette, '\0', sizeof(s->palette));
1935 s->bank_offset = 0;
1936#ifdef CONFIG_BOCHS_VBE
1937 s->vbe_index = 0;
1938 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
af92284b 1939 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
6e6b7363
BS		 1940 s->vbe_start_addr = 0;
1941 s->vbe_line_offset = 0;
1942 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1943#endif
1944 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
799e709b 1945 s->graphic_mode = -1; /* force full update */
6e6b7363
BS		 1946 s->shift_control = 0;
1947 s->double_scan = 0;
1948 s->line_offset = 0;
1949 s->line_compare = 0;
1950 s->start_addr = 0;
1951 s->plane_updated = 0;
1952 s->last_cw = 0;
1953 s->last_ch = 0;
1954 s->last_width = 0;
1955 s->last_height = 0;
1956 s->last_scr_width = 0;
1957 s->last_scr_height = 0;
1958 s->cursor_start = 0;
1959 s->cursor_end = 0;
1960 s->cursor_offset = 0;
1961 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1962 memset(s->last_palette, '\0', sizeof(s->last_palette));
1963 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1964 switch (vga_retrace_method) {
1965 case VGA_RETRACE_DUMB:
1966 break;
1967 case VGA_RETRACE_PRECISE:
1968 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1969 break;
1970 }
80763888 1971 vga_update_memory_access(s);
e89f66ec
FB		 1972}
1973
03a3e7ba
JQ		 1974static void vga_reset(void *opaque)
1975{
cedd91d2 1976 VGACommonState *s = opaque;
03a3e7ba
JQ		 1977 vga_common_reset(s);
1978}
1979
4d3b6f6e
AZ		 1980#define TEXTMODE_X(x) ((x) % width)
1981#define TEXTMODE_Y(x) ((x) / width)
1982#define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1983 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1984/* relay text rendering to the display driver
1985 * instead of doing a full vga_update_display() */
c227f099 1986static void vga_update_text(void *opaque, console_ch_t *chardata)
4d3b6f6e 1987{
cedd91d2 1988 VGACommonState *s = opaque;
799e709b 1989 int graphic_mode, i, cursor_offset, cursor_visible;
4d3b6f6e
AZ		 1990 int cw, cheight, width, height, size, c_min, c_max;
1991 uint32_t *src;
c227f099 1992 console_ch_t *dst, val;
4d3b6f6e 1993 char msg_buffer[80];
799e709b
AL		 1994 int full_update = 0;
1995
e9a07334
JK		 1996 qemu_flush_coalesced_mmio_buffer();
1997
799e709b
AL		 1998 if (!(s->ar_index & 0x20)) {
1999 graphic_mode = GMODE_BLANK;
2000 } else {
5e55efc9 2001 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
799e709b
AL		 2002 }
2003 if (graphic_mode != s->graphic_mode) {
2004 s->graphic_mode = graphic_mode;
2005 full_update = 1;
2006 }
2007 if (s->last_width == -1) {
2008 s->last_width = 0;
2009 full_update = 1;
2010 }
4d3b6f6e 2011
799e709b 2012 switch (graphic_mode) {
4d3b6f6e
AZ		 2013 case GMODE_TEXT:
2014 /* TODO: update palette */
799e709b 2015 full_update |= update_basic_params(s);
4d3b6f6e 2016
799e709b 2017 /* total width & height */
5e55efc9 2018 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
799e709b 2019 cw = 8;
5e55efc9 2020 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
799e709b 2021 cw = 9;
5e55efc9
BS		 2022 }
2023 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
799e709b 2024 cw = 16; /* NOTE: no 18 pixel wide */
5e55efc9
BS		 2025 }
2026 width = (s->cr[VGA_CRTC_H_DISP] + 1);
2027 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
799e709b
AL		 2028 /* ugly hack for CGA 160x100x16 - explain me the logic */
2029 height = 100;
2030 } else {
5e55efc9
BS		 2031 height = s->cr[VGA_CRTC_V_DISP_END] |
2032 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
2033 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
799e709b 2034 height = (height + 1) / cheight;
4d3b6f6e
AZ		 2035 }
2036
2037 size = (height * width);
2038 if (size > CH_ATTR_SIZE) {
2039 if (!full_update)
2040 return;
2041
363a37d5
BS		 2042 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2043 width, height);
4d3b6f6e
AZ		 2044 break;
2045 }
2046
799e709b
AL		 2047 if (width != s->last_width || height != s->last_height ||
2048 cw != s->last_cw || cheight != s->last_ch) {
2049 s->last_scr_width = width * cw;
2050 s->last_scr_height = height * cheight;
2051 s->ds->surface->width = width;
2052 s->ds->surface->height = height;
2053 dpy_resize(s->ds);
2054 s->last_width = width;
2055 s->last_height = height;
2056 s->last_ch = cheight;
2057 s->last_cw = cw;
2058 full_update = 1;
2059 }
2060
4d3b6f6e 2061 /* Update "hardware" cursor */
5e55efc9
BS		 2062 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
2063 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
4d3b6f6e 2064 if (cursor_offset != s->cursor_offset ||
5e55efc9
BS		 2065 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
2066 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
2067 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
4d3b6f6e
AZ		 2068 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2069 dpy_cursor(s->ds,
2070 TEXTMODE_X(cursor_offset),
2071 TEXTMODE_Y(cursor_offset));
2072 else
2073 dpy_cursor(s->ds, -1, -1);
2074 s->cursor_offset = cursor_offset;
5e55efc9
BS		 2075 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
2076 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
4d3b6f6e
AZ		 2077 }
2078
2079 src = (uint32_t *) s->vram_ptr + s->start_addr;
2080 dst = chardata;
2081
2082 if (full_update) {
2083 for (i = 0; i < size; src ++, dst ++, i ++)
9ae19b65 2084 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2085
2086 dpy_update(s->ds, 0, 0, width, height);
2087 } else {
2088 c_max = 0;
2089
2090 for (i = 0; i < size; src ++, dst ++, i ++) {
9ae19b65 2091 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2092 if (*dst != val) {
2093 *dst = val;
2094 c_max = i;
2095 break;
2096 }
2097 }
2098 c_min = i;
2099 for (; i < size; src ++, dst ++, i ++) {
9ae19b65 2100 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
4d3b6f6e
AZ		 2101 if (*dst != val) {
2102 *dst = val;
2103 c_max = i;
2104 }
2105 }
2106
2107 if (c_min <= c_max) {
2108 i = TEXTMODE_Y(c_min);
2109 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2110 }
2111 }
2112
2113 return;
2114 case GMODE_GRAPH:
2115 if (!full_update)
2116 return;
2117
2118 s->get_resolution(s, &width, &height);
363a37d5
BS		 2119 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2120 width, height);
4d3b6f6e
AZ		 2121 break;
2122 case GMODE_BLANK:
2123 default:
2124 if (!full_update)
2125 return;
2126
363a37d5 2127 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
4d3b6f6e
AZ		 2128 break;
2129 }
2130
2131 /* Display a message */
5228c2d3
AZ		 2132 s->last_width = 60;
2133 s->last_height = height = 3;
4d3b6f6e 2134 dpy_cursor(s->ds, -1, -1);
7d957bd8
AL		 2135 s->ds->surface->width = s->last_width;
2136 s->ds->surface->height = height;
2137 dpy_resize(s->ds);
4d3b6f6e 2138
5228c2d3 2139 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
4d3b6f6e
AZ		 2140 console_write_ch(dst ++, ' ');
2141
2142 size = strlen(msg_buffer);
5228c2d3
AZ		 2143 width = (s->last_width - size) / 2;
2144 dst = chardata + s->last_width + width;
4d3b6f6e
AZ		 2145 for (i = 0; i < size; i ++)
2146 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2147
5228c2d3 2148 dpy_update(s->ds, 0, 0, s->last_width, height);
4d3b6f6e
AZ		 2149}
2150
b1950430
AK		 2151static uint64_t vga_mem_read(void *opaque, target_phys_addr_t addr,
2152 unsigned size)
2153{
2154 VGACommonState *s = opaque;
2155
b2a5e761 2156 return vga_mem_readb(s, addr);
b1950430 2157}
e89f66ec 2158
b1950430
AK		 2159static void vga_mem_write(void *opaque, target_phys_addr_t addr,
2160 uint64_t data, unsigned size)
2161{
2162 VGACommonState *s = opaque;
2163
b2a5e761 2164 return vga_mem_writeb(s, addr, data);
b1950430
AK		 2165}
2166
2167const MemoryRegionOps vga_mem_ops = {
2168 .read = vga_mem_read,
2169 .write = vga_mem_write,
2170 .endianness = DEVICE_LITTLE_ENDIAN,
b2a5e761
AK		 2171 .impl = {
2172 .min_access_size = 1,
2173 .max_access_size = 1,
2174 },
e89f66ec
FB		 2175};
2176
11b6b345 2177static int vga_common_post_load(void *opaque, int version_id)
b0a21b53 2178{
0d65ddc3 2179 VGACommonState *s = opaque;
11b6b345
JQ		 2180
2181 /* force refresh */
2182 s->graphic_mode = -1;
2183 return 0;
2184}
2185
2186const VMStateDescription vmstate_vga_common = {
2187 .name = "vga",
2188 .version_id = 2,
2189 .minimum_version_id = 2,
2190 .minimum_version_id_old = 2,
2191 .post_load = vga_common_post_load,
2192 .fields = (VMStateField []) {
2193 VMSTATE_UINT32(latch, VGACommonState),
2194 VMSTATE_UINT8(sr_index, VGACommonState),
2195 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2196 VMSTATE_UINT8(gr_index, VGACommonState),
2197 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2198 VMSTATE_UINT8(ar_index, VGACommonState),
2199 VMSTATE_BUFFER(ar, VGACommonState),
2200 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2201 VMSTATE_UINT8(cr_index, VGACommonState),
2202 VMSTATE_BUFFER(cr, VGACommonState),
2203 VMSTATE_UINT8(msr, VGACommonState),
2204 VMSTATE_UINT8(fcr, VGACommonState),
2205 VMSTATE_UINT8(st00, VGACommonState),
2206 VMSTATE_UINT8(st01, VGACommonState),
2207
2208 VMSTATE_UINT8(dac_state, VGACommonState),
2209 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2210 VMSTATE_UINT8(dac_read_index, VGACommonState),
2211 VMSTATE_UINT8(dac_write_index, VGACommonState),
2212 VMSTATE_BUFFER(dac_cache, VGACommonState),
2213 VMSTATE_BUFFER(palette, VGACommonState),
2214
2215 VMSTATE_INT32(bank_offset, VGACommonState),
2216 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
b0a21b53 2217#ifdef CONFIG_BOCHS_VBE
11b6b345
JQ		 2218 VMSTATE_UINT16(vbe_index, VGACommonState),
2219 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2220 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2221 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2222 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
b0a21b53 2223#endif
11b6b345
JQ		 2224 VMSTATE_END_OF_LIST()
2225 }
2226};
2227
a4a2f59c 2228void vga_common_init(VGACommonState *s, int vga_ram_size)
e89f66ec 2229{
17b0018b 2230 int i, j, v, b;
e89f66ec
FB		 2231
2232 for(i = 0;i < 256; i++) {
2233 v = 0;
2234 for(j = 0; j < 8; j++) {
2235 v |= ((i >> j) & 1) << (j * 4);
2236 }
2237 expand4[i] = v;
2238
2239 v = 0;
2240 for(j = 0; j < 4; j++) {
2241 v |= ((i >> (2 * j)) & 3) << (j * 4);
2242 }
2243 expand2[i] = v;
2244 }
17b0018b
FB		 2245 for(i = 0; i < 16; i++) {
2246 v = 0;
2247 for(j = 0; j < 4; j++) {
2248 b = ((i >> j) & 1);
2249 v |= b << (2 * j);
2250 v |= b << (2 * j + 1);
2251 }
2252 expand4to8[i] = v;
2253 }
e89f66ec 2254
2a3138ab
JQ		 2255#ifdef CONFIG_BOCHS_VBE
2256 s->is_vbe_vmstate = 1;
2257#else
2258 s->is_vbe_vmstate = 0;
2259#endif
c5705a77
AK		 2260 memory_region_init_ram(&s->vram, "vga.vram", vga_ram_size);
2261 vmstate_register_ram_global(&s->vram);
c65adf9b 2262 xen_register_framebuffer(&s->vram);
b1950430 2263 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
e89f66ec 2264 s->vram_size = vga_ram_size;
798b0c25
FB		 2265 s->get_bpp = vga_get_bpp;
2266 s->get_offsets = vga_get_offsets;
a130a41e 2267 s->get_resolution = vga_get_resolution;
d34cab9f
TS		 2268 s->update = vga_update_display;
2269 s->invalidate = vga_invalidate_display;
2270 s->screen_dump = vga_screen_dump;
4d3b6f6e 2271 s->text_update = vga_update_text;
cb5a7aa8 2272 switch (vga_retrace_method) {
2273 case VGA_RETRACE_DUMB:
2274 s->retrace = vga_dumb_retrace;
2275 s->update_retrace_info = vga_dumb_update_retrace_info;
2276 break;
2277
2278 case VGA_RETRACE_PRECISE:
2279 s->retrace = vga_precise_retrace;
2280 s->update_retrace_info = vga_precise_update_retrace_info;
cb5a7aa8 2281 break;
2282 }
b1950430 2283 vga_dirty_log_start(s);
798b0c25
FB		 2284}
2285
0a039dc7
RH		 2286static const MemoryRegionPortio vga_portio_list[] = {
2287 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2288 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2289 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2290 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2291 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2292 PORTIO_END_OF_LIST(),
2293};
e89f66ec 2294
4fa0f5d2 2295#ifdef CONFIG_BOCHS_VBE
0a039dc7
RH		 2296static const MemoryRegionPortio vbe_portio_list[] = {
2297 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2298# ifdef TARGET_I386
2299 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2300# else
2301 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2302# endif
2303 PORTIO_END_OF_LIST(),
2304};
2305#endif /* CONFIG_BOCHS_VBE */
4fa0f5d2 2306
0a039dc7
RH		 2307/* Used by both ISA and PCI */
2308MemoryRegion *vga_init_io(VGACommonState *s,
2309 const MemoryRegionPortio **vga_ports,
2310 const MemoryRegionPortio **vbe_ports)
2311{
2312 MemoryRegion *vga_mem;
09a79b49 2313
0a039dc7
RH		 2314 *vga_ports = vga_portio_list;
2315 *vbe_ports = NULL;
2316#ifdef CONFIG_BOCHS_VBE
2317 *vbe_ports = vbe_portio_list;
4fa0f5d2
FB		 2318#endif
2319
7267c094 2320 vga_mem = g_malloc(sizeof(*vga_mem));
b1950430
AK		 2321 memory_region_init_io(vga_mem, &vga_mem_ops, s,
2322 "vga-lowmem", 0x20000);
2323
2324 return vga_mem;
7435b791
BS		 2325}
2326
0a039dc7
RH		 2327void vga_init(VGACommonState *s, MemoryRegion *address_space,
2328 MemoryRegion *address_space_io, bool init_vga_ports)
7435b791 2329{
b1950430 2330 MemoryRegion *vga_io_memory;
0a039dc7
RH		 2331 const MemoryRegionPortio *vga_ports, *vbe_ports;
2332 PortioList *vga_port_list = g_new(PortioList, 1);
2333 PortioList *vbe_port_list = g_new(PortioList, 1);
7435b791
BS		 2334
2335 qemu_register_reset(vga_reset, s);
2336
2337 s->bank_offset = 0;
2338
80763888
JK		 2339 s->legacy_address_space = address_space;
2340
0a039dc7 2341 vga_io_memory = vga_init_io(s, &vga_ports, &vbe_ports);
be20f9e9 2342 memory_region_add_subregion_overlap(address_space,
b1950430
AK		 2343 isa_mem_base + 0x000a0000,
2344 vga_io_memory,
2345 1);
2346 memory_region_set_coalescing(vga_io_memory);
0a039dc7
RH		 2347 if (init_vga_ports) {
2348 portio_list_init(vga_port_list, vga_ports, s, "vga");
2349 portio_list_add(vga_port_list, address_space_io, 0x3b0);
2350 }
2351 if (vbe_ports) {
2352 portio_list_init(vbe_port_list, vbe_ports, s, "vbe");
2353 portio_list_add(vbe_port_list, address_space_io, 0x1ce);
2354 }
d2269f6f
FB		 2355}
2356
be20f9e9 2357void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory)
f0138a63
AL		 2358{
2359#ifdef CONFIG_BOCHS_VBE
2360 /* XXX: use optimized standard vga accesses */
be20f9e9 2361 memory_region_add_subregion(system_memory,
b1950430
AK		 2362 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2363 &s->vram);
f0138a63
AL		 2364 s->vbe_mapped = 1;
2365#endif
2366}
59a983b9
FB		 2367/********************************************************/
2368/* vga screen dump */
2369
e07d630a 2370int ppm_save(const char *filename, struct DisplaySurface *ds)
59a983b9
FB		 2371{
2372 FILE *f;
2373 uint8_t *d, *d1;
e07d630a 2374 uint32_t v;
59a983b9 2375 int y, x;
e07d630a 2376 uint8_t r, g, b;
f8e378f2
AK		 2377 int ret;
2378 char *linebuf, *pbuf;
59a983b9 2379
72750018 2380 trace_ppm_save(filename, ds);
59a983b9
FB		 2381 f = fopen(filename, "wb");
2382 if (!f)
2383 return -1;
2384 fprintf(f, "P6\n%d %d\n%d\n",
e07d630a 2385 ds->width, ds->height, 255);
7267c094 2386 linebuf = g_malloc(ds->width * 3);
e07d630a
AL		 2387 d1 = ds->data;
2388 for(y = 0; y < ds->height; y++) {
59a983b9 2389 d = d1;
f8e378f2 2390 pbuf = linebuf;
e07d630a
AL		 2391 for(x = 0; x < ds->width; x++) {
2392 if (ds->pf.bits_per_pixel == 32)
2393 v = *(uint32_t *)d;
2394 else
2395 v = (uint32_t) (*(uint16_t *)d);
a0f42610
AK		 2396 /* Limited to 8 or fewer bits per channel: */
2397 r = ((v >> ds->pf.rshift) & ds->pf.rmax) << (8 - ds->pf.rbits);
2398 g = ((v >> ds->pf.gshift) & ds->pf.gmax) << (8 - ds->pf.gbits);
2399 b = ((v >> ds->pf.bshift) & ds->pf.bmax) << (8 - ds->pf.bbits);
f8e378f2
AK		 2400 *pbuf++ = r;
2401 *pbuf++ = g;
2402 *pbuf++ = b;
e07d630a 2403 d += ds->pf.bytes_per_pixel;
59a983b9 2404 }
e07d630a 2405 d1 += ds->linesize;
f8e378f2
AK		 2406 ret = fwrite(linebuf, 1, pbuf - linebuf, f);
2407 (void)ret;
59a983b9 2408 }
7267c094 2409 g_free(linebuf);
59a983b9
FB		 2410 fclose(f);
2411 return 0;
2412}
2413
4c5e8c5c
BS		 2414/* save the vga display in a PPM image even if no display is
2415 available */
45efb161 2416static void vga_screen_dump(void *opaque, const char *filename, bool cswitch)
4c5e8c5c 2417{
cedd91d2 2418 VGACommonState *s = opaque;
4c5e8c5c 2419
45efb161
GH		 2420 if (cswitch) {
2421 vga_invalidate_display(s);
45efb161 2422 }
08c4ea29 2423 vga_hw_update();
9a51f5b0 2424 ppm_save(filename, s->ds->surface);
4c5e8c5c 2425}
Qemu copy for testing