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798b0c25 FB |
1 | /* |
2 | * QEMU internal VGA defines. | |
3 | * | |
4 | * Copyright (c) 2003-2004 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #define MSR_COLOR_EMULATION 0x01 | |
25 | #define MSR_PAGE_SELECT 0x20 | |
26 | ||
27 | #define ST01_V_RETRACE 0x08 | |
28 | #define ST01_DISP_ENABLE 0x01 | |
29 | ||
30 | /* bochs VBE support */ | |
31 | #define CONFIG_BOCHS_VBE | |
32 | ||
33 | #define VBE_DISPI_MAX_XRES 1024 | |
34 | #define VBE_DISPI_MAX_YRES 768 | |
35 | ||
36 | #define VBE_DISPI_INDEX_ID 0x0 | |
37 | #define VBE_DISPI_INDEX_XRES 0x1 | |
38 | #define VBE_DISPI_INDEX_YRES 0x2 | |
39 | #define VBE_DISPI_INDEX_BPP 0x3 | |
40 | #define VBE_DISPI_INDEX_ENABLE 0x4 | |
41 | #define VBE_DISPI_INDEX_BANK 0x5 | |
42 | #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6 | |
43 | #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7 | |
44 | #define VBE_DISPI_INDEX_X_OFFSET 0x8 | |
45 | #define VBE_DISPI_INDEX_Y_OFFSET 0x9 | |
46 | #define VBE_DISPI_INDEX_NB 0xa | |
47 | ||
48 | #define VBE_DISPI_ID0 0xB0C0 | |
49 | #define VBE_DISPI_ID1 0xB0C1 | |
50 | #define VBE_DISPI_ID2 0xB0C2 | |
51 | ||
52 | #define VBE_DISPI_DISABLED 0x00 | |
53 | #define VBE_DISPI_ENABLED 0x01 | |
54 | #define VBE_DISPI_LFB_ENABLED 0x40 | |
55 | #define VBE_DISPI_NOCLEARMEM 0x80 | |
56 | ||
57 | #define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000 | |
58 | ||
798b0c25 | 59 | #ifdef CONFIG_BOCHS_VBE |
4e3e9d0b FB |
60 | |
61 | #define VGA_STATE_COMMON_BOCHS_VBE \ | |
62 | uint16_t vbe_index; \ | |
63 | uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \ | |
64 | uint32_t vbe_start_addr; \ | |
65 | uint32_t vbe_line_offset; \ | |
798b0c25 | 66 | uint32_t vbe_bank_mask; |
4e3e9d0b FB |
67 | |
68 | #else | |
69 | ||
70 | #define VGA_STATE_COMMON_BOCHS_VBE | |
71 | ||
72 | #endif /* !CONFIG_BOCHS_VBE */ | |
73 | ||
798b0c25 | 74 | #define CH_ATTR_SIZE (160 * 100) |
a8aa669b | 75 | #define VGA_MAX_HEIGHT 1024 |
4e3e9d0b FB |
76 | |
77 | #define VGA_STATE_COMMON \ | |
78 | uint8_t *vram_ptr; \ | |
79 | unsigned long vram_offset; \ | |
80 | unsigned int vram_size; \ | |
d5295253 FB |
81 | unsigned long bios_offset; \ |
82 | unsigned int bios_size; \ | |
4e3e9d0b FB |
83 | uint32_t latch; \ |
84 | uint8_t sr_index; \ | |
85 | uint8_t sr[256]; \ | |
86 | uint8_t gr_index; \ | |
87 | uint8_t gr[256]; \ | |
88 | uint8_t ar_index; \ | |
89 | uint8_t ar[21]; \ | |
90 | int ar_flip_flop; \ | |
91 | uint8_t cr_index; \ | |
92 | uint8_t cr[256]; /* CRT registers */ \ | |
93 | uint8_t msr; /* Misc Output Register */ \ | |
94 | uint8_t fcr; /* Feature Control Register */ \ | |
95 | uint8_t st00; /* status 0 */ \ | |
96 | uint8_t st01; /* status 1 */ \ | |
97 | uint8_t dac_state; \ | |
98 | uint8_t dac_sub_index; \ | |
99 | uint8_t dac_read_index; \ | |
100 | uint8_t dac_write_index; \ | |
101 | uint8_t dac_cache[3]; /* used when writing */ \ | |
102 | uint8_t palette[768]; \ | |
103 | int32_t bank_offset; \ | |
104 | int (*get_bpp)(struct VGAState *s); \ | |
105 | void (*get_offsets)(struct VGAState *s, \ | |
106 | uint32_t *pline_offset, \ | |
107 | uint32_t *pstart_addr); \ | |
a130a41e FB |
108 | void (*get_resolution)(struct VGAState *s, \ |
109 | int *pwidth, \ | |
110 | int *pheight); \ | |
4e3e9d0b FB |
111 | VGA_STATE_COMMON_BOCHS_VBE \ |
112 | /* display refresh support */ \ | |
113 | DisplayState *ds; \ | |
114 | uint32_t font_offsets[2]; \ | |
115 | int graphic_mode; \ | |
116 | uint8_t shift_control; \ | |
117 | uint8_t double_scan; \ | |
118 | uint32_t line_offset; \ | |
119 | uint32_t line_compare; \ | |
120 | uint32_t start_addr; \ | |
546fa6ab | 121 | uint32_t plane_updated; \ |
4e3e9d0b FB |
122 | uint8_t last_cw, last_ch; \ |
123 | uint32_t last_width, last_height; /* in chars or pixels */ \ | |
124 | uint32_t last_scr_width, last_scr_height; /* in pixels */ \ | |
125 | uint8_t cursor_start, cursor_end; \ | |
126 | uint32_t cursor_offset; \ | |
127 | unsigned int (*rgb_to_pixel)(unsigned int r, \ | |
128 | unsigned int g, unsigned b); \ | |
a8aa669b FB |
129 | /* hardware mouse cursor support */ \ |
130 | uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \ | |
131 | void (*cursor_invalidate)(struct VGAState *s); \ | |
132 | void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y); \ | |
4e3e9d0b FB |
133 | /* tell for each page if it has been updated since the last time */ \ |
134 | uint32_t last_palette[256]; \ | |
798b0c25 | 135 | uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */ |
4e3e9d0b FB |
136 | |
137 | ||
138 | typedef struct VGAState { | |
139 | VGA_STATE_COMMON | |
798b0c25 FB |
140 | } VGAState; |
141 | ||
a8aa669b FB |
142 | static inline int c6_to_8(int v) |
143 | { | |
144 | int b; | |
145 | v &= 0x3f; | |
146 | b = v & 1; | |
147 | return (v << 2) | (b << 1) | b; | |
148 | } | |
149 | ||
798b0c25 FB |
150 | void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base, |
151 | unsigned long vga_ram_offset, int vga_ram_size); | |
152 | uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr); | |
153 | void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val); | |
a8aa669b FB |
154 | void vga_invalidate_scanlines(VGAState *s, int y1, int y2); |
155 | ||
156 | void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1, | |
157 | int poffset, int w, | |
158 | unsigned int color0, unsigned int color1, | |
159 | unsigned int color_xor); | |
160 | void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1, | |
161 | int poffset, int w, | |
162 | unsigned int color0, unsigned int color1, | |
163 | unsigned int color_xor); | |
164 | void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1, | |
165 | int poffset, int w, | |
166 | unsigned int color0, unsigned int color1, | |
167 | unsigned int color_xor); | |
798b0c25 FB |
168 | |
169 | extern const uint8_t sr_mask[8]; | |
170 | extern const uint8_t gr_mask[16]; |