[qemu.git] / hw / vga_int.h

/*
 * QEMU internal VGA defines.
 *
 * Copyright (c) 2003-2004 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#define MSR_COLOR_EMULATION 0x01
#define MSR_PAGE_SELECT     0x20

#define ST01_V_RETRACE      0x08
#define ST01_DISP_ENABLE    0x01

/* bochs VBE support */
#define CONFIG_BOCHS_VBE

#define VBE_DISPI_MAX_XRES              1600
#define VBE_DISPI_MAX_YRES              1200
#define VBE_DISPI_MAX_BPP               32

#define VBE_DISPI_INDEX_ID              0x0
#define VBE_DISPI_INDEX_XRES            0x1
#define VBE_DISPI_INDEX_YRES            0x2
#define VBE_DISPI_INDEX_BPP             0x3
#define VBE_DISPI_INDEX_ENABLE          0x4
#define VBE_DISPI_INDEX_BANK            0x5
#define VBE_DISPI_INDEX_VIRT_WIDTH      0x6
#define VBE_DISPI_INDEX_VIRT_HEIGHT     0x7
#define VBE_DISPI_INDEX_X_OFFSET        0x8
#define VBE_DISPI_INDEX_Y_OFFSET        0x9
#define VBE_DISPI_INDEX_NB              0xa

#define VBE_DISPI_ID0                   0xB0C0
#define VBE_DISPI_ID1                   0xB0C1
#define VBE_DISPI_ID2                   0xB0C2
#define VBE_DISPI_ID3                   0xB0C3
#define VBE_DISPI_ID4                   0xB0C4

#define VBE_DISPI_DISABLED              0x00
#define VBE_DISPI_ENABLED               0x01
#define VBE_DISPI_GETCAPS               0x02
#define VBE_DISPI_8BIT_DAC              0x20
#define VBE_DISPI_LFB_ENABLED           0x40
#define VBE_DISPI_NOCLEARMEM            0x80

#define VBE_DISPI_LFB_PHYSICAL_ADDRESS  0xE0000000

#ifdef CONFIG_BOCHS_VBE

#define VGA_STATE_COMMON_BOCHS_VBE              \
    uint16_t vbe_index;                         \
    uint16_t vbe_regs[VBE_DISPI_INDEX_NB];      \
    uint32_t vbe_start_addr;                    \
    uint32_t vbe_line_offset;                   \
    uint32_t vbe_bank_mask;

#else

#define VGA_STATE_COMMON_BOCHS_VBE

#endif /* !CONFIG_BOCHS_VBE */

#define CH_ATTR_SIZE (160 * 100)
#define VGA_MAX_HEIGHT 2048

struct vga_precise_retrace {
    int64_t ticks_per_char;
    int64_t total_chars;
    int htotal;
    int hstart;
    int hend;
    int vstart;
    int vend;
    int freq;
};

union vga_retrace {
    struct vga_precise_retrace precise;
};

struct VGACommonState;
typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);

typedef struct VGACommonState {
    uint8_t *vram_ptr;
    ram_addr_t vram_offset;
    unsigned int vram_size;
    uint32_t lfb_addr;
    uint32_t lfb_end;
    uint32_t map_addr;
    uint32_t map_end;
    uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */
    uint32_t bios_offset;
    uint32_t bios_size;
    uint32_t latch;
    uint8_t sr_index;
    uint8_t sr[256];
    uint8_t gr_index;
    uint8_t gr[256];
    uint8_t ar_index;
    uint8_t ar[21];
    int ar_flip_flop;
    uint8_t cr_index;
    uint8_t cr[256]; /* CRT registers */
    uint8_t msr; /* Misc Output Register */
    uint8_t fcr; /* Feature Control Register */
    uint8_t st00; /* status 0 */
    uint8_t st01; /* status 1 */
    uint8_t dac_state;
    uint8_t dac_sub_index;
    uint8_t dac_read_index;
    uint8_t dac_write_index;
    uint8_t dac_cache[3]; /* used when writing */
    int dac_8bit;
    uint8_t palette[768];
    int32_t bank_offset;
    int vga_io_memory;
    int (*get_bpp)(struct VGACommonState *s);
    void (*get_offsets)(struct VGACommonState *s,
                        uint32_t *pline_offset,
                        uint32_t *pstart_addr,
                        uint32_t *pline_compare);
    void (*get_resolution)(struct VGACommonState *s,
                        int *pwidth,
                        int *pheight);
    VGA_STATE_COMMON_BOCHS_VBE
    /* display refresh support */
    DisplayState *ds;
    uint32_t font_offsets[2];
    int graphic_mode;
    uint8_t shift_control;
    uint8_t double_scan;
    uint32_t line_offset;
    uint32_t line_compare;
    uint32_t start_addr;
    uint32_t plane_updated;
    uint32_t last_line_offset;
    uint8_t last_cw, last_ch;
    uint32_t last_width, last_height; /* in chars or pixels */
    uint32_t last_scr_width, last_scr_height; /* in pixels */
    uint32_t last_depth; /* in bits */
    uint8_t full_update;
    uint8_t cursor_start, cursor_end;
    uint32_t cursor_offset;
    unsigned int (*rgb_to_pixel)(unsigned int r,
                                 unsigned int g, unsigned b);
    vga_hw_update_ptr update;
    vga_hw_invalidate_ptr invalidate;
    vga_hw_screen_dump_ptr screen_dump;
    vga_hw_text_update_ptr text_update;
    /* hardware mouse cursor support */
    uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
    void (*cursor_invalidate)(struct VGACommonState *s);
    void (*cursor_draw_line)(struct VGACommonState *s, uint8_t *d, int y);
    /* tell for each page if it has been updated since the last time */
    uint32_t last_palette[256];
    uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
    /* retrace */
    vga_retrace_fn retrace;
    vga_update_retrace_info_fn update_retrace_info;
    union vga_retrace retrace_info;
} VGACommonState;

static inline int c6_to_8(int v)
{
    int b;
    v &= 0x3f;
    b = v & 1;
    return (v << 2) | (b << 1) | b;
}

void vga_common_init(VGACommonState *s, int vga_ram_size);
void vga_init(VGACommonState *s);
void vga_common_reset(VGACommonState *s);

void vga_dirty_log_start(VGACommonState *s);

void vga_common_save(QEMUFile *f, void *opaque);
int vga_common_load(QEMUFile *f, void *opaque, int version_id);
uint32_t vga_ioport_read(void *opaque, uint32_t addr);
void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
int ppm_save(const char *filename, struct DisplaySurface *ds);

void vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
                            int poffset, int w,
                            unsigned int color0, unsigned int color1,
                            unsigned int color_xor);
void vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
                             int poffset, int w,
                             unsigned int color0, unsigned int color1,
                             unsigned int color_xor);
void vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
                             int poffset, int w,
                             unsigned int color0, unsigned int color1,
                             unsigned int color_xor);

int vga_ioport_invalid(VGACommonState *s, uint32_t addr);

extern const uint8_t sr_mask[8];
extern const uint8_t gr_mask[16];

#define VGA_RAM_SIZE (8192 * 1024)

extern CPUReadMemoryFunc * const vga_mem_read[3];
extern CPUWriteMemoryFunc * const vga_mem_write[3];
Commit	Line	Data
798b0c25 FB	1	/*
798b0c25 FB	2	* QEMU internal VGA defines.
5fafdf24	3	*
798b0c25	4	* Copyright (c) 2003-2004 Fabrice Bellard
5fafdf24	5	*
798b0c25 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#define MSR_COLOR_EMULATION 0x01
	25	#define MSR_PAGE_SELECT 0x20
	26
	27	#define ST01_V_RETRACE 0x08
	28	#define ST01_DISP_ENABLE 0x01
	29
	30	/* bochs VBE support */
	31	#define CONFIG_BOCHS_VBE
	32
8454df8b FB	33	#define VBE_DISPI_MAX_XRES 1600
	34	#define VBE_DISPI_MAX_YRES 1200
	35	#define VBE_DISPI_MAX_BPP 32
798b0c25 FB	36
	37	#define VBE_DISPI_INDEX_ID 0x0
	38	#define VBE_DISPI_INDEX_XRES 0x1
	39	#define VBE_DISPI_INDEX_YRES 0x2
	40	#define VBE_DISPI_INDEX_BPP 0x3
	41	#define VBE_DISPI_INDEX_ENABLE 0x4
	42	#define VBE_DISPI_INDEX_BANK 0x5
	43	#define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
	44	#define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
	45	#define VBE_DISPI_INDEX_X_OFFSET 0x8
	46	#define VBE_DISPI_INDEX_Y_OFFSET 0x9
	47	#define VBE_DISPI_INDEX_NB 0xa
3b46e624	48
798b0c25 FB	49	#define VBE_DISPI_ID0 0xB0C0
	50	#define VBE_DISPI_ID1 0xB0C1
	51	#define VBE_DISPI_ID2 0xB0C2
37dd208d FB	52	#define VBE_DISPI_ID3 0xB0C3
37dd208d FB	53	#define VBE_DISPI_ID4 0xB0C4
3b46e624	54
798b0c25 FB	55	#define VBE_DISPI_DISABLED 0x00
798b0c25 FB	56	#define VBE_DISPI_ENABLED 0x01
8454df8b FB	57	#define VBE_DISPI_GETCAPS 0x02
8454df8b FB	58	#define VBE_DISPI_8BIT_DAC 0x20
798b0c25 FB	59	#define VBE_DISPI_LFB_ENABLED 0x40
798b0c25 FB	60	#define VBE_DISPI_NOCLEARMEM 0x80
3b46e624	61
798b0c25 FB	62	#define VBE_DISPI_LFB_PHYSICAL_ADDRESS 0xE0000000
798b0c25 FB	63
798b0c25	64	#ifdef CONFIG_BOCHS_VBE
4e3e9d0b FB	65
	66	#define VGA_STATE_COMMON_BOCHS_VBE \
	67	uint16_t vbe_index; \
	68	uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
	69	uint32_t vbe_start_addr; \
	70	uint32_t vbe_line_offset; \
798b0c25	71	uint32_t vbe_bank_mask;
4e3e9d0b FB	72
	73	#else
	74
	75	#define VGA_STATE_COMMON_BOCHS_VBE
	76
	77	#endif /* !CONFIG_BOCHS_VBE */
	78
798b0c25	79	#define CH_ATTR_SIZE (160 * 100)
8454df8b	80	#define VGA_MAX_HEIGHT 2048
4e3e9d0b	81
cb5a7aa8	82	struct vga_precise_retrace {
	83	int64_t ticks_per_char;
	84	int64_t total_chars;
	85	int htotal;
	86	int hstart;
	87	int hend;
	88	int vstart;
	89	int vend;
	90	int freq;
	91	};
	92
	93	union vga_retrace {
	94	struct vga_precise_retrace precise;
	95	};
	96
4e12cd94 AK	97	struct VGACommonState;
	98	typedef uint8_t (* vga_retrace_fn)(struct VGACommonState *s);
	99	typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s);
	100
	101	typedef struct VGACommonState {
	102	uint8_t *vram_ptr;
c227f099	103	ram_addr_t vram_offset;
4e12cd94 AK	104	unsigned int vram_size;
	105	uint32_t lfb_addr;
	106	uint32_t lfb_end;
	107	uint32_t map_addr;
	108	uint32_t map_end;
	109	uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */
df59cbc6 GH	110	uint32_t bios_offset;
df59cbc6 GH	111	uint32_t bios_size;
4e12cd94 AK	112	uint32_t latch;
	113	uint8_t sr_index;
	114	uint8_t sr[256];
	115	uint8_t gr_index;
	116	uint8_t gr[256];
	117	uint8_t ar_index;
	118	uint8_t ar[21];
	119	int ar_flip_flop;
	120	uint8_t cr_index;
	121	uint8_t cr[256]; /* CRT registers */
	122	uint8_t msr; /* Misc Output Register */
	123	uint8_t fcr; /* Feature Control Register */
	124	uint8_t st00; /* status 0 */
	125	uint8_t st01; /* status 1 */
	126	uint8_t dac_state;
	127	uint8_t dac_sub_index;
	128	uint8_t dac_read_index;
	129	uint8_t dac_write_index;
	130	uint8_t dac_cache[3]; /* used when writing */
	131	int dac_8bit;
	132	uint8_t palette[768];
	133	int32_t bank_offset;
	134	int vga_io_memory;
	135	int (get_bpp)(struct VGACommonState s);
	136	void (get_offsets)(struct VGACommonState s,
	137	uint32_t *pline_offset,
	138	uint32_t *pstart_addr,
	139	uint32_t *pline_compare);
	140	void (get_resolution)(struct VGACommonState s,
	141	int *pwidth,
	142	int *pheight);
	143	VGA_STATE_COMMON_BOCHS_VBE
	144	/* display refresh support */
	145	DisplayState *ds;
	146	uint32_t font_offsets[2];
	147	int graphic_mode;
	148	uint8_t shift_control;
	149	uint8_t double_scan;
	150	uint32_t line_offset;
	151	uint32_t line_compare;
	152	uint32_t start_addr;
	153	uint32_t plane_updated;
	154	uint32_t last_line_offset;
	155	uint8_t last_cw, last_ch;
	156	uint32_t last_width, last_height; /* in chars or pixels */
	157	uint32_t last_scr_width, last_scr_height; /* in pixels */
	158	uint32_t last_depth; /* in bits */
0bd8246b	159	uint8_t full_update;
4e12cd94 AK	160	uint8_t cursor_start, cursor_end;
	161	uint32_t cursor_offset;
	162	unsigned int (*rgb_to_pixel)(unsigned int r,
	163	unsigned int g, unsigned b);
	164	vga_hw_update_ptr update;
	165	vga_hw_invalidate_ptr invalidate;
	166	vga_hw_screen_dump_ptr screen_dump;
	167	vga_hw_text_update_ptr text_update;
	168	/* hardware mouse cursor support */
	169	uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32];
	170	void (cursor_invalidate)(struct VGACommonState s);
	171	void (cursor_draw_line)(struct VGACommonState s, uint8_t *d, int y);
	172	/* tell for each page if it has been updated since the last time */
	173	uint32_t last_palette[256];
	174	uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
	175	/* retrace */
	176	vga_retrace_fn retrace;
	177	vga_update_retrace_info_fn update_retrace_info;
cb5a7aa8	178	union vga_retrace retrace_info;
4e12cd94	179	} VGACommonState;
4e3e9d0b	180
a8aa669b FB	181	static inline int c6_to_8(int v)
	182	{
	183	int b;
	184	v &= 0x3f;
	185	b = v & 1;
	186	return (v << 2) \| (b << 1) \| b;
	187	}
	188
a4a2f59c JQ	189	void vga_common_init(VGACommonState *s, int vga_ram_size);
a4a2f59c JQ	190	void vga_init(VGACommonState *s);
03a3e7ba	191	void vga_common_reset(VGACommonState *s);
2bec46dc	192
a4a2f59c	193	void vga_dirty_log_start(VGACommonState *s);
2bec46dc	194
0d65ddc3 JQ	195	void vga_common_save(QEMUFile f, void opaque);
0d65ddc3 JQ	196	int vga_common_load(QEMUFile f, void opaque, int version_id);
43bf782b JQ	197	uint32_t vga_ioport_read(void *opaque, uint32_t addr);
43bf782b JQ	198	void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val);
c227f099 AL	199	uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
c227f099 AL	200	void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
a4a2f59c	201	void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2);
e07d630a	202	int ppm_save(const char filename, struct DisplaySurface ds);
a8aa669b	203
5fafdf24 TS	204	void vga_draw_cursor_line_8(uint8_t d1, const uint8_t src1,
5fafdf24 TS	205	int poffset, int w,
a8aa669b FB	206	unsigned int color0, unsigned int color1,
a8aa669b FB	207	unsigned int color_xor);
5fafdf24 TS	208	void vga_draw_cursor_line_16(uint8_t d1, const uint8_t src1,
5fafdf24 TS	209	int poffset, int w,
a8aa669b FB	210	unsigned int color0, unsigned int color1,
a8aa669b FB	211	unsigned int color_xor);
5fafdf24 TS	212	void vga_draw_cursor_line_32(uint8_t d1, const uint8_t src1,
5fafdf24 TS	213	int poffset, int w,
a8aa669b FB	214	unsigned int color0, unsigned int color1,
a8aa669b FB	215	unsigned int color_xor);
798b0c25	216
25a18cbd JQ	217	int vga_ioport_invalid(VGACommonState *s, uint32_t addr);
25a18cbd JQ	218
798b0c25 FB	219	extern const uint8_t sr_mask[8];
798b0c25 FB	220	extern const uint8_t gr_mask[16];
fbe1b595 PB	221
	222	#define VGA_RAM_SIZE (8192 * 1024)
	223
f97e36b9 JQ	224	extern CPUReadMemoryFunc * const vga_mem_read[3];
f97e36b9 JQ	225	extern CPUWriteMemoryFunc * const vga_mem_write[3];