[qemu.git] / hw / virtio-pci.c

/*
 * Virtio PCI Bindings
 *
 * Copyright IBM, Corp. 2007
 * Copyright (c) 2009 CodeSourcery
 *
 * Authors:
 *  Anthony Liguori   <aliguori@us.ibm.com>
 *  Paul Brook        <paul@codesourcery.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

#include <inttypes.h>

#include "virtio.h"
#include "pci.h"
#include "sysemu.h"
#include "msix.h"
#include "net.h"
#include "loader.h"

/* from Linux's linux/virtio_pci.h */

/* A 32-bit r/o bitmask of the features supported by the host */
#define VIRTIO_PCI_HOST_FEATURES        0

/* A 32-bit r/w bitmask of features activated by the guest */
#define VIRTIO_PCI_GUEST_FEATURES       4

/* A 32-bit r/w PFN for the currently selected queue */
#define VIRTIO_PCI_QUEUE_PFN            8

/* A 16-bit r/o queue size for the currently selected queue */
#define VIRTIO_PCI_QUEUE_NUM            12

/* A 16-bit r/w queue selector */
#define VIRTIO_PCI_QUEUE_SEL            14

/* A 16-bit r/w queue notifier */
#define VIRTIO_PCI_QUEUE_NOTIFY         16

/* An 8-bit device status register.  */
#define VIRTIO_PCI_STATUS               18

/* An 8-bit r/o interrupt status register.  Reading the value will return the
 * current contents of the ISR and will also clear it.  This is effectively
 * a read-and-acknowledge. */
#define VIRTIO_PCI_ISR                  19

/* MSI-X registers: only enabled if MSI-X is enabled. */
/* A 16-bit vector for configuration changes. */
#define VIRTIO_MSI_CONFIG_VECTOR        20
/* A 16-bit vector for selected queue notifications. */
#define VIRTIO_MSI_QUEUE_VECTOR         22

/* Config space size */
#define VIRTIO_PCI_CONFIG_NOMSI         20
#define VIRTIO_PCI_CONFIG_MSI           24
#define VIRTIO_PCI_REGION_SIZE(dev)     (msix_present(dev) ? \
                                         VIRTIO_PCI_CONFIG_MSI : \
                                         VIRTIO_PCI_CONFIG_NOMSI)

/* The remaining space is defined by each driver as the per-driver
 * configuration space */
#define VIRTIO_PCI_CONFIG(dev)          (msix_enabled(dev) ? \
                                         VIRTIO_PCI_CONFIG_MSI : \
                                         VIRTIO_PCI_CONFIG_NOMSI)

/* Virtio ABI version, if we increment this, we break the guest driver. */
#define VIRTIO_PCI_ABI_VERSION          0

/* How many bits to shift physical queue address written to QUEUE_PFN.
 * 12 is historical, and due to x86 page size. */
#define VIRTIO_PCI_QUEUE_ADDR_SHIFT    12

/* QEMU doesn't strictly need write barriers since everything runs in
 * lock-step.  We'll leave the calls to wmb() in though to make it obvious for
 * KVM or if kqemu gets SMP support.
 */
#define wmb() do { } while (0)

/* PCI bindings.  */

typedef struct {
    PCIDevice pci_dev;
    VirtIODevice *vdev;
    uint32_t addr;
    uint32_t class_code;
    uint32_t nvectors;
    DriveInfo *dinfo;
    NICConf nic;
} VirtIOPCIProxy;

/* virtio device */

static void virtio_pci_notify(void *opaque, uint16_t vector)
{
    VirtIOPCIProxy *proxy = opaque;
    if (msix_enabled(&proxy->pci_dev))
        msix_notify(&proxy->pci_dev, vector);
    else
        qemu_set_irq(proxy->pci_dev.irq[0], proxy->vdev->isr & 1);
}

static void virtio_pci_save_config(void * opaque, QEMUFile *f)
{
    VirtIOPCIProxy *proxy = opaque;
    pci_device_save(&proxy->pci_dev, f);
    msix_save(&proxy->pci_dev, f);
    if (msix_present(&proxy->pci_dev))
        qemu_put_be16(f, proxy->vdev->config_vector);
}

static void virtio_pci_save_queue(void * opaque, int n, QEMUFile *f)
{
    VirtIOPCIProxy *proxy = opaque;
    if (msix_present(&proxy->pci_dev))
        qemu_put_be16(f, virtio_queue_vector(proxy->vdev, n));
}

static int virtio_pci_load_config(void * opaque, QEMUFile *f)
{
    VirtIOPCIProxy *proxy = opaque;
    int ret;
    ret = pci_device_load(&proxy->pci_dev, f);
    if (ret) {
        return ret;
    }
    msix_load(&proxy->pci_dev, f);
    if (msix_present(&proxy->pci_dev)) {
        qemu_get_be16s(f, &proxy->vdev->config_vector);
    } else {
        proxy->vdev->config_vector = VIRTIO_NO_VECTOR;
    }
    if (proxy->vdev->config_vector != VIRTIO_NO_VECTOR) {
        return msix_vector_use(&proxy->pci_dev, proxy->vdev->config_vector);
    }
    return 0;
}

static int virtio_pci_load_queue(void * opaque, int n, QEMUFile *f)
{
    VirtIOPCIProxy *proxy = opaque;
    uint16_t vector;
    if (msix_present(&proxy->pci_dev)) {
        qemu_get_be16s(f, &vector);
    } else {
        vector = VIRTIO_NO_VECTOR;
    }
    virtio_queue_set_vector(proxy->vdev, n, vector);
    if (vector != VIRTIO_NO_VECTOR) {
        return msix_vector_use(&proxy->pci_dev, vector);
    }
    return 0;
}

static void virtio_pci_reset(DeviceState *d)
{
    VirtIOPCIProxy *proxy = container_of(d, VirtIOPCIProxy, pci_dev.qdev);
    virtio_reset(proxy->vdev);
    msix_reset(&proxy->pci_dev);
}

static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val)
{
    VirtIOPCIProxy *proxy = opaque;
    VirtIODevice *vdev = proxy->vdev;
    target_phys_addr_t pa;

    switch (addr) {
    case VIRTIO_PCI_GUEST_FEATURES:
	/* Guest does not negotiate properly?  We have to assume nothing. */
	if (val & (1 << VIRTIO_F_BAD_FEATURE)) {
	    if (vdev->bad_features)
		val = vdev->bad_features(vdev);
	    else
		val = 0;
	}
        if (vdev->set_features)
            vdev->set_features(vdev, val);
        vdev->features = val;
        break;
    case VIRTIO_PCI_QUEUE_PFN:
        pa = (target_phys_addr_t)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
        if (pa == 0)
            virtio_pci_reset(&proxy->pci_dev.qdev);
        else
            virtio_queue_set_addr(vdev, vdev->queue_sel, pa);
        break;
    case VIRTIO_PCI_QUEUE_SEL:
        if (val < VIRTIO_PCI_QUEUE_MAX)
            vdev->queue_sel = val;
        break;
    case VIRTIO_PCI_QUEUE_NOTIFY:
        virtio_queue_notify(vdev, val);
        break;
    case VIRTIO_PCI_STATUS:
        vdev->status = val & 0xFF;
        if (vdev->status == 0)
            virtio_pci_reset(&proxy->pci_dev.qdev);
        break;
    case VIRTIO_MSI_CONFIG_VECTOR:
        msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
        /* Make it possible for guest to discover an error took place. */
        if (msix_vector_use(&proxy->pci_dev, val) < 0)
            val = VIRTIO_NO_VECTOR;
        vdev->config_vector = val;
        break;
    case VIRTIO_MSI_QUEUE_VECTOR:
        msix_vector_unuse(&proxy->pci_dev,
                          virtio_queue_vector(vdev, vdev->queue_sel));
        /* Make it possible for guest to discover an error took place. */
        if (msix_vector_use(&proxy->pci_dev, val) < 0)
            val = VIRTIO_NO_VECTOR;
        virtio_queue_set_vector(vdev, vdev->queue_sel, val);
        break;
    default:
        fprintf(stderr, "%s: unexpected address 0x%x value 0x%x\n",
                __func__, addr, val);
        break;
    }
}

static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr)
{
    VirtIODevice *vdev = proxy->vdev;
    uint32_t ret = 0xFFFFFFFF;

    switch (addr) {
    case VIRTIO_PCI_HOST_FEATURES:
        ret = vdev->get_features(vdev);
        ret |= (1 << VIRTIO_F_NOTIFY_ON_EMPTY);
        ret |= (1 << VIRTIO_RING_F_INDIRECT_DESC);
        ret |= (1 << VIRTIO_F_BAD_FEATURE);
        break;
    case VIRTIO_PCI_GUEST_FEATURES:
        ret = vdev->features;
        break;
    case VIRTIO_PCI_QUEUE_PFN:
        ret = virtio_queue_get_addr(vdev, vdev->queue_sel)
              >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
        break;
    case VIRTIO_PCI_QUEUE_NUM:
        ret = virtio_queue_get_num(vdev, vdev->queue_sel);
        break;
    case VIRTIO_PCI_QUEUE_SEL:
        ret = vdev->queue_sel;
        break;
    case VIRTIO_PCI_STATUS:
        ret = vdev->status;
        break;
    case VIRTIO_PCI_ISR:
        /* reading from the ISR also clears it. */
        ret = vdev->isr;
        vdev->isr = 0;
        qemu_set_irq(proxy->pci_dev.irq[0], 0);
        break;
    case VIRTIO_MSI_CONFIG_VECTOR:
        ret = vdev->config_vector;
        break;
    case VIRTIO_MSI_QUEUE_VECTOR:
        ret = virtio_queue_vector(vdev, vdev->queue_sel);
        break;
    default:
        break;
    }

    return ret;
}

static uint32_t virtio_pci_config_readb(void *opaque, uint32_t addr)
{
    VirtIOPCIProxy *proxy = opaque;
    uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
    addr -= proxy->addr;
    if (addr < config)
        return virtio_ioport_read(proxy, addr);
    addr -= config;
    return virtio_config_readb(proxy->vdev, addr);
}

static uint32_t virtio_pci_config_readw(void *opaque, uint32_t addr)
{
    VirtIOPCIProxy *proxy = opaque;
    uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
    addr -= proxy->addr;
    if (addr < config)
        return virtio_ioport_read(proxy, addr);
    addr -= config;
    return virtio_config_readw(proxy->vdev, addr);
}

static uint32_t virtio_pci_config_readl(void *opaque, uint32_t addr)
{
    VirtIOPCIProxy *proxy = opaque;
    uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
    addr -= proxy->addr;
    if (addr < config)
        return virtio_ioport_read(proxy, addr);
    addr -= config;
    return virtio_config_readl(proxy->vdev, addr);
}

static void virtio_pci_config_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    VirtIOPCIProxy *proxy = opaque;
    uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
    addr -= proxy->addr;
    if (addr < config) {
        virtio_ioport_write(proxy, addr, val);
        return;
    }
    addr -= config;
    virtio_config_writeb(proxy->vdev, addr, val);
}

static void virtio_pci_config_writew(void *opaque, uint32_t addr, uint32_t val)
{
    VirtIOPCIProxy *proxy = opaque;
    uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
    addr -= proxy->addr;
    if (addr < config) {
        virtio_ioport_write(proxy, addr, val);
        return;
    }
    addr -= config;
    virtio_config_writew(proxy->vdev, addr, val);
}

static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val)
{
    VirtIOPCIProxy *proxy = opaque;
    uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
    addr -= proxy->addr;
    if (addr < config) {
        virtio_ioport_write(proxy, addr, val);
        return;
    }
    addr -= config;
    virtio_config_writel(proxy->vdev, addr, val);
}

static void virtio_map(PCIDevice *pci_dev, int region_num,
                       uint32_t addr, uint32_t size, int type)
{
    VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev);
    VirtIODevice *vdev = proxy->vdev;
    unsigned config_len = VIRTIO_PCI_REGION_SIZE(pci_dev) + vdev->config_len;

    proxy->addr = addr;

    register_ioport_write(addr, config_len, 1, virtio_pci_config_writeb, proxy);
    register_ioport_write(addr, config_len, 2, virtio_pci_config_writew, proxy);
    register_ioport_write(addr, config_len, 4, virtio_pci_config_writel, proxy);
    register_ioport_read(addr, config_len, 1, virtio_pci_config_readb, proxy);
    register_ioport_read(addr, config_len, 2, virtio_pci_config_readw, proxy);
    register_ioport_read(addr, config_len, 4, virtio_pci_config_readl, proxy);

    if (vdev->config_len)
        vdev->get_config(vdev, vdev->config);
}

static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
                                uint32_t val, int len)
{
    VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);

    if (PCI_COMMAND == address) {
        if (!(val & PCI_COMMAND_MASTER)) {
            proxy->vdev->status &= !VIRTIO_CONFIG_S_DRIVER_OK;
        }
    }

    pci_default_write_config(pci_dev, address, val, len);
    msix_write_config(pci_dev, address, val, len);
}

static const VirtIOBindings virtio_pci_bindings = {
    .notify = virtio_pci_notify,
    .save_config = virtio_pci_save_config,
    .load_config = virtio_pci_load_config,
    .save_queue = virtio_pci_save_queue,
    .load_queue = virtio_pci_load_queue,
};

static void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev,
                            uint16_t vendor, uint16_t device,
                            uint16_t class_code, uint8_t pif)
{
    uint8_t *config;
    uint32_t size;

    proxy->vdev = vdev;

    config = proxy->pci_dev.config;
    pci_config_set_vendor_id(config, vendor);
    pci_config_set_device_id(config, device);

    config[0x08] = VIRTIO_PCI_ABI_VERSION;

    config[0x09] = pif;
    pci_config_set_class(config, class_code);
    config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;

    config[0x2c] = vendor & 0xFF;
    config[0x2d] = (vendor >> 8) & 0xFF;
    config[0x2e] = vdev->device_id & 0xFF;
    config[0x2f] = (vdev->device_id >> 8) & 0xFF;

    config[0x3d] = 1;

    if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0)) {
        pci_register_bar(&proxy->pci_dev, 1,
                         msix_bar_size(&proxy->pci_dev),
                         PCI_BASE_ADDRESS_SPACE_MEMORY,
                         msix_mmio_map);
    } else
        vdev->nvectors = 0;

    proxy->pci_dev.config_write = virtio_write_config;

    size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev) + vdev->config_len;
    if (size & (size-1))
        size = 1 << qemu_fls(size);

    pci_register_bar(&proxy->pci_dev, 0, size, PCI_BASE_ADDRESS_SPACE_IO,
                           virtio_map);

    virtio_bind_device(vdev, &virtio_pci_bindings, proxy);
}

static int virtio_blk_init_pci(PCIDevice *pci_dev)
{
    VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
    VirtIODevice *vdev;

    if (proxy->class_code != PCI_CLASS_STORAGE_SCSI &&
        proxy->class_code != PCI_CLASS_STORAGE_OTHER)
        proxy->class_code = PCI_CLASS_STORAGE_SCSI;

    if (!proxy->dinfo) {
        qemu_error("virtio-blk-pci: drive property not set\n");
        return -1;
    }
    vdev = virtio_blk_init(&pci_dev->qdev, proxy->dinfo);
    vdev->nvectors = proxy->nvectors;
    virtio_init_pci(proxy, vdev,
                    PCI_VENDOR_ID_REDHAT_QUMRANET,
                    PCI_DEVICE_ID_VIRTIO_BLOCK,
                    proxy->class_code, 0x00);
    /* make the actual value visible */
    proxy->nvectors = vdev->nvectors;
    return 0;
}

static int virtio_exit_pci(PCIDevice *pci_dev)
{
    return msix_uninit(pci_dev);
}

static int virtio_blk_exit_pci(PCIDevice *pci_dev)
{
    VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);

    drive_uninit(proxy->dinfo);
    return virtio_exit_pci(pci_dev);
}

static int virtio_console_init_pci(PCIDevice *pci_dev)
{
    VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
    VirtIODevice *vdev;

    if (proxy->class_code != PCI_CLASS_COMMUNICATION_OTHER &&
        proxy->class_code != PCI_CLASS_DISPLAY_OTHER && /* qemu 0.10 */
        proxy->class_code != PCI_CLASS_OTHERS)          /* qemu-kvm  */
        proxy->class_code = PCI_CLASS_COMMUNICATION_OTHER;

    vdev = virtio_console_init(&pci_dev->qdev);
    if (!vdev) {
        return -1;
    }
    virtio_init_pci(proxy, vdev,
                    PCI_VENDOR_ID_REDHAT_QUMRANET,
                    PCI_DEVICE_ID_VIRTIO_CONSOLE,
                    proxy->class_code, 0x00);
    return 0;
}

static int virtio_net_init_pci(PCIDevice *pci_dev)
{
    VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
    VirtIODevice *vdev;

    vdev = virtio_net_init(&pci_dev->qdev, &proxy->nic);

    vdev->nvectors = proxy->nvectors;
    virtio_init_pci(proxy, vdev,
                    PCI_VENDOR_ID_REDHAT_QUMRANET,
                    PCI_DEVICE_ID_VIRTIO_NET,
                    PCI_CLASS_NETWORK_ETHERNET,
                    0x00);

    /* make the actual value visible */
    proxy->nvectors = vdev->nvectors;

    if (!pci_dev->qdev.hotplugged) {
        static int loaded = 0;
        if (!loaded) {
            rom_add_option("pxe-virtio.bin");
            loaded = 1;
        }
    }
    return 0;
}

static int virtio_net_exit_pci(PCIDevice *pci_dev)
{
    VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);

    virtio_net_exit(proxy->vdev);
    return virtio_exit_pci(pci_dev);
}

static int virtio_balloon_init_pci(PCIDevice *pci_dev)
{
    VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
    VirtIODevice *vdev;

    vdev = virtio_balloon_init(&pci_dev->qdev);
    virtio_init_pci(proxy, vdev,
                    PCI_VENDOR_ID_REDHAT_QUMRANET,
                    PCI_DEVICE_ID_VIRTIO_BALLOON,
                    PCI_CLASS_MEMORY_RAM,
                    0x00);
    return 0;
}

static PCIDeviceInfo virtio_info[] = {
    {
        .qdev.name = "virtio-blk-pci",
        .qdev.size = sizeof(VirtIOPCIProxy),
        .init      = virtio_blk_init_pci,
        .exit      = virtio_blk_exit_pci,
        .qdev.props = (Property[]) {
            DEFINE_PROP_HEX32("class", VirtIOPCIProxy, class_code, 0),
            DEFINE_PROP_DRIVE("drive", VirtIOPCIProxy, dinfo),
            DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
            DEFINE_PROP_END_OF_LIST(),
        },
        .qdev.reset = virtio_pci_reset,
    },{
        .qdev.name  = "virtio-net-pci",
        .qdev.size  = sizeof(VirtIOPCIProxy),
        .init       = virtio_net_init_pci,
        .exit       = virtio_net_exit_pci,
        .qdev.props = (Property[]) {
            DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3),
            DEFINE_NIC_PROPERTIES(VirtIOPCIProxy, nic),
            DEFINE_PROP_END_OF_LIST(),
        },
        .qdev.reset = virtio_pci_reset,
    },{
        .qdev.name = "virtio-console-pci",
        .qdev.size = sizeof(VirtIOPCIProxy),
        .init      = virtio_console_init_pci,
        .exit      = virtio_exit_pci,
        .qdev.props = (Property[]) {
            DEFINE_PROP_HEX32("class", VirtIOPCIProxy, class_code, 0),
            DEFINE_PROP_END_OF_LIST(),
        },
        .qdev.reset = virtio_pci_reset,
    },{
        .qdev.name = "virtio-balloon-pci",
        .qdev.size = sizeof(VirtIOPCIProxy),
        .init      = virtio_balloon_init_pci,
        .exit      = virtio_exit_pci,
        .qdev.reset = virtio_pci_reset,
    },{
        /* end of list */
    }
};

static void virtio_pci_register_devices(void)
{
    pci_qdev_register_many(virtio_info);
}

device_init(virtio_pci_register_devices)
Commit	Line	Data
53c25cea PB	1	/*
	2	* Virtio PCI Bindings
	3	*
	4	* Copyright IBM, Corp. 2007
	5	* Copyright (c) 2009 CodeSourcery
	6	*
	7	* Authors:
	8	* Anthony Liguori <aliguori@us.ibm.com>
	9	* Paul Brook <paul@codesourcery.com>
	10	*
	11	* This work is licensed under the terms of the GNU GPL, version 2. See
	12	* the COPYING file in the top-level directory.
	13	*
	14	*/
	15
	16	#include <inttypes.h>
	17
	18	#include "virtio.h"
	19	#include "pci.h"
d176c495	20	#include "sysemu.h"
aba800a3	21	#include "msix.h"
a1e0fea5	22	#include "net.h"
97b15621	23	#include "loader.h"
53c25cea PB	24
	25	/* from Linux's linux/virtio_pci.h */
	26
	27	/* A 32-bit r/o bitmask of the features supported by the host */
	28	#define VIRTIO_PCI_HOST_FEATURES 0
	29
	30	/* A 32-bit r/w bitmask of features activated by the guest */
	31	#define VIRTIO_PCI_GUEST_FEATURES 4
	32
	33	/* A 32-bit r/w PFN for the currently selected queue */
	34	#define VIRTIO_PCI_QUEUE_PFN 8
	35
	36	/* A 16-bit r/o queue size for the currently selected queue */
	37	#define VIRTIO_PCI_QUEUE_NUM 12
	38
	39	/* A 16-bit r/w queue selector */
	40	#define VIRTIO_PCI_QUEUE_SEL 14
	41
	42	/* A 16-bit r/w queue notifier */
	43	#define VIRTIO_PCI_QUEUE_NOTIFY 16
	44
	45	/* An 8-bit device status register. */
	46	#define VIRTIO_PCI_STATUS 18
	47
	48	/* An 8-bit r/o interrupt status register. Reading the value will return the
	49	* current contents of the ISR and will also clear it. This is effectively
	50	* a read-and-acknowledge. */
	51	#define VIRTIO_PCI_ISR 19
	52
aba800a3 MT	53	/* MSI-X registers: only enabled if MSI-X is enabled. */
	54	/* A 16-bit vector for configuration changes. */
	55	#define VIRTIO_MSI_CONFIG_VECTOR 20
	56	/* A 16-bit vector for selected queue notifications. */
	57	#define VIRTIO_MSI_QUEUE_VECTOR 22
	58
	59	/* Config space size */
	60	#define VIRTIO_PCI_CONFIG_NOMSI 20
	61	#define VIRTIO_PCI_CONFIG_MSI 24
	62	#define VIRTIO_PCI_REGION_SIZE(dev) (msix_present(dev) ? \
	63	VIRTIO_PCI_CONFIG_MSI : \
	64	VIRTIO_PCI_CONFIG_NOMSI)
	65
	66	/* The remaining space is defined by each driver as the per-driver
	67	* configuration space */
	68	#define VIRTIO_PCI_CONFIG(dev) (msix_enabled(dev) ? \
	69	VIRTIO_PCI_CONFIG_MSI : \
	70	VIRTIO_PCI_CONFIG_NOMSI)
53c25cea PB	71
	72	/* Virtio ABI version, if we increment this, we break the guest driver. */
	73	#define VIRTIO_PCI_ABI_VERSION 0
	74
	75	/* How many bits to shift physical queue address written to QUEUE_PFN.
	76	* 12 is historical, and due to x86 page size. */
	77	#define VIRTIO_PCI_QUEUE_ADDR_SHIFT 12
	78
	79	/* QEMU doesn't strictly need write barriers since everything runs in
	80	* lock-step. We'll leave the calls to wmb() in though to make it obvious for
	81	* KVM or if kqemu gets SMP support.
	82	*/
	83	#define wmb() do { } while (0)
	84
	85	/* PCI bindings. */
	86
	87	typedef struct {
	88	PCIDevice pci_dev;
	89	VirtIODevice *vdev;
	90	uint32_t addr;
ab73ff29	91	uint32_t class_code;
a1e0fea5	92	uint32_t nvectors;
d176c495	93	DriveInfo *dinfo;
97b15621	94	NICConf nic;
53c25cea PB	95	} VirtIOPCIProxy;
	96
	97	/* virtio device */
	98
7055e687	99	static void virtio_pci_notify(void *opaque, uint16_t vector)
53c25cea PB	100	{
53c25cea PB	101	VirtIOPCIProxy *proxy = opaque;
aba800a3 MT	102	if (msix_enabled(&proxy->pci_dev))
	103	msix_notify(&proxy->pci_dev, vector);
	104	else
	105	qemu_set_irq(proxy->pci_dev.irq[0], proxy->vdev->isr & 1);
53c25cea PB	106	}
53c25cea PB	107
ff24bd58 MT	108	static void virtio_pci_save_config(void * opaque, QEMUFile *f)
	109	{
	110	VirtIOPCIProxy *proxy = opaque;
	111	pci_device_save(&proxy->pci_dev, f);
	112	msix_save(&proxy->pci_dev, f);
	113	if (msix_present(&proxy->pci_dev))
	114	qemu_put_be16(f, proxy->vdev->config_vector);
	115	}
	116
	117	static void virtio_pci_save_queue(void * opaque, int n, QEMUFile *f)
	118	{
	119	VirtIOPCIProxy *proxy = opaque;
	120	if (msix_present(&proxy->pci_dev))
	121	qemu_put_be16(f, virtio_queue_vector(proxy->vdev, n));
	122	}
	123
	124	static int virtio_pci_load_config(void * opaque, QEMUFile *f)
	125	{
	126	VirtIOPCIProxy *proxy = opaque;
	127	int ret;
	128	ret = pci_device_load(&proxy->pci_dev, f);
e6da7680	129	if (ret) {
ff24bd58	130	return ret;
e6da7680	131	}
ff24bd58	132	msix_load(&proxy->pci_dev, f);
e6da7680	133	if (msix_present(&proxy->pci_dev)) {
ff24bd58	134	qemu_get_be16s(f, &proxy->vdev->config_vector);
e6da7680 MT	135	} else {
	136	proxy->vdev->config_vector = VIRTIO_NO_VECTOR;
	137	}
	138	if (proxy->vdev->config_vector != VIRTIO_NO_VECTOR) {
	139	return msix_vector_use(&proxy->pci_dev, proxy->vdev->config_vector);
	140	}
ff24bd58 MT	141	return 0;
	142	}
	143
	144	static int virtio_pci_load_queue(void * opaque, int n, QEMUFile *f)
	145	{
	146	VirtIOPCIProxy *proxy = opaque;
	147	uint16_t vector;
e6da7680 MT	148	if (msix_present(&proxy->pci_dev)) {
	149	qemu_get_be16s(f, &vector);
	150	} else {
	151	vector = VIRTIO_NO_VECTOR;
	152	}
ff24bd58	153	virtio_queue_set_vector(proxy->vdev, n, vector);
e6da7680 MT	154	if (vector != VIRTIO_NO_VECTOR) {
	155	return msix_vector_use(&proxy->pci_dev, vector);
	156	}
ff24bd58 MT	157	return 0;
	158	}
	159
e489030d	160	static void virtio_pci_reset(DeviceState *d)
7055e687	161	{
e489030d	162	VirtIOPCIProxy *proxy = container_of(d, VirtIOPCIProxy, pci_dev.qdev);
7055e687	163	virtio_reset(proxy->vdev);
aba800a3	164	msix_reset(&proxy->pci_dev);
7055e687 MT	165	}
7055e687 MT	166
53c25cea PB	167	static void virtio_ioport_write(void *opaque, uint32_t addr, uint32_t val)
	168	{
	169	VirtIOPCIProxy *proxy = opaque;
	170	VirtIODevice *vdev = proxy->vdev;
c227f099	171	target_phys_addr_t pa;
53c25cea	172
53c25cea PB	173	switch (addr) {
	174	case VIRTIO_PCI_GUEST_FEATURES:
	175	/* Guest does not negotiate properly? We have to assume nothing. */
	176	if (val & (1 << VIRTIO_F_BAD_FEATURE)) {
	177	if (vdev->bad_features)
	178	val = vdev->bad_features(vdev);
	179	else
	180	val = 0;
	181	}
	182	if (vdev->set_features)
	183	vdev->set_features(vdev, val);
	184	vdev->features = val;
	185	break;
	186	case VIRTIO_PCI_QUEUE_PFN:
c227f099	187	pa = (target_phys_addr_t)val << VIRTIO_PCI_QUEUE_ADDR_SHIFT;
7055e687	188	if (pa == 0)
e489030d	189	virtio_pci_reset(&proxy->pci_dev.qdev);
7055e687 MT	190	else
7055e687 MT	191	virtio_queue_set_addr(vdev, vdev->queue_sel, pa);
53c25cea PB	192	break;
	193	case VIRTIO_PCI_QUEUE_SEL:
	194	if (val < VIRTIO_PCI_QUEUE_MAX)
	195	vdev->queue_sel = val;
	196	break;
	197	case VIRTIO_PCI_QUEUE_NOTIFY:
	198	virtio_queue_notify(vdev, val);
	199	break;
	200	case VIRTIO_PCI_STATUS:
	201	vdev->status = val & 0xFF;
	202	if (vdev->status == 0)
e489030d	203	virtio_pci_reset(&proxy->pci_dev.qdev);
53c25cea	204	break;
aba800a3 MT	205	case VIRTIO_MSI_CONFIG_VECTOR:
	206	msix_vector_unuse(&proxy->pci_dev, vdev->config_vector);
	207	/* Make it possible for guest to discover an error took place. */
	208	if (msix_vector_use(&proxy->pci_dev, val) < 0)
	209	val = VIRTIO_NO_VECTOR;
	210	vdev->config_vector = val;
	211	break;
	212	case VIRTIO_MSI_QUEUE_VECTOR:
	213	msix_vector_unuse(&proxy->pci_dev,
	214	virtio_queue_vector(vdev, vdev->queue_sel));
	215	/* Make it possible for guest to discover an error took place. */
	216	if (msix_vector_use(&proxy->pci_dev, val) < 0)
	217	val = VIRTIO_NO_VECTOR;
	218	virtio_queue_set_vector(vdev, vdev->queue_sel, val);
	219	break;
	220	default:
	221	fprintf(stderr, "%s: unexpected address 0x%x value 0x%x\n",
	222	__func__, addr, val);
	223	break;
53c25cea PB	224	}
	225	}
	226
aba800a3	227	static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr)
53c25cea	228	{
53c25cea PB	229	VirtIODevice *vdev = proxy->vdev;
	230	uint32_t ret = 0xFFFFFFFF;
	231
53c25cea PB	232	switch (addr) {
	233	case VIRTIO_PCI_HOST_FEATURES:
	234	ret = vdev->get_features(vdev);
efeea6d0 MM	235	ret \|= (1 << VIRTIO_F_NOTIFY_ON_EMPTY);
	236	ret \|= (1 << VIRTIO_RING_F_INDIRECT_DESC);
	237	ret \|= (1 << VIRTIO_F_BAD_FEATURE);
53c25cea PB	238	break;
	239	case VIRTIO_PCI_GUEST_FEATURES:
	240	ret = vdev->features;
	241	break;
	242	case VIRTIO_PCI_QUEUE_PFN:
	243	ret = virtio_queue_get_addr(vdev, vdev->queue_sel)
	244	>> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
	245	break;
	246	case VIRTIO_PCI_QUEUE_NUM:
	247	ret = virtio_queue_get_num(vdev, vdev->queue_sel);
	248	break;
	249	case VIRTIO_PCI_QUEUE_SEL:
	250	ret = vdev->queue_sel;
	251	break;
	252	case VIRTIO_PCI_STATUS:
	253	ret = vdev->status;
	254	break;
	255	case VIRTIO_PCI_ISR:
	256	/* reading from the ISR also clears it. */
	257	ret = vdev->isr;
	258	vdev->isr = 0;
7055e687	259	qemu_set_irq(proxy->pci_dev.irq[0], 0);
53c25cea	260	break;
aba800a3 MT	261	case VIRTIO_MSI_CONFIG_VECTOR:
	262	ret = vdev->config_vector;
	263	break;
	264	case VIRTIO_MSI_QUEUE_VECTOR:
	265	ret = virtio_queue_vector(vdev, vdev->queue_sel);
	266	break;
53c25cea PB	267	default:
	268	break;
	269	}
	270
	271	return ret;
	272	}
	273
	274	static uint32_t virtio_pci_config_readb(void *opaque, uint32_t addr)
	275	{
	276	VirtIOPCIProxy *proxy = opaque;
aba800a3 MT	277	uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
	278	addr -= proxy->addr;
	279	if (addr < config)
	280	return virtio_ioport_read(proxy, addr);
	281	addr -= config;
53c25cea PB	282	return virtio_config_readb(proxy->vdev, addr);
	283	}
	284
	285	static uint32_t virtio_pci_config_readw(void *opaque, uint32_t addr)
	286	{
	287	VirtIOPCIProxy *proxy = opaque;
aba800a3 MT	288	uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
	289	addr -= proxy->addr;
	290	if (addr < config)
	291	return virtio_ioport_read(proxy, addr);
	292	addr -= config;
53c25cea PB	293	return virtio_config_readw(proxy->vdev, addr);
	294	}
	295
	296	static uint32_t virtio_pci_config_readl(void *opaque, uint32_t addr)
	297	{
	298	VirtIOPCIProxy *proxy = opaque;
aba800a3 MT	299	uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
	300	addr -= proxy->addr;
	301	if (addr < config)
	302	return virtio_ioport_read(proxy, addr);
	303	addr -= config;
53c25cea PB	304	return virtio_config_readl(proxy->vdev, addr);
	305	}
	306
	307	static void virtio_pci_config_writeb(void *opaque, uint32_t addr, uint32_t val)
	308	{
	309	VirtIOPCIProxy *proxy = opaque;
aba800a3 MT	310	uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
	311	addr -= proxy->addr;
	312	if (addr < config) {
	313	virtio_ioport_write(proxy, addr, val);
	314	return;
	315	}
	316	addr -= config;
53c25cea PB	317	virtio_config_writeb(proxy->vdev, addr, val);
	318	}
	319
	320	static void virtio_pci_config_writew(void *opaque, uint32_t addr, uint32_t val)
	321	{
	322	VirtIOPCIProxy *proxy = opaque;
aba800a3 MT	323	uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
	324	addr -= proxy->addr;
	325	if (addr < config) {
	326	virtio_ioport_write(proxy, addr, val);
	327	return;
	328	}
	329	addr -= config;
53c25cea PB	330	virtio_config_writew(proxy->vdev, addr, val);
	331	}
	332
	333	static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val)
	334	{
	335	VirtIOPCIProxy *proxy = opaque;
aba800a3 MT	336	uint32_t config = VIRTIO_PCI_CONFIG(&proxy->pci_dev);
	337	addr -= proxy->addr;
	338	if (addr < config) {
	339	virtio_ioport_write(proxy, addr, val);
	340	return;
	341	}
	342	addr -= config;
53c25cea PB	343	virtio_config_writel(proxy->vdev, addr, val);
	344	}
	345
	346	static void virtio_map(PCIDevice *pci_dev, int region_num,
	347	uint32_t addr, uint32_t size, int type)
	348	{
	349	VirtIOPCIProxy *proxy = container_of(pci_dev, VirtIOPCIProxy, pci_dev);
	350	VirtIODevice *vdev = proxy->vdev;
aba800a3	351	unsigned config_len = VIRTIO_PCI_REGION_SIZE(pci_dev) + vdev->config_len;
53c25cea PB	352
53c25cea PB	353	proxy->addr = addr;
53c25cea	354
aba800a3 MT	355	register_ioport_write(addr, config_len, 1, virtio_pci_config_writeb, proxy);
	356	register_ioport_write(addr, config_len, 2, virtio_pci_config_writew, proxy);
	357	register_ioport_write(addr, config_len, 4, virtio_pci_config_writel, proxy);
	358	register_ioport_read(addr, config_len, 1, virtio_pci_config_readb, proxy);
	359	register_ioport_read(addr, config_len, 2, virtio_pci_config_readw, proxy);
	360	register_ioport_read(addr, config_len, 4, virtio_pci_config_readl, proxy);
53c25cea	361
aba800a3	362	if (vdev->config_len)
53c25cea	363	vdev->get_config(vdev, vdev->config);
aba800a3 MT	364	}
	365
	366	static void virtio_write_config(PCIDevice *pci_dev, uint32_t address,
	367	uint32_t val, int len)
	368	{
ed757e14 YV	369	VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
	370
	371	if (PCI_COMMAND == address) {
	372	if (!(val & PCI_COMMAND_MASTER)) {
	373	proxy->vdev->status &= !VIRTIO_CONFIG_S_DRIVER_OK;
	374	}
	375	}
	376
aba800a3	377	pci_default_write_config(pci_dev, address, val, len);
85352471	378	msix_write_config(pci_dev, address, val, len);
53c25cea PB	379	}
	380
	381	static const VirtIOBindings virtio_pci_bindings = {
ff24bd58 MT	382	.notify = virtio_pci_notify,
	383	.save_config = virtio_pci_save_config,
	384	.load_config = virtio_pci_load_config,
	385	.save_queue = virtio_pci_save_queue,
	386	.load_queue = virtio_pci_load_queue,
53c25cea PB	387	};
	388
	389	static void virtio_init_pci(VirtIOPCIProxy proxy, VirtIODevice vdev,
	390	uint16_t vendor, uint16_t device,
	391	uint16_t class_code, uint8_t pif)
	392	{
	393	uint8_t *config;
	394	uint32_t size;
	395
	396	proxy->vdev = vdev;
	397
	398	config = proxy->pci_dev.config;
	399	pci_config_set_vendor_id(config, vendor);
	400	pci_config_set_device_id(config, device);
	401
	402	config[0x08] = VIRTIO_PCI_ABI_VERSION;
	403
	404	config[0x09] = pif;
	405	pci_config_set_class(config, class_code);
	406	config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
	407
	408	config[0x2c] = vendor & 0xFF;
	409	config[0x2d] = (vendor >> 8) & 0xFF;
	410	config[0x2e] = vdev->device_id & 0xFF;
	411	config[0x2f] = (vdev->device_id >> 8) & 0xFF;
	412
	413	config[0x3d] = 1;
	414
5a1fc5e8	415	if (vdev->nvectors && !msix_init(&proxy->pci_dev, vdev->nvectors, 1, 0)) {
aba800a3 MT	416	pci_register_bar(&proxy->pci_dev, 1,
aba800a3 MT	417	msix_bar_size(&proxy->pci_dev),
0392a017	418	PCI_BASE_ADDRESS_SPACE_MEMORY,
aba800a3	419	msix_mmio_map);
aba800a3 MT	420	} else
	421	vdev->nvectors = 0;
	422
ed757e14 YV	423	proxy->pci_dev.config_write = virtio_write_config;
ed757e14 YV	424
aba800a3	425	size = VIRTIO_PCI_REGION_SIZE(&proxy->pci_dev) + vdev->config_len;
53c25cea PB	426	if (size & (size-1))
	427	size = 1 << qemu_fls(size);
	428
0392a017	429	pci_register_bar(&proxy->pci_dev, 0, size, PCI_BASE_ADDRESS_SPACE_IO,
53c25cea PB	430	virtio_map);
	431
	432	virtio_bind_device(vdev, &virtio_pci_bindings, proxy);
	433	}
	434
81a322d4	435	static int virtio_blk_init_pci(PCIDevice *pci_dev)
53c25cea PB	436	{
	437	VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
	438	VirtIODevice *vdev;
	439
ab73ff29 GH	440	if (proxy->class_code != PCI_CLASS_STORAGE_SCSI &&
	441	proxy->class_code != PCI_CLASS_STORAGE_OTHER)
	442	proxy->class_code = PCI_CLASS_STORAGE_SCSI;
53c25cea	443
d176c495	444	if (!proxy->dinfo) {
84fc5589	445	qemu_error("virtio-blk-pci: drive property not set\n");
81a322d4	446	return -1;
d176c495 GH	447	}
d176c495 GH	448	vdev = virtio_blk_init(&pci_dev->qdev, proxy->dinfo);
177539e0	449	vdev->nvectors = proxy->nvectors;
53c25cea PB	450	virtio_init_pci(proxy, vdev,
53c25cea PB	451	PCI_VENDOR_ID_REDHAT_QUMRANET,
85c2c735 MM	452	PCI_DEVICE_ID_VIRTIO_BLOCK,
85c2c735 MM	453	proxy->class_code, 0x00);
177539e0 GH	454	/* make the actual value visible */
177539e0 GH	455	proxy->nvectors = vdev->nvectors;
81a322d4	456	return 0;
21d58b57 MM	457	}
21d58b57 MM	458
0f457d91 MT	459	static int virtio_exit_pci(PCIDevice *pci_dev)
	460	{
	461	return msix_uninit(pci_dev);
	462	}
	463
56a14938 GH	464	static int virtio_blk_exit_pci(PCIDevice *pci_dev)
	465	{
	466	VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
	467
	468	drive_uninit(proxy->dinfo);
0f457d91	469	return virtio_exit_pci(pci_dev);
56a14938 GH	470	}
56a14938 GH	471
81a322d4	472	static int virtio_console_init_pci(PCIDevice *pci_dev)
21d58b57	473	{
d6beee99	474	VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
85c2c735 MM	475	VirtIODevice *vdev;
85c2c735 MM	476
d6beee99 GH	477	if (proxy->class_code != PCI_CLASS_COMMUNICATION_OTHER &&
	478	proxy->class_code != PCI_CLASS_DISPLAY_OTHER && /* qemu 0.10 */
	479	proxy->class_code != PCI_CLASS_OTHERS) /* qemu-kvm */
	480	proxy->class_code = PCI_CLASS_COMMUNICATION_OTHER;
	481
85c2c735	482	vdev = virtio_console_init(&pci_dev->qdev);
25fe3654 AS	483	if (!vdev) {
	484	return -1;
	485	}
85c2c735 MM	486	virtio_init_pci(proxy, vdev,
	487	PCI_VENDOR_ID_REDHAT_QUMRANET,
	488	PCI_DEVICE_ID_VIRTIO_CONSOLE,
	489	proxy->class_code, 0x00);
81a322d4	490	return 0;
53c25cea PB	491	}
53c25cea PB	492
81a322d4	493	static int virtio_net_init_pci(PCIDevice *pci_dev)
53c25cea PB	494	{
	495	VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
	496	VirtIODevice *vdev;
	497
97b15621	498	vdev = virtio_net_init(&pci_dev->qdev, &proxy->nic);
a1e0fea5	499
97b15621	500	vdev->nvectors = proxy->nvectors;
53c25cea PB	501	virtio_init_pci(proxy, vdev,
	502	PCI_VENDOR_ID_REDHAT_QUMRANET,
	503	PCI_DEVICE_ID_VIRTIO_NET,
	504	PCI_CLASS_NETWORK_ETHERNET,
	505	0x00);
a1e0fea5 GH	506
	507	/* make the actual value visible */
	508	proxy->nvectors = vdev->nvectors;
97b15621 GH	509
	510	if (!pci_dev->qdev.hotplugged) {
	511	static int loaded = 0;
	512	if (!loaded) {
	513	rom_add_option("pxe-virtio.bin");
	514	loaded = 1;
	515	}
	516	}
81a322d4	517	return 0;
53c25cea PB	518	}
53c25cea PB	519
97b15621 GH	520	static int virtio_net_exit_pci(PCIDevice *pci_dev)
	521	{
	522	VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
	523
	524	virtio_net_exit(proxy->vdev);
	525	return virtio_exit_pci(pci_dev);
	526	}
	527
81a322d4	528	static int virtio_balloon_init_pci(PCIDevice *pci_dev)
53c25cea PB	529	{
	530	VirtIOPCIProxy *proxy = DO_UPCAST(VirtIOPCIProxy, pci_dev, pci_dev);
	531	VirtIODevice *vdev;
	532
	533	vdev = virtio_balloon_init(&pci_dev->qdev);
	534	virtio_init_pci(proxy, vdev,
	535	PCI_VENDOR_ID_REDHAT_QUMRANET,
	536	PCI_DEVICE_ID_VIRTIO_BALLOON,
	537	PCI_CLASS_MEMORY_RAM,
	538	0x00);
81a322d4	539	return 0;
53c25cea PB	540	}
53c25cea PB	541
0aab0d3a GH	542	static PCIDeviceInfo virtio_info[] = {
	543	{
	544	.qdev.name = "virtio-blk-pci",
	545	.qdev.size = sizeof(VirtIOPCIProxy),
	546	.init = virtio_blk_init_pci,
56a14938	547	.exit = virtio_blk_exit_pci,
ab73ff29	548	.qdev.props = (Property[]) {
72c61d0b GH	549	DEFINE_PROP_HEX32("class", VirtIOPCIProxy, class_code, 0),
72c61d0b GH	550	DEFINE_PROP_DRIVE("drive", VirtIOPCIProxy, dinfo),
177539e0	551	DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2),
72c61d0b	552	DEFINE_PROP_END_OF_LIST(),
ab73ff29	553	},
e489030d	554	.qdev.reset = virtio_pci_reset,
0aab0d3a	555	},{
a1e0fea5 GH	556	.qdev.name = "virtio-net-pci",
	557	.qdev.size = sizeof(VirtIOPCIProxy),
	558	.init = virtio_net_init_pci,
97b15621	559	.exit = virtio_net_exit_pci,
a1e0fea5	560	.qdev.props = (Property[]) {
97b15621 GH	561	DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3),
97b15621 GH	562	DEFINE_NIC_PROPERTIES(VirtIOPCIProxy, nic),
72c61d0b	563	DEFINE_PROP_END_OF_LIST(),
a1e0fea5	564	},
e489030d	565	.qdev.reset = virtio_pci_reset,
0aab0d3a GH	566	},{
	567	.qdev.name = "virtio-console-pci",
	568	.qdev.size = sizeof(VirtIOPCIProxy),
	569	.init = virtio_console_init_pci,
0f457d91	570	.exit = virtio_exit_pci,
d6beee99	571	.qdev.props = (Property[]) {
72c61d0b GH	572	DEFINE_PROP_HEX32("class", VirtIOPCIProxy, class_code, 0),
72c61d0b GH	573	DEFINE_PROP_END_OF_LIST(),
d6beee99	574	},
e489030d	575	.qdev.reset = virtio_pci_reset,
0aab0d3a GH	576	},{
	577	.qdev.name = "virtio-balloon-pci",
	578	.qdev.size = sizeof(VirtIOPCIProxy),
	579	.init = virtio_balloon_init_pci,
0f457d91	580	.exit = virtio_exit_pci,
e489030d	581	.qdev.reset = virtio_pci_reset,
0aab0d3a GH	582	},{
	583	/* end of list */
	584	}
	585	};
	586
53c25cea PB	587	static void virtio_pci_register_devices(void)
53c25cea PB	588	{
0aab0d3a	589	pci_qdev_register_many(virtio_info);
53c25cea PB	590	}
	591
	592	device_init(virtio_pci_register_devices)