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pci: rename pci_register_bar_region() to pci_register_bar()
[qemu.git] / hw / vmware_vga.c
CommitLineData
d34cab9f
TS		 1/*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
87ecb68b 24#include "hw.h"
b3c3f123 25#include "loader.h"
87ecb68b
PB		 26#include "console.h"
27#include "pci.h"
18e08a55 28#include "vmware_vga.h"
d34cab9f
TS		 29
30#define VERBOSE
d34cab9f
TS		 31#undef DIRECT_VRAM
32#define HW_RECT_ACCEL
33#define HW_FILL_ACCEL
34#define HW_MOUSE_ACCEL
35
d34cab9f 36# include "vga_int.h"
d34cab9f
TS		 37
38struct vmsvga_state_s {
4e12cd94 39 VGACommonState vga;
d34cab9f
TS		 40
41 int width;
42 int height;
43 int invalidated;
44 int depth;
45 int bypp;
46 int enable;
47 int config;
48 struct {
49 int id;
50 int x;
51 int y;
52 int on;
53 } cursor;
54
d34cab9f
TS		 55 int index;
56 int scratch_size;
57 uint32_t *scratch;
58 int new_width;
59 int new_height;
60 uint32_t guest;
61 uint32_t svgaid;
62 uint32_t wred;
63 uint32_t wgreen;
64 uint32_t wblue;
65 int syncing;
66 int fb_size;
67
b1950430 68 MemoryRegion fifo_ram;
f351d050
DA		 69 uint8_t *fifo_ptr;
70 unsigned int fifo_size;
f351d050 71
d34cab9f
TS		 72 union {
73 uint32_t *fifo;
74 struct __attribute__((__packed__)) {
75 uint32_t min;
76 uint32_t max;
77 uint32_t next_cmd;
78 uint32_t stop;
79 /* Add registers here when adding capabilities. */
80 uint32_t fifo[0];
81 } *cmd;
82 };
83
84#define REDRAW_FIFO_LEN 512
85 struct vmsvga_rect_s {
86 int x, y, w, h;
87 } redraw_fifo[REDRAW_FIFO_LEN];
88 int redraw_fifo_first, redraw_fifo_last;
89};
90
91struct pci_vmsvga_state_s {
92 PCIDevice card;
93 struct vmsvga_state_s chip;
b1950430 94 MemoryRegion io_bar;
d34cab9f
TS		 95};
96
97#define SVGA_MAGIC 0x900000UL
98#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
99#define SVGA_ID_0 SVGA_MAKE_ID(0)
100#define SVGA_ID_1 SVGA_MAKE_ID(1)
101#define SVGA_ID_2 SVGA_MAKE_ID(2)
102
103#define SVGA_LEGACY_BASE_PORT 0x4560
104#define SVGA_INDEX_PORT 0x0
105#define SVGA_VALUE_PORT 0x1
106#define SVGA_BIOS_PORT 0x2
107
108#define SVGA_VERSION_2
109
110#ifdef SVGA_VERSION_2
111# define SVGA_ID SVGA_ID_2
112# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
113# define SVGA_IO_MUL 1
114# define SVGA_FIFO_SIZE 0x10000
d34cab9f
TS		 115# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
116#else
117# define SVGA_ID SVGA_ID_1
118# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
119# define SVGA_IO_MUL 4
120# define SVGA_FIFO_SIZE 0x10000
d34cab9f
TS		 121# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
122#endif
123
124enum {
125 /* ID 0, 1 and 2 registers */
126 SVGA_REG_ID = 0,
127 SVGA_REG_ENABLE = 1,
128 SVGA_REG_WIDTH = 2,
129 SVGA_REG_HEIGHT = 3,
130 SVGA_REG_MAX_WIDTH = 4,
131 SVGA_REG_MAX_HEIGHT = 5,
132 SVGA_REG_DEPTH = 6,
133 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
134 SVGA_REG_PSEUDOCOLOR = 8,
135 SVGA_REG_RED_MASK = 9,
136 SVGA_REG_GREEN_MASK = 10,
137 SVGA_REG_BLUE_MASK = 11,
138 SVGA_REG_BYTES_PER_LINE = 12,
139 SVGA_REG_FB_START = 13,
140 SVGA_REG_FB_OFFSET = 14,
141 SVGA_REG_VRAM_SIZE = 15,
142 SVGA_REG_FB_SIZE = 16,
143
144 /* ID 1 and 2 registers */
145 SVGA_REG_CAPABILITIES = 17,
146 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
147 SVGA_REG_MEM_SIZE = 19,
148 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
149 SVGA_REG_SYNC = 21, /* Write to force synchronization */
150 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
151 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
152 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
153 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
154 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
155 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
156 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
157 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
158 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
159 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
160 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
161
162 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
163 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
164 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
165};
166
167#define SVGA_CAP_NONE 0
168#define SVGA_CAP_RECT_FILL (1 << 0)
169#define SVGA_CAP_RECT_COPY (1 << 1)
170#define SVGA_CAP_RECT_PAT_FILL (1 << 2)
171#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
172#define SVGA_CAP_RASTER_OP (1 << 4)
173#define SVGA_CAP_CURSOR (1 << 5)
174#define SVGA_CAP_CURSOR_BYPASS (1 << 6)
175#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
176#define SVGA_CAP_8BIT_EMULATION (1 << 8)
177#define SVGA_CAP_ALPHA_CURSOR (1 << 9)
178#define SVGA_CAP_GLYPH (1 << 10)
179#define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
180#define SVGA_CAP_OFFSCREEN_1 (1 << 12)
181#define SVGA_CAP_ALPHA_BLEND (1 << 13)
182#define SVGA_CAP_3D (1 << 14)
183#define SVGA_CAP_EXTENDED_FIFO (1 << 15)
184#define SVGA_CAP_MULTIMON (1 << 16)
185#define SVGA_CAP_PITCHLOCK (1 << 17)
186
187/*
188 * FIFO offsets (seen as an array of 32-bit words)
189 */
190enum {
191 /*
192 * The original defined FIFO offsets
193 */
194 SVGA_FIFO_MIN = 0,
195 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
196 SVGA_FIFO_NEXT_CMD,
197 SVGA_FIFO_STOP,
198
199 /*
200 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
201 */
202 SVGA_FIFO_CAPABILITIES = 4,
203 SVGA_FIFO_FLAGS,
204 SVGA_FIFO_FENCE,
205 SVGA_FIFO_3D_HWVERSION,
206 SVGA_FIFO_PITCHLOCK,
207};
208
209#define SVGA_FIFO_CAP_NONE 0
210#define SVGA_FIFO_CAP_FENCE (1 << 0)
211#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
212#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
213
214#define SVGA_FIFO_FLAG_NONE 0
215#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
216
217/* These values can probably be changed arbitrarily. */
218#define SVGA_SCRATCH_SIZE 0x8000
219#define SVGA_MAX_WIDTH 2360
220#define SVGA_MAX_HEIGHT 1770
221
222#ifdef VERBOSE
223# define GUEST_OS_BASE 0x5001
224static const char *vmsvga_guest_id[] = {
f707cfba
AZ		 225 [0x00] = "Dos",
226 [0x01] = "Windows 3.1",
227 [0x02] = "Windows 95",
228 [0x03] = "Windows 98",
229 [0x04] = "Windows ME",
230 [0x05] = "Windows NT",
231 [0x06] = "Windows 2000",
232 [0x07] = "Linux",
233 [0x08] = "OS/2",
511d2b14 234 [0x09] = "an unknown OS",
f707cfba
AZ		 235 [0x0a] = "BSD",
236 [0x0b] = "Whistler",
511d2b14
BS		 237 [0x0c] = "an unknown OS",
238 [0x0d] = "an unknown OS",
239 [0x0e] = "an unknown OS",
240 [0x0f] = "an unknown OS",
241 [0x10] = "an unknown OS",
242 [0x11] = "an unknown OS",
243 [0x12] = "an unknown OS",
244 [0x13] = "an unknown OS",
245 [0x14] = "an unknown OS",
f707cfba 246 [0x15] = "Windows 2003",
d34cab9f
TS		 247};
248#endif
249
250enum {
251 SVGA_CMD_INVALID_CMD = 0,
252 SVGA_CMD_UPDATE = 1,
253 SVGA_CMD_RECT_FILL = 2,
254 SVGA_CMD_RECT_COPY = 3,
255 SVGA_CMD_DEFINE_BITMAP = 4,
256 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
257 SVGA_CMD_DEFINE_PIXMAP = 6,
258 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
259 SVGA_CMD_RECT_BITMAP_FILL = 8,
260 SVGA_CMD_RECT_PIXMAP_FILL = 9,
261 SVGA_CMD_RECT_BITMAP_COPY = 10,
262 SVGA_CMD_RECT_PIXMAP_COPY = 11,
263 SVGA_CMD_FREE_OBJECT = 12,
264 SVGA_CMD_RECT_ROP_FILL = 13,
265 SVGA_CMD_RECT_ROP_COPY = 14,
266 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
267 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
268 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
269 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
270 SVGA_CMD_DEFINE_CURSOR = 19,
271 SVGA_CMD_DISPLAY_CURSOR = 20,
272 SVGA_CMD_MOVE_CURSOR = 21,
273 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
274 SVGA_CMD_DRAW_GLYPH = 23,
275 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
276 SVGA_CMD_UPDATE_VERBOSE = 25,
277 SVGA_CMD_SURFACE_FILL = 26,
278 SVGA_CMD_SURFACE_COPY = 27,
279 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
280 SVGA_CMD_FRONT_ROP_FILL = 29,
281 SVGA_CMD_FENCE = 30,
282};
283
284/* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
285enum {
286 SVGA_CURSOR_ON_HIDE = 0,
287 SVGA_CURSOR_ON_SHOW = 1,
288 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
289 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
290};
291
292static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
293 int x, int y, int w, int h)
294{
295#ifndef DIRECT_VRAM
a8fbaf96
AZ		 296 int line;
297 int bypl;
298 int width;
299 int start;
300 uint8_t *src;
301 uint8_t *dst;
302
303 if (x + w > s->width) {
304 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
305 __FUNCTION__, x, w);
306 x = MIN(x, s->width);
307 w = s->width - x;
308 }
309
310 if (y + h > s->height) {
311 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
312 __FUNCTION__, y, h);
313 y = MIN(y, s->height);
314 h = s->height - y;
315 }
316
317 line = h;
318 bypl = s->bypp * s->width;
319 width = s->bypp * w;
320 start = s->bypp * x + bypl * y;
4e12cd94
AK		 321 src = s->vga.vram_ptr + start;
322 dst = ds_get_data(s->vga.ds) + start;
d34cab9f
TS		 323
324 for (; line > 0; line --, src += bypl, dst += bypl)
325 memcpy(dst, src, width);
326#endif
327
4e12cd94 328 dpy_update(s->vga.ds, x, y, w, h);
d34cab9f
TS		 329}
330
331static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
332{
333#ifndef DIRECT_VRAM
4e12cd94 334 memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height);
d34cab9f
TS		 335#endif
336
4e12cd94 337 dpy_update(s->vga.ds, 0, 0, s->width, s->height);
d34cab9f
TS		 338}
339
340#ifdef DIRECT_VRAM
341# define vmsvga_update_rect_delayed vmsvga_update_rect
342#else
343static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
344 int x, int y, int w, int h)
345{
346 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
347 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
348 rect->x = x;
349 rect->y = y;
350 rect->w = w;
351 rect->h = h;
352}
353#endif
354
355static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
356{
357 struct vmsvga_rect_s *rect;
358 if (s->invalidated) {
359 s->redraw_fifo_first = s->redraw_fifo_last;
360 return;
361 }
362 /* Overlapping region updates can be optimised out here - if someone
363 * knows a smart algorithm to do that, please share. */
364 while (s->redraw_fifo_first != s->redraw_fifo_last) {
365 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
366 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
367 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
368 }
369}
370
371#ifdef HW_RECT_ACCEL
372static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
373 int x0, int y0, int x1, int y1, int w, int h)
374{
375# ifdef DIRECT_VRAM
0e1f5a0c 376 uint8_t *vram = ds_get_data(s->ds);
d34cab9f 377# else
4e12cd94 378 uint8_t *vram = s->vga.vram_ptr;
d34cab9f
TS		 379# endif
380 int bypl = s->bypp * s->width;
381 int width = s->bypp * w;
382 int line = h;
383 uint8_t *ptr[2];
384
385# ifdef DIRECT_VRAM
386 if (s->ds->dpy_copy)
3023f332 387 qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
d34cab9f
TS		 388 else
389# endif
390 {
391 if (y1 > y0) {
392 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
393 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
394 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
395 memmove(ptr[1], ptr[0], width);
396 } else {
397 ptr[0] = vram + s->bypp * x0 + bypl * y0;
398 ptr[1] = vram + s->bypp * x1 + bypl * y1;
399 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
400 memmove(ptr[1], ptr[0], width);
401 }
402 }
403
404 vmsvga_update_rect_delayed(s, x1, y1, w, h);
405}
406#endif
407
408#ifdef HW_FILL_ACCEL
409static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
410 uint32_t c, int x, int y, int w, int h)
411{
412# ifdef DIRECT_VRAM
0e1f5a0c 413 uint8_t *vram = ds_get_data(s->ds);
d34cab9f 414# else
4e12cd94 415 uint8_t *vram = s->vga.vram_ptr;
d34cab9f
TS		 416# endif
417 int bypp = s->bypp;
418 int bypl = bypp * s->width;
419 int width = bypp * w;
420 int line = h;
421 int column;
422 uint8_t *fst = vram + bypp * x + bypl * y;
423 uint8_t *dst;
424 uint8_t *src;
425 uint8_t col[4];
426
427# ifdef DIRECT_VRAM
428 if (s->ds->dpy_fill)
429 s->ds->dpy_fill(s->ds, x, y, w, h, c);
430 else
431# endif
432 {
433 col[0] = c;
434 col[1] = c >> 8;
435 col[2] = c >> 16;
436 col[3] = c >> 24;
437
438 if (line --) {
439 dst = fst;
440 src = col;
441 for (column = width; column > 0; column --) {
442 *(dst ++) = *(src ++);
443 if (src - col == bypp)
444 src = col;
445 }
446 dst = fst;
447 for (; line > 0; line --) {
448 dst += bypl;
449 memcpy(dst, fst, width);
450 }
451 }
452 }
453
454 vmsvga_update_rect_delayed(s, x, y, w, h);
455}
456#endif
457
458struct vmsvga_cursor_definition_s {
459 int width;
460 int height;
461 int id;
462 int bpp;
463 int hot_x;
464 int hot_y;
465 uint32_t mask[1024];
8095cb3e 466 uint32_t image[4096];
d34cab9f
TS		 467};
468
469#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
470#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
471
472#ifdef HW_MOUSE_ACCEL
473static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
474 struct vmsvga_cursor_definition_s *c)
475{
fbe6d7a4
GH		 476 QEMUCursor *qc;
477 int i, pixels;
478
479 qc = cursor_alloc(c->width, c->height);
480 qc->hot_x = c->hot_x;
481 qc->hot_y = c->hot_y;
482 switch (c->bpp) {
483 case 1:
484 cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image,
485 1, (void*)c->mask);
486#ifdef DEBUG
487 cursor_print_ascii_art(qc, "vmware/mono");
488#endif
489 break;
490 case 32:
491 /* fill alpha channel from mask, set color to zero */
492 cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask,
493 1, (void*)c->mask);
494 /* add in rgb values */
495 pixels = c->width * c->height;
496 for (i = 0; i < pixels; i++) {
497 qc->data[i] |= c->image[i] & 0xffffff;
498 }
499#ifdef DEBUG
500 cursor_print_ascii_art(qc, "vmware/32bit");
501#endif
502 break;
503 default:
504 fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
505 __FUNCTION__, c->bpp);
506 cursor_put(qc);
507 qc = cursor_builtin_left_ptr();
508 }
d34cab9f 509
4e12cd94 510 if (s->vga.ds->cursor_define)
fbe6d7a4
GH		 511 s->vga.ds->cursor_define(qc);
512 cursor_put(qc);
d34cab9f
TS		 513}
514#endif
515
ff9cf2cb
AZ		 516#define CMD(f) le32_to_cpu(s->cmd->f)
517
4dedc07f 518static inline int vmsvga_fifo_length(struct vmsvga_state_s *s)
d34cab9f 519{
4dedc07f 520 int num;
d34cab9f 521 if (!s->config || !s->enable)
4dedc07f
AZ		 522 return 0;
523 num = CMD(next_cmd) - CMD(stop);
524 if (num < 0)
525 num += CMD(max) - CMD(min);
526 return num >> 2;
d34cab9f
TS		 527}
528
ff9cf2cb 529static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
d34cab9f 530{
ff9cf2cb
AZ		 531 uint32_t cmd = s->fifo[CMD(stop) >> 2];
532 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
533 if (CMD(stop) >= CMD(max))
d34cab9f
TS		 534 s->cmd->stop = s->cmd->min;
535 return cmd;
536}
537
ff9cf2cb
AZ		 538static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
539{
540 return le32_to_cpu(vmsvga_fifo_read_raw(s));
541}
542
d34cab9f
TS		 543static void vmsvga_fifo_run(struct vmsvga_state_s *s)
544{
545 uint32_t cmd, colour;
4dedc07f 546 int args, len;
d34cab9f
TS		 547 int x, y, dx, dy, width, height;
548 struct vmsvga_cursor_definition_s cursor;
4dedc07f
AZ		 549 uint32_t cmd_start;
550
551 len = vmsvga_fifo_length(s);
552 while (len > 0) {
553 /* May need to go back to the start of the command if incomplete */
554 cmd_start = s->cmd->stop;
555
d34cab9f
TS		 556 switch (cmd = vmsvga_fifo_read(s)) {
557 case SVGA_CMD_UPDATE:
558 case SVGA_CMD_UPDATE_VERBOSE:
4dedc07f
AZ		 559 len -= 5;
560 if (len < 0)
561 goto rewind;
562
d34cab9f
TS		 563 x = vmsvga_fifo_read(s);
564 y = vmsvga_fifo_read(s);
565 width = vmsvga_fifo_read(s);
566 height = vmsvga_fifo_read(s);
567 vmsvga_update_rect_delayed(s, x, y, width, height);
568 break;
569
570 case SVGA_CMD_RECT_FILL:
4dedc07f
AZ		 571 len -= 6;
572 if (len < 0)
573 goto rewind;
574
d34cab9f
TS		 575 colour = vmsvga_fifo_read(s);
576 x = vmsvga_fifo_read(s);
577 y = vmsvga_fifo_read(s);
578 width = vmsvga_fifo_read(s);
579 height = vmsvga_fifo_read(s);
580#ifdef HW_FILL_ACCEL
581 vmsvga_fill_rect(s, colour, x, y, width, height);
582 break;
583#else
4dedc07f 584 args = 0;
d34cab9f
TS		 585 goto badcmd;
586#endif
587
588 case SVGA_CMD_RECT_COPY:
4dedc07f
AZ		 589 len -= 7;
590 if (len < 0)
591 goto rewind;
592
d34cab9f
TS		 593 x = vmsvga_fifo_read(s);
594 y = vmsvga_fifo_read(s);
595 dx = vmsvga_fifo_read(s);
596 dy = vmsvga_fifo_read(s);
597 width = vmsvga_fifo_read(s);
598 height = vmsvga_fifo_read(s);
599#ifdef HW_RECT_ACCEL
600 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
601 break;
602#else
4dedc07f 603 args = 0;
d34cab9f
TS		 604 goto badcmd;
605#endif
606
607 case SVGA_CMD_DEFINE_CURSOR:
4dedc07f
AZ		 608 len -= 8;
609 if (len < 0)
610 goto rewind;
611
d34cab9f
TS		 612 cursor.id = vmsvga_fifo_read(s);
613 cursor.hot_x = vmsvga_fifo_read(s);
614 cursor.hot_y = vmsvga_fifo_read(s);
615 cursor.width = x = vmsvga_fifo_read(s);
616 cursor.height = y = vmsvga_fifo_read(s);
617 vmsvga_fifo_read(s);
618 cursor.bpp = vmsvga_fifo_read(s);
f2d928d4 619
4dedc07f 620 args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp);
9f810beb
AZ		 621 if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask ||
622 SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image)
623 goto badcmd;
4dedc07f
AZ		 624
625 len -= args;
626 if (len < 0)
627 goto rewind;
f2d928d4 628
d34cab9f 629 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
ff9cf2cb 630 cursor.mask[args] = vmsvga_fifo_read_raw(s);
d34cab9f 631 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
ff9cf2cb 632 cursor.image[args] = vmsvga_fifo_read_raw(s);
d34cab9f
TS		 633#ifdef HW_MOUSE_ACCEL
634 vmsvga_cursor_define(s, &cursor);
635 break;
636#else
637 args = 0;
638 goto badcmd;
639#endif
640
641 /*
642 * Other commands that we at least know the number of arguments
643 * for so we can avoid FIFO desync if driver uses them illegally.
644 */
645 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
4dedc07f
AZ		 646 len -= 6;
647 if (len < 0)
648 goto rewind;
649
d34cab9f
TS		 650 vmsvga_fifo_read(s);
651 vmsvga_fifo_read(s);
652 vmsvga_fifo_read(s);
653 x = vmsvga_fifo_read(s);
654 y = vmsvga_fifo_read(s);
655 args = x * y;
656 goto badcmd;
657 case SVGA_CMD_RECT_ROP_FILL:
658 args = 6;
659 goto badcmd;
660 case SVGA_CMD_RECT_ROP_COPY:
661 args = 7;
662 goto badcmd;
663 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
4dedc07f
AZ		 664 len -= 4;
665 if (len < 0)
666 goto rewind;
667
d34cab9f
TS		 668 vmsvga_fifo_read(s);
669 vmsvga_fifo_read(s);
670 args = 7 + (vmsvga_fifo_read(s) >> 2);
671 goto badcmd;
672 case SVGA_CMD_SURFACE_ALPHA_BLEND:
673 args = 12;
674 goto badcmd;
675
676 /*
677 * Other commands that are not listed as depending on any
678 * CAPABILITIES bits, but are not described in the README either.
679 */
680 case SVGA_CMD_SURFACE_FILL:
681 case SVGA_CMD_SURFACE_COPY:
682 case SVGA_CMD_FRONT_ROP_FILL:
683 case SVGA_CMD_FENCE:
684 case SVGA_CMD_INVALID_CMD:
685 break; /* Nop */
686
687 default:
4dedc07f 688 args = 0;
d34cab9f 689 badcmd:
4dedc07f
AZ		 690 len -= args;
691 if (len < 0)
692 goto rewind;
d34cab9f
TS		 693 while (args --)
694 vmsvga_fifo_read(s);
695 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
696 __FUNCTION__, cmd);
697 break;
4dedc07f
AZ		 698
699 rewind:
700 s->cmd->stop = cmd_start;
701 break;
d34cab9f 702 }
4dedc07f 703 }
d34cab9f
TS		 704
705 s->syncing = 0;
706}
707
708static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
709{
467d44b2 710 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 711 return s->index;
712}
713
714static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
715{
467d44b2 716 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 717 s->index = index;
718}
719
720static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
721{
722 uint32_t caps;
467d44b2 723 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 724 switch (s->index) {
725 case SVGA_REG_ID:
726 return s->svgaid;
727
728 case SVGA_REG_ENABLE:
729 return s->enable;
730
731 case SVGA_REG_WIDTH:
732 return s->width;
733
734 case SVGA_REG_HEIGHT:
735 return s->height;
736
737 case SVGA_REG_MAX_WIDTH:
738 return SVGA_MAX_WIDTH;
739
740 case SVGA_REG_MAX_HEIGHT:
f707cfba 741 return SVGA_MAX_HEIGHT;
d34cab9f
TS		 742
743 case SVGA_REG_DEPTH:
744 return s->depth;
745
746 case SVGA_REG_BITS_PER_PIXEL:
747 return (s->depth + 7) & ~7;
748
749 case SVGA_REG_PSEUDOCOLOR:
750 return 0x0;
751
752 case SVGA_REG_RED_MASK:
753 return s->wred;
754 case SVGA_REG_GREEN_MASK:
755 return s->wgreen;
756 case SVGA_REG_BLUE_MASK:
757 return s->wblue;
758
759 case SVGA_REG_BYTES_PER_LINE:
760 return ((s->depth + 7) >> 3) * s->new_width;
761
7b619b9a
AK		 762 case SVGA_REG_FB_START: {
763 struct pci_vmsvga_state_s *pci_vmsvga
764 = container_of(s, struct pci_vmsvga_state_s, chip);
765 return pci_get_bar_addr(&pci_vmsvga->card, 1);
766 }
d34cab9f
TS		 767
768 case SVGA_REG_FB_OFFSET:
769 return 0x0;
770
771 case SVGA_REG_VRAM_SIZE:
f351d050 772 return s->vga.vram_size;
d34cab9f
TS		 773
774 case SVGA_REG_FB_SIZE:
775 return s->fb_size;
776
777 case SVGA_REG_CAPABILITIES:
778 caps = SVGA_CAP_NONE;
779#ifdef HW_RECT_ACCEL
780 caps |= SVGA_CAP_RECT_COPY;
781#endif
782#ifdef HW_FILL_ACCEL
783 caps |= SVGA_CAP_RECT_FILL;
784#endif
785#ifdef HW_MOUSE_ACCEL
4e12cd94 786 if (s->vga.ds->mouse_set)
d34cab9f
TS		 787 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
788 SVGA_CAP_CURSOR_BYPASS;
789#endif
790 return caps;
791
b1950430
AK		 792 case SVGA_REG_MEM_START: {
793 struct pci_vmsvga_state_s *pci_vmsvga
794 = container_of(s, struct pci_vmsvga_state_s, chip);
795 return pci_get_bar_addr(&pci_vmsvga->card, 2);
796 }
d34cab9f
TS		 797
798 case SVGA_REG_MEM_SIZE:
f351d050 799 return s->fifo_size;
d34cab9f
TS		 800
801 case SVGA_REG_CONFIG_DONE:
802 return s->config;
803
804 case SVGA_REG_SYNC:
805 case SVGA_REG_BUSY:
806 return s->syncing;
807
808 case SVGA_REG_GUEST_ID:
809 return s->guest;
810
811 case SVGA_REG_CURSOR_ID:
812 return s->cursor.id;
813
814 case SVGA_REG_CURSOR_X:
815 return s->cursor.x;
816
817 case SVGA_REG_CURSOR_Y:
818 return s->cursor.x;
819
820 case SVGA_REG_CURSOR_ON:
821 return s->cursor.on;
822
823 case SVGA_REG_HOST_BITS_PER_PIXEL:
824 return (s->depth + 7) & ~7;
825
826 case SVGA_REG_SCRATCH_SIZE:
827 return s->scratch_size;
828
829 case SVGA_REG_MEM_REGS:
830 case SVGA_REG_NUM_DISPLAYS:
831 case SVGA_REG_PITCHLOCK:
832 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
833 return 0;
834
835 default:
836 if (s->index >= SVGA_SCRATCH_BASE &&
837 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
838 return s->scratch[s->index - SVGA_SCRATCH_BASE];
839 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
840 }
841
842 return 0;
843}
844
845static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
846{
467d44b2 847 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 848 switch (s->index) {
849 case SVGA_REG_ID:
850 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
851 s->svgaid = value;
852 break;
853
854 case SVGA_REG_ENABLE:
f707cfba
AZ		 855 s->enable = value;
856 s->config &= !!value;
d34cab9f
TS		 857 s->width = -1;
858 s->height = -1;
859 s->invalidated = 1;
4e12cd94 860 s->vga.invalidate(&s->vga);
b5cc6e32 861 if (s->enable) {
9f810beb
AZ		 862 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
863 vga_dirty_log_stop(&s->vga);
864 } else {
865 vga_dirty_log_start(&s->vga);
866 }
d34cab9f
TS		 867 break;
868
869 case SVGA_REG_WIDTH:
870 s->new_width = value;
871 s->invalidated = 1;
872 break;
873
874 case SVGA_REG_HEIGHT:
875 s->new_height = value;
876 s->invalidated = 1;
877 break;
878
879 case SVGA_REG_DEPTH:
880 case SVGA_REG_BITS_PER_PIXEL:
881 if (value != s->depth) {
882 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
883 s->config = 0;
884 }
885 break;
886
887 case SVGA_REG_CONFIG_DONE:
888 if (value) {
f351d050 889 s->fifo = (uint32_t *) s->fifo_ptr;
d34cab9f 890 /* Check range and alignment. */
ff9cf2cb
AZ		 891 if ((CMD(min) | CMD(max) |
892 CMD(next_cmd) | CMD(stop)) & 3)
d34cab9f 893 break;
ff9cf2cb 894 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
d34cab9f 895 break;
ff9cf2cb 896 if (CMD(max) > SVGA_FIFO_SIZE)
d34cab9f 897 break;
ff9cf2cb 898 if (CMD(max) < CMD(min) + 10 * 1024)
d34cab9f
TS		 899 break;
900 }
f707cfba 901 s->config = !!value;
d34cab9f
TS		 902 break;
903
904 case SVGA_REG_SYNC:
905 s->syncing = 1;
906 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
907 break;
908
909 case SVGA_REG_GUEST_ID:
910 s->guest = value;
911#ifdef VERBOSE
912 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
b1503cda 913 ARRAY_SIZE(vmsvga_guest_id))
d34cab9f
TS		 914 printf("%s: guest runs %s.\n", __FUNCTION__,
915 vmsvga_guest_id[value - GUEST_OS_BASE]);
916#endif
917 break;
918
919 case SVGA_REG_CURSOR_ID:
920 s->cursor.id = value;
921 break;
922
923 case SVGA_REG_CURSOR_X:
924 s->cursor.x = value;
925 break;
926
927 case SVGA_REG_CURSOR_Y:
928 s->cursor.y = value;
929 break;
930
931 case SVGA_REG_CURSOR_ON:
932 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
933 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
934#ifdef HW_MOUSE_ACCEL
4e12cd94
AK		 935 if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
936 s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
d34cab9f
TS		 937#endif
938 break;
939
940 case SVGA_REG_MEM_REGS:
941 case SVGA_REG_NUM_DISPLAYS:
942 case SVGA_REG_PITCHLOCK:
943 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
944 break;
945
946 default:
947 if (s->index >= SVGA_SCRATCH_BASE &&
948 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
949 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
950 break;
951 }
952 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
953 }
954}
955
956static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
957{
958 printf("%s: what are we supposed to return?\n", __FUNCTION__);
959 return 0xcafe;
960}
961
962static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
963{
964 printf("%s: what are we supposed to do with (%08x)?\n",
965 __FUNCTION__, data);
966}
967
968static inline void vmsvga_size(struct vmsvga_state_s *s)
969{
970 if (s->new_width != s->width || s->new_height != s->height) {
971 s->width = s->new_width;
972 s->height = s->new_height;
4e12cd94 973 qemu_console_resize(s->vga.ds, s->width, s->height);
d34cab9f
TS		 974 s->invalidated = 1;
975 }
976}
977
978static void vmsvga_update_display(void *opaque)
979{
467d44b2 980 struct vmsvga_state_s *s = opaque;
d34cab9f 981 if (!s->enable) {
4e12cd94 982 s->vga.update(&s->vga);
d34cab9f
TS		 983 return;
984 }
985
986 vmsvga_size(s);
987
988 vmsvga_fifo_run(s);
989 vmsvga_update_rect_flush(s);
990
991 /*
992 * Is it more efficient to look at vram VGA-dirty bits or wait
993 * for the driver to issue SVGA_CMD_UPDATE?
994 */
995 if (s->invalidated) {
996 s->invalidated = 0;
997 vmsvga_update_screen(s);
998 }
999}
1000
1001static void vmsvga_reset(struct vmsvga_state_s *s)
1002{
1003 s->index = 0;
1004 s->enable = 0;
1005 s->config = 0;
1006 s->width = -1;
1007 s->height = -1;
1008 s->svgaid = SVGA_ID;
a6109ff1
AL		 1009 s->depth = ds_get_bits_per_pixel(s->vga.ds);
1010 s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
d34cab9f
TS		 1011 s->cursor.on = 0;
1012 s->redraw_fifo_first = 0;
1013 s->redraw_fifo_last = 0;
1014 switch (s->depth) {
1015 case 8:
1016 s->wred = 0x00000007;
1017 s->wgreen = 0x00000038;
1018 s->wblue = 0x000000c0;
1019 break;
1020 case 15:
1021 s->wred = 0x0000001f;
1022 s->wgreen = 0x000003e0;
1023 s->wblue = 0x00007c00;
1024 break;
1025 case 16:
1026 s->wred = 0x0000001f;
1027 s->wgreen = 0x000007e0;
1028 s->wblue = 0x0000f800;
1029 break;
1030 case 24:
f707cfba 1031 s->wred = 0x00ff0000;
d34cab9f 1032 s->wgreen = 0x0000ff00;
f707cfba 1033 s->wblue = 0x000000ff;
d34cab9f
TS		 1034 break;
1035 case 32:
f707cfba 1036 s->wred = 0x00ff0000;
d34cab9f 1037 s->wgreen = 0x0000ff00;
f707cfba 1038 s->wblue = 0x000000ff;
d34cab9f
TS		 1039 break;
1040 }
1041 s->syncing = 0;
b5cc6e32
AL		 1042
1043 vga_dirty_log_start(&s->vga);
d34cab9f
TS		 1044}
1045
1046static void vmsvga_invalidate_display(void *opaque)
1047{
467d44b2 1048 struct vmsvga_state_s *s = opaque;
d34cab9f 1049 if (!s->enable) {
4e12cd94 1050 s->vga.invalidate(&s->vga);
d34cab9f
TS		 1051 return;
1052 }
1053
1054 s->invalidated = 1;
1055}
1056
f707cfba
AZ		 1057/* save the vga display in a PPM image even if no display is
1058 available */
d34cab9f
TS		 1059static void vmsvga_screen_dump(void *opaque, const char *filename)
1060{
467d44b2 1061 struct vmsvga_state_s *s = opaque;
d34cab9f 1062 if (!s->enable) {
4e12cd94 1063 s->vga.screen_dump(&s->vga, filename);
d34cab9f
TS		 1064 return;
1065 }
1066
f707cfba 1067 if (s->depth == 32) {
e07d630a 1068 DisplaySurface *ds = qemu_create_displaysurface_from(s->width,
4e12cd94 1069 s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
e07d630a
AL		 1070 ppm_save(filename, ds);
1071 qemu_free(ds);
f707cfba 1072 }
d34cab9f
TS		 1073}
1074
c227f099 1075static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
4d3b6f6e 1076{
467d44b2 1077 struct vmsvga_state_s *s = opaque;
4d3b6f6e 1078
4e12cd94
AK		 1079 if (s->vga.text_update)
1080 s->vga.text_update(&s->vga, chardata);
4d3b6f6e
AZ		 1081}
1082
d34cab9f 1083#ifdef DIRECT_VRAM
c227f099 1084static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
d34cab9f 1085{
467d44b2 1086 struct vmsvga_state_s *s = opaque;
d34cab9f 1087 if (addr < s->fb_size)
0e1f5a0c 1088 return *(uint8_t *) (ds_get_data(s->ds) + addr);
d34cab9f 1089 else
b584726d 1090 return *(uint8_t *) (s->vram_ptr + addr);
d34cab9f
TS		 1091}
1092
c227f099 1093static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
d34cab9f 1094{
467d44b2 1095 struct vmsvga_state_s *s = opaque;
d34cab9f 1096 if (addr < s->fb_size)
0e1f5a0c 1097 return *(uint16_t *) (ds_get_data(s->ds) + addr);
d34cab9f 1098 else
b584726d 1099 return *(uint16_t *) (s->vram_ptr + addr);
d34cab9f
TS		 1100}
1101
c227f099 1102static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
d34cab9f 1103{
467d44b2 1104 struct vmsvga_state_s *s = opaque;
d34cab9f 1105 if (addr < s->fb_size)
0e1f5a0c 1106 return *(uint32_t *) (ds_get_data(s->ds) + addr);
d34cab9f 1107 else
b584726d 1108 return *(uint32_t *) (s->vram_ptr + addr);
d34cab9f
TS		 1109}
1110
c227f099 1111static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
d34cab9f
TS		 1112 uint32_t value)
1113{
467d44b2 1114 struct vmsvga_state_s *s = opaque;
d34cab9f 1115 if (addr < s->fb_size)
0e1f5a0c 1116 *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f 1117 else
b584726d 1118 *(uint8_t *) (s->vram_ptr + addr) = value;
d34cab9f
TS		 1119}
1120
c227f099 1121static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
d34cab9f
TS		 1122 uint32_t value)
1123{
467d44b2 1124 struct vmsvga_state_s *s = opaque;
d34cab9f 1125 if (addr < s->fb_size)
0e1f5a0c 1126 *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f 1127 else
b584726d 1128 *(uint16_t *) (s->vram_ptr + addr) = value;
d34cab9f
TS		 1129}
1130
c227f099 1131static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
d34cab9f
TS		 1132 uint32_t value)
1133{
467d44b2 1134 struct vmsvga_state_s *s = opaque;
d34cab9f 1135 if (addr < s->fb_size)
0e1f5a0c 1136 *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
d34cab9f 1137 else
b584726d 1138 *(uint32_t *) (s->vram_ptr + addr) = value;
d34cab9f
TS		 1139}
1140
b1950430
AK		 1141static const MemoryRegionOps vmsvga_vram_io_ops = {
1142 .old_mmio = {
1143 .read = {
1144 vmsvga_vram_readb,
1145 vmsvga_vram_readw,
1146 vmsvga_vram_readl,
1147 },
1148 .write = {
1149 vmsvga_vram_writeb,
1150 vmsvga_vram_writew,
1151 vmsvga_vram_writel,
1152 },
1153 },
1154 .endianness = DEVICE_NATIVE_ENDIAN,
1155}
d34cab9f 1156
d34cab9f
TS		 1157#endif
1158
bacbe284 1159static int vmsvga_post_load(void *opaque, int version_id)
d34cab9f 1160{
bacbe284 1161 struct vmsvga_state_s *s = opaque;
d34cab9f
TS		 1162
1163 s->invalidated = 1;
1164 if (s->config)
f351d050 1165 s->fifo = (uint32_t *) s->fifo_ptr;
d34cab9f
TS		 1166
1167 return 0;
1168}
1169
d05ac8fa 1170static const VMStateDescription vmstate_vmware_vga_internal = {
bacbe284
JQ		 1171 .name = "vmware_vga_internal",
1172 .version_id = 0,
1173 .minimum_version_id = 0,
1174 .minimum_version_id_old = 0,
1175 .post_load = vmsvga_post_load,
1176 .fields = (VMStateField []) {
1177 VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
1178 VMSTATE_INT32(enable, struct vmsvga_state_s),
1179 VMSTATE_INT32(config, struct vmsvga_state_s),
1180 VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
1181 VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
1182 VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
1183 VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
1184 VMSTATE_INT32(index, struct vmsvga_state_s),
1185 VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
1186 scratch_size, 0, vmstate_info_uint32, uint32_t),
1187 VMSTATE_INT32(new_width, struct vmsvga_state_s),
1188 VMSTATE_INT32(new_height, struct vmsvga_state_s),
1189 VMSTATE_UINT32(guest, struct vmsvga_state_s),
1190 VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
1191 VMSTATE_INT32(syncing, struct vmsvga_state_s),
1192 VMSTATE_INT32(fb_size, struct vmsvga_state_s),
1193 VMSTATE_END_OF_LIST()
1194 }
1195};
1196
d05ac8fa 1197static const VMStateDescription vmstate_vmware_vga = {
bacbe284
JQ		 1198 .name = "vmware_vga",
1199 .version_id = 0,
1200 .minimum_version_id = 0,
1201 .minimum_version_id_old = 0,
1202 .fields = (VMStateField []) {
1203 VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
1204 VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0,
1205 vmstate_vmware_vga_internal, struct vmsvga_state_s),
1206 VMSTATE_END_OF_LIST()
1207 }
1208};
1209
b584726d 1210static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size)
d34cab9f 1211{
d34cab9f 1212 s->scratch_size = SVGA_SCRATCH_SIZE;
fe740c43 1213 s->scratch = qemu_malloc(s->scratch_size * 4);
d34cab9f 1214
a6109ff1
AL		 1215 s->vga.ds = graphic_console_init(vmsvga_update_display,
1216 vmsvga_invalidate_display,
1217 vmsvga_screen_dump,
1218 vmsvga_text_update, s);
1219
4445b0a6 1220
f351d050 1221 s->fifo_size = SVGA_FIFO_SIZE;
b1950430
AK		 1222 memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size);
1223 s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram);
f351d050 1224
a4a2f59c
JQ		 1225 vga_common_init(&s->vga, vga_ram_size);
1226 vga_init(&s->vga);
0be71e32 1227 vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
e93a5f4f 1228
b5cc6e32 1229 vmsvga_reset(s);
d34cab9f
TS		 1230}
1231
b1950430
AK		 1232static uint64_t vmsvga_io_read(void *opaque, target_phys_addr_t addr,
1233 unsigned size)
1492a3c4 1234{
b1950430
AK		 1235 struct vmsvga_state_s *s = opaque;
1236
1237 switch (addr) {
1238 case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr);
1239 case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr);
1240 case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr);
1241 default: return -1u;
1242 }
1492a3c4
AZ		 1243}
1244
b1950430
AK		 1245static void vmsvga_io_write(void *opaque, target_phys_addr_t addr,
1246 uint64_t data, unsigned size)
3016d80b 1247{
b1950430 1248 struct vmsvga_state_s *s = opaque;
ee3e41a9 1249
b1950430
AK		 1250 switch (addr) {
1251 case SVGA_IO_MUL * SVGA_INDEX_PORT:
1252 return vmsvga_index_write(s, addr, data);
1253 case SVGA_IO_MUL * SVGA_VALUE_PORT:
1254 return vmsvga_value_write(s, addr, data);
1255 case SVGA_IO_MUL * SVGA_BIOS_PORT:
1256 return vmsvga_bios_write(s, addr, data);
1257 }
3016d80b
AZ		 1258}
1259
b1950430
AK		 1260static const MemoryRegionOps vmsvga_io_ops = {
1261 .read = vmsvga_io_read,
1262 .write = vmsvga_io_write,
1263 .endianness = DEVICE_LITTLE_ENDIAN,
1264 .valid = {
1265 .min_access_size = 4,
1266 .max_access_size = 4,
1267 },
1268};
f351d050 1269
81a322d4 1270static int pci_vmsvga_initfn(PCIDevice *dev)
d34cab9f 1271{
a414c306
GH		 1272 struct pci_vmsvga_state_s *s =
1273 DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
b1950430
AK		 1274 MemoryRegion *iomem;
1275
1276#ifdef DIRECT_VRAM
1277 DirectMem *directmem = qemu_malloc(sizeof(*directmem));
1278
1279 iomem = &directmem->mr;
1280 memory_region_init_io(iomem, &vmsvga_vram_io_ops, &s->chip, "vmsvga",
1281 memory_region_size(&s->chip.vga.vram));
1282#else
1283 iomem = &s->chip.vga.vram;
1284#endif
1285
1286 vga_dirty_log_restart(&s->chip.vga);
d34cab9f 1287
3fa0f955
MT		 1288 s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */
1289 s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */
3fa0f955 1290 s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */
d34cab9f 1291
b1950430
AK		 1292 memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
1293 "vmsvga-io", 0x10);
e824b2cc 1294 pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
f351d050 1295
fbe1b595 1296 vmsvga_init(&s->chip, VGA_RAM_SIZE);
d34cab9f 1297
e824b2cc
AK		 1298 pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
1299 pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
1300 &s->chip.fifo_ram);
b1950430 1301
281a26b1
GH		 1302 if (!dev->rom_bar) {
1303 /* compatibility with pc-0.13 and older */
1304 vga_init_vbe(&s->chip.vga);
1305 }
1306
81a322d4 1307 return 0;
d34cab9f 1308}
a414c306 1309
a414c306 1310static PCIDeviceInfo vmsvga_info = {
556cd098 1311 .qdev.name = "vmware-svga",
a414c306 1312 .qdev.size = sizeof(struct pci_vmsvga_state_s),
be73cfe2 1313 .qdev.vmsd = &vmstate_vmware_vga,
be92bbf7 1314 .no_hotplug = 1,
a414c306 1315 .init = pci_vmsvga_initfn,
4eccfec4 1316 .romfile = "vgabios-vmware.bin",
310faaed
IY		 1317
1318 .vendor_id = PCI_VENDOR_ID_VMWARE,
1319 .device_id = SVGA_PCI_DEVICE_ID,
1320 .class_id = PCI_CLASS_DISPLAY_VGA,
1321 .subsystem_vendor_id = PCI_VENDOR_ID_VMWARE,
1322 .subsystem_id = SVGA_PCI_DEVICE_ID,
a414c306
GH		 1323};
1324
1325static void vmsvga_register(void)
1326{
1327 pci_qdev_register(&vmsvga_info);
1328}
1329device_init(vmsvga_register);
Qemu copy for testing