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edf79e66 HC |
1 | /* |
2 | * VT82C686B south bridge support | |
3 | * | |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) | |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) | |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) | |
7 | * This code is licensed under the GNU GPL v2. | |
8 | */ | |
9 | ||
10 | #include "hw.h" | |
11 | #include "pc.h" | |
12 | #include "vt82c686.h" | |
13 | #include "i2c.h" | |
14 | #include "smbus.h" | |
15 | #include "pci.h" | |
16 | #include "isa.h" | |
17 | #include "sysbus.h" | |
18 | #include "mips.h" | |
19 | #include "apm.h" | |
20 | #include "acpi.h" | |
21 | #include "pm_smbus.h" | |
22 | #include "sysemu.h" | |
23 | #include "qemu-timer.h" | |
24 | ||
25 | typedef uint32_t pci_addr_t; | |
26 | #include "pci_host.h" | |
27 | //#define DEBUG_VT82C686B | |
28 | ||
29 | #ifdef DEBUG_VT82C686B | |
30 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) | |
31 | #else | |
32 | #define DPRINTF(fmt, ...) | |
33 | #endif | |
34 | ||
35 | typedef struct SuperIOConfig | |
36 | { | |
37 | uint8_t config[0xff]; | |
38 | uint8_t index; | |
39 | uint8_t data; | |
40 | } SuperIOConfig; | |
41 | ||
42 | typedef struct VT82C686BState { | |
43 | PCIDevice dev; | |
44 | SuperIOConfig superio_conf; | |
45 | } VT82C686BState; | |
46 | ||
47 | static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) | |
48 | { | |
49 | int can_write; | |
50 | SuperIOConfig *superio_conf = opaque; | |
51 | ||
52 | DPRINTF("superio_ioport_writeb address 0x%x val 0x%x \n", addr, data); | |
53 | if (addr == 0x3f0) { | |
54 | superio_conf->index = data & 0xff; | |
55 | } else { | |
56 | /* 0x3f1 */ | |
57 | switch (superio_conf->index) { | |
58 | case 0x00 ... 0xdf: | |
59 | case 0xe4: | |
60 | case 0xe5: | |
61 | case 0xe9 ... 0xed: | |
62 | case 0xf3: | |
63 | case 0xf5: | |
64 | case 0xf7: | |
65 | case 0xf9 ... 0xfb: | |
66 | case 0xfd ... 0xff: | |
67 | can_write = 0; | |
68 | break; | |
69 | default: | |
70 | can_write = 1; | |
71 | ||
72 | if (can_write) { | |
73 | switch (superio_conf->index) { | |
74 | case 0xe7: | |
75 | if ((data & 0xff) != 0xfe) { | |
76 | DPRINTF("chage uart 1 base. unsupported yet \n"); | |
77 | } | |
78 | break; | |
79 | case 0xe8: | |
80 | if ((data & 0xff) != 0xbe) { | |
81 | DPRINTF("chage uart 2 base. unsupported yet \n"); | |
82 | } | |
83 | break; | |
84 | ||
85 | default: | |
86 | superio_conf->config[superio_conf->index] = data & 0xff; | |
87 | } | |
88 | } | |
89 | } | |
90 | superio_conf->config[superio_conf->index] = data & 0xff; | |
91 | } | |
92 | } | |
93 | ||
94 | static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) | |
95 | { | |
96 | SuperIOConfig *superio_conf = opaque; | |
97 | ||
98 | DPRINTF("superio_ioport_readb address 0x%x \n", addr); | |
99 | return (superio_conf->config[superio_conf->index]); | |
100 | } | |
101 | ||
102 | static void vt82c686b_reset(void * opaque) | |
103 | { | |
104 | PCIDevice *d = opaque; | |
105 | uint8_t *pci_conf = d->config; | |
106 | VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); | |
107 | ||
108 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); | |
109 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | | |
110 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); | |
111 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
112 | ||
113 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ | |
114 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ | |
115 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ | |
116 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ | |
117 | pci_conf[0x59] = 0x04; | |
118 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ | |
119 | pci_conf[0x5f] = 0x04; | |
120 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ | |
121 | ||
122 | vt82c->superio_conf.config[0xe0] = 0x3c; | |
123 | vt82c->superio_conf.config[0xe2] = 0x03; | |
124 | vt82c->superio_conf.config[0xe3] = 0xfc; | |
125 | vt82c->superio_conf.config[0xe6] = 0xde; | |
126 | vt82c->superio_conf.config[0xe7] = 0xfe; | |
127 | vt82c->superio_conf.config[0xe8] = 0xbe; | |
128 | } | |
129 | ||
130 | /* write config pci function0 registers. PCI-ISA bridge */ | |
131 | static void vt82c686b_write_config(PCIDevice * d, uint32_t address, | |
132 | uint32_t val, int len) | |
133 | { | |
134 | VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d); | |
135 | ||
136 | DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x \n", | |
137 | address, val, len); | |
138 | ||
139 | pci_default_write_config(d, address, val, len); | |
140 | if (address == 0x85) { /* enable or disable super IO configure */ | |
141 | if (val & 0x2) { | |
142 | /* floppy also uses 0x3f0 and 0x3f1. | |
143 | * But we do not emulate flopy,so just set it here. */ | |
144 | isa_unassign_ioport(0x3f0, 2); | |
145 | register_ioport_read(0x3f0, 2, 1, superio_ioport_readb, | |
146 | &vt686->superio_conf); | |
147 | register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb, | |
148 | &vt686->superio_conf); | |
149 | } else { | |
150 | isa_unassign_ioport(0x3f0, 2); | |
151 | } | |
152 | } | |
153 | } | |
154 | ||
155 | #define ACPI_DBG_IO_ADDR 0xb044 | |
156 | ||
157 | typedef struct VT686PMState { | |
158 | PCIDevice dev; | |
04dc308f | 159 | ACPIPM1EVT pm1a; |
edf79e66 HC |
160 | uint16_t pmcntrl; |
161 | APMState apm; | |
a54d41a8 | 162 | ACPIPMTimer tmr; |
edf79e66 HC |
163 | PMSMBus smb; |
164 | uint32_t smb_io_base; | |
165 | } VT686PMState; | |
166 | ||
167 | typedef struct VT686AC97State { | |
168 | PCIDevice dev; | |
169 | } VT686AC97State; | |
170 | ||
171 | typedef struct VT686MC97State { | |
172 | PCIDevice dev; | |
173 | } VT686MC97State; | |
174 | ||
edf79e66 HC |
175 | static void pm_update_sci(VT686PMState *s) |
176 | { | |
177 | int sci_level, pmsts; | |
edf79e66 | 178 | |
04dc308f IY |
179 | pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
180 | sci_level = (((pmsts & s->pm1a.en) & | |
181 | (ACPI_BITMASK_RT_CLOCK_ENABLE | | |
182 | ACPI_BITMASK_POWER_BUTTON_ENABLE | | |
183 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | | |
184 | ACPI_BITMASK_TIMER_ENABLE)) != 0); | |
edf79e66 HC |
185 | qemu_set_irq(s->dev.irq[0], sci_level); |
186 | /* schedule a timer interruption if needed */ | |
04dc308f | 187 | acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) && |
a54d41a8 | 188 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
edf79e66 HC |
189 | } |
190 | ||
a54d41a8 | 191 | static void pm_tmr_timer(ACPIPMTimer *tmr) |
edf79e66 | 192 | { |
a54d41a8 | 193 | VT686PMState *s = container_of(tmr, VT686PMState, tmr); |
edf79e66 HC |
194 | pm_update_sci(s); |
195 | } | |
196 | ||
197 | static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) | |
198 | { | |
199 | VT686PMState *s = opaque; | |
200 | ||
201 | addr &= 0x0f; | |
202 | switch (addr) { | |
203 | case 0x00: | |
04dc308f IY |
204 | acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val); |
205 | pm_update_sci(s); | |
edf79e66 HC |
206 | break; |
207 | case 0x02: | |
04dc308f | 208 | s->pm1a.en = val; |
edf79e66 HC |
209 | pm_update_sci(s); |
210 | break; | |
211 | case 0x04: | |
212 | { | |
213 | int sus_typ; | |
214 | s->pmcntrl = val & ~(SUS_EN); | |
215 | if (val & SUS_EN) { | |
216 | /* change suspend type */ | |
217 | sus_typ = (val >> 10) & 3; | |
218 | switch (sus_typ) { | |
219 | case 0: /* soft power off */ | |
220 | qemu_system_shutdown_request(); | |
221 | break; | |
222 | default: | |
223 | break; | |
224 | } | |
225 | } | |
226 | } | |
227 | break; | |
228 | default: | |
229 | break; | |
230 | } | |
231 | DPRINTF("PM writew port=0x%04x val=0x%02x\n", addr, val); | |
232 | } | |
233 | ||
234 | static uint32_t pm_ioport_readw(void *opaque, uint32_t addr) | |
235 | { | |
236 | VT686PMState *s = opaque; | |
237 | uint32_t val; | |
238 | ||
239 | addr &= 0x0f; | |
240 | switch (addr) { | |
241 | case 0x00: | |
04dc308f | 242 | val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time); |
edf79e66 HC |
243 | break; |
244 | case 0x02: | |
04dc308f | 245 | val = s->pm1a.en; |
edf79e66 HC |
246 | break; |
247 | case 0x04: | |
248 | val = s->pmcntrl; | |
249 | break; | |
250 | default: | |
251 | val = 0; | |
252 | break; | |
253 | } | |
254 | DPRINTF("PM readw port=0x%04x val=0x%02x\n", addr, val); | |
255 | return val; | |
256 | } | |
257 | ||
258 | static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val) | |
259 | { | |
260 | addr &= 0x0f; | |
261 | DPRINTF("PM writel port=0x%04x val=0x%08x\n", addr, val); | |
262 | } | |
263 | ||
264 | static uint32_t pm_ioport_readl(void *opaque, uint32_t addr) | |
265 | { | |
266 | VT686PMState *s = opaque; | |
267 | uint32_t val; | |
268 | ||
269 | addr &= 0x0f; | |
270 | switch (addr) { | |
271 | case 0x08: | |
a54d41a8 | 272 | val = acpi_pm_tmr_get(&s->tmr); |
edf79e66 HC |
273 | break; |
274 | default: | |
275 | val = 0; | |
276 | break; | |
277 | } | |
278 | DPRINTF("PM readl port=0x%04x val=0x%08x\n", addr, val); | |
279 | return val; | |
280 | } | |
281 | ||
282 | static void pm_io_space_update(VT686PMState *s) | |
283 | { | |
284 | uint32_t pm_io_base; | |
285 | ||
286 | if (s->dev.config[0x80] & 1) { | |
287 | pm_io_base = pci_get_long(s->dev.config + 0x40); | |
288 | pm_io_base &= 0xffc0; | |
289 | ||
290 | /* XXX: need to improve memory and ioport allocation */ | |
291 | DPRINTF("PM: mapping to 0x%x\n", pm_io_base); | |
292 | register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s); | |
293 | register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s); | |
294 | register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s); | |
295 | register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s); | |
296 | } | |
297 | } | |
298 | ||
299 | static void pm_write_config(PCIDevice *d, | |
300 | uint32_t address, uint32_t val, int len) | |
301 | { | |
302 | DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x \n", | |
303 | address, val, len); | |
304 | pci_default_write_config(d, address, val, len); | |
305 | } | |
306 | ||
307 | static int vmstate_acpi_post_load(void *opaque, int version_id) | |
308 | { | |
309 | VT686PMState *s = opaque; | |
310 | ||
311 | pm_io_space_update(s); | |
312 | return 0; | |
313 | } | |
314 | ||
315 | static const VMStateDescription vmstate_acpi = { | |
316 | .name = "vt82c686b_pm", | |
317 | .version_id = 1, | |
318 | .minimum_version_id = 1, | |
319 | .minimum_version_id_old = 1, | |
320 | .post_load = vmstate_acpi_post_load, | |
321 | .fields = (VMStateField []) { | |
322 | VMSTATE_PCI_DEVICE(dev, VT686PMState), | |
04dc308f IY |
323 | VMSTATE_UINT16(pm1a.sts, VT686PMState), |
324 | VMSTATE_UINT16(pm1a.en, VT686PMState), | |
edf79e66 HC |
325 | VMSTATE_UINT16(pmcntrl, VT686PMState), |
326 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), | |
a54d41a8 IY |
327 | VMSTATE_TIMER(tmr.timer, VT686PMState), |
328 | VMSTATE_INT64(tmr.overflow_time, VT686PMState), | |
edf79e66 HC |
329 | VMSTATE_END_OF_LIST() |
330 | } | |
331 | }; | |
332 | ||
333 | /* | |
334 | * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() | |
335 | * just register a PCI device now, functionalities will be implemented later. | |
336 | */ | |
337 | ||
338 | static int vt82c686b_ac97_initfn(PCIDevice *dev) | |
339 | { | |
340 | VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev); | |
341 | uint8_t *pci_conf = s->dev.config; | |
342 | ||
343 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); | |
344 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_AC97); | |
345 | pci_config_set_class(pci_conf, PCI_CLASS_MULTIMEDIA_AUDIO); | |
346 | pci_config_set_revision(pci_conf, 0x50); | |
347 | ||
348 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | | |
349 | PCI_COMMAND_PARITY); | |
350 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | | |
351 | PCI_STATUS_DEVSEL_MEDIUM); | |
352 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
353 | ||
354 | return 0; | |
355 | } | |
356 | ||
357 | void vt82c686b_ac97_init(PCIBus *bus, int devfn) | |
358 | { | |
359 | PCIDevice *dev; | |
360 | ||
361 | dev = pci_create(bus, devfn, "VT82C686B_AC97"); | |
362 | qdev_init_nofail(&dev->qdev); | |
363 | } | |
364 | ||
365 | static PCIDeviceInfo via_ac97_info = { | |
366 | .qdev.name = "VT82C686B_AC97", | |
367 | .qdev.desc = "AC97", | |
368 | .qdev.size = sizeof(VT686AC97State), | |
369 | .init = vt82c686b_ac97_initfn, | |
370 | }; | |
371 | ||
372 | static void vt82c686b_ac97_register(void) | |
373 | { | |
374 | pci_qdev_register(&via_ac97_info); | |
375 | } | |
376 | ||
377 | device_init(vt82c686b_ac97_register); | |
378 | ||
379 | static int vt82c686b_mc97_initfn(PCIDevice *dev) | |
380 | { | |
381 | VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev); | |
382 | uint8_t *pci_conf = s->dev.config; | |
383 | ||
384 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); | |
385 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_MC97); | |
386 | pci_config_set_class(pci_conf, PCI_CLASS_COMMUNICATION_OTHER); | |
387 | pci_config_set_revision(pci_conf, 0x30); | |
388 | ||
389 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | | |
390 | PCI_COMMAND_VGA_PALETTE); | |
391 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); | |
392 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); | |
393 | ||
394 | return 0; | |
395 | } | |
396 | ||
397 | void vt82c686b_mc97_init(PCIBus *bus, int devfn) | |
398 | { | |
399 | PCIDevice *dev; | |
400 | ||
401 | dev = pci_create(bus, devfn, "VT82C686B_MC97"); | |
402 | qdev_init_nofail(&dev->qdev); | |
403 | } | |
404 | ||
405 | static PCIDeviceInfo via_mc97_info = { | |
406 | .qdev.name = "VT82C686B_MC97", | |
407 | .qdev.desc = "MC97", | |
408 | .qdev.size = sizeof(VT686MC97State), | |
409 | .init = vt82c686b_mc97_initfn, | |
410 | }; | |
411 | ||
412 | static void vt82c686b_mc97_register(void) | |
413 | { | |
414 | pci_qdev_register(&via_mc97_info); | |
415 | } | |
416 | ||
417 | device_init(vt82c686b_mc97_register); | |
418 | ||
419 | /* vt82c686 pm init */ | |
420 | static int vt82c686b_pm_initfn(PCIDevice *dev) | |
421 | { | |
422 | VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev); | |
423 | uint8_t *pci_conf; | |
424 | ||
425 | pci_conf = s->dev.config; | |
426 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); | |
427 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ACPI); | |
428 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); | |
429 | pci_config_set_revision(pci_conf, 0x40); | |
edf79e66 HC |
430 | |
431 | pci_set_word(pci_conf + PCI_COMMAND, 0); | |
432 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | | |
433 | PCI_STATUS_DEVSEL_MEDIUM); | |
434 | ||
435 | /* 0x48-0x4B is Power Management I/O Base */ | |
436 | pci_set_long(pci_conf + 0x48, 0x00000001); | |
437 | ||
438 | /* SMB ports:0xeee0~0xeeef */ | |
439 | s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); | |
440 | pci_conf[0x90] = s->smb_io_base | 1; | |
441 | pci_conf[0x91] = s->smb_io_base >> 8; | |
442 | pci_conf[0xd2] = 0x90; | |
443 | register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb); | |
444 | register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb); | |
445 | ||
446 | apm_init(&s->apm, NULL, s); | |
447 | ||
a54d41a8 | 448 | acpi_pm_tmr_init(&s->tmr, pm_tmr_timer); |
edf79e66 HC |
449 | |
450 | pm_smbus_init(&s->dev.qdev, &s->smb); | |
451 | ||
452 | return 0; | |
453 | } | |
454 | ||
455 | i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, | |
456 | qemu_irq sci_irq) | |
457 | { | |
458 | PCIDevice *dev; | |
459 | VT686PMState *s; | |
460 | ||
461 | dev = pci_create(bus, devfn, "VT82C686B_PM"); | |
462 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); | |
463 | ||
464 | s = DO_UPCAST(VT686PMState, dev, dev); | |
465 | ||
466 | qdev_init_nofail(&dev->qdev); | |
467 | ||
468 | return s->smb.smbus; | |
469 | } | |
470 | ||
471 | static PCIDeviceInfo via_pm_info = { | |
472 | .qdev.name = "VT82C686B_PM", | |
473 | .qdev.desc = "PM", | |
474 | .qdev.size = sizeof(VT686PMState), | |
475 | .qdev.vmsd = &vmstate_acpi, | |
476 | .init = vt82c686b_pm_initfn, | |
477 | .config_write = pm_write_config, | |
478 | .qdev.props = (Property[]) { | |
479 | DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), | |
480 | DEFINE_PROP_END_OF_LIST(), | |
481 | } | |
482 | }; | |
483 | ||
484 | static void vt82c686b_pm_register(void) | |
485 | { | |
486 | pci_qdev_register(&via_pm_info); | |
487 | } | |
488 | ||
489 | device_init(vt82c686b_pm_register); | |
490 | ||
491 | static const VMStateDescription vmstate_via = { | |
492 | .name = "vt82c686b", | |
493 | .version_id = 1, | |
494 | .minimum_version_id = 1, | |
495 | .minimum_version_id_old = 1, | |
496 | .fields = (VMStateField []) { | |
497 | VMSTATE_PCI_DEVICE(dev, VT82C686BState), | |
498 | VMSTATE_END_OF_LIST() | |
499 | } | |
500 | }; | |
501 | ||
502 | /* init the PCI-to-ISA bridge */ | |
503 | static int vt82c686b_initfn(PCIDevice *d) | |
504 | { | |
505 | uint8_t *pci_conf; | |
506 | uint8_t *wmask; | |
507 | int i; | |
508 | ||
509 | isa_bus_new(&d->qdev); | |
510 | ||
511 | pci_conf = d->config; | |
512 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); | |
513 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_ISA_BRIDGE); | |
514 | pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); | |
515 | pci_config_set_prog_interface(pci_conf, 0x0); | |
516 | pci_config_set_revision(pci_conf,0x40); /* Revision 4.0 */ | |
edf79e66 HC |
517 | |
518 | wmask = d->wmask; | |
519 | for (i = 0x00; i < 0xff; i++) { | |
520 | if (i<=0x03 || (i>=0x08 && i<=0x3f)) { | |
521 | wmask[i] = 0x00; | |
522 | } | |
523 | } | |
524 | ||
525 | qemu_register_reset(vt82c686b_reset, d); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
530 | int vt82c686b_init(PCIBus *bus, int devfn) | |
531 | { | |
532 | PCIDevice *d; | |
533 | ||
aa5fb7b3 | 534 | d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B"); |
edf79e66 HC |
535 | |
536 | return d->devfn; | |
537 | } | |
538 | ||
539 | static PCIDeviceInfo via_info = { | |
540 | .qdev.name = "VT82C686B", | |
541 | .qdev.desc = "ISA bridge", | |
542 | .qdev.size = sizeof(VT82C686BState), | |
543 | .qdev.vmsd = &vmstate_via, | |
544 | .qdev.no_user = 1, | |
545 | .init = vt82c686b_initfn, | |
546 | .config_write = vt82c686b_write_config, | |
547 | }; | |
548 | ||
549 | static void vt82c686b_register(void) | |
550 | { | |
551 | pci_qdev_register(&via_info); | |
552 | } | |
553 | device_init(vt82c686b_register); |