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9dd986cc RJ |
1 | /* |
2 | * Virtual hardware watchdog. | |
3 | * | |
4 | * Copyright (C) 2009 Red Hat Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
8167ee88 | 17 | * along with this program; if not, see <http://www.gnu.org/licenses/>. |
9dd986cc RJ |
18 | * |
19 | * By Richard W.M. Jones (rjones@redhat.com). | |
20 | */ | |
21 | ||
22 | #include <inttypes.h> | |
23 | ||
24 | #include "qemu-common.h" | |
25 | #include "qemu-timer.h" | |
26 | #include "watchdog.h" | |
27 | #include "hw.h" | |
9dd986cc RJ |
28 | #include "pc.h" |
29 | #include "pci.h" | |
30 | ||
31 | /*#define I6300ESB_DEBUG 1*/ | |
32 | ||
33 | #ifdef I6300ESB_DEBUG | |
34 | #define i6300esb_debug(fs,...) \ | |
35 | fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__) | |
36 | #else | |
37 | #define i6300esb_debug(fs,...) | |
38 | #endif | |
39 | ||
40 | #ifndef PCI_DEVICE_ID_INTEL_ESB_9 | |
41 | #define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab | |
42 | #endif | |
43 | ||
44 | /* PCI configuration registers */ | |
45 | #define ESB_CONFIG_REG 0x60 /* Config register */ | |
46 | #define ESB_LOCK_REG 0x68 /* WDT lock register */ | |
47 | ||
48 | /* Memory mapped registers (offset from base address) */ | |
49 | #define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */ | |
50 | #define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */ | |
51 | #define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */ | |
52 | #define ESB_RELOAD_REG 0x0c /* Reload register */ | |
53 | ||
54 | /* Lock register bits */ | |
55 | #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */ | |
56 | #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */ | |
57 | #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */ | |
58 | ||
59 | /* Config register bits */ | |
60 | #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */ | |
61 | #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */ | |
62 | #define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */ | |
63 | ||
64 | /* Reload register bits */ | |
65 | #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */ | |
66 | ||
67 | /* Magic constants */ | |
68 | #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ | |
69 | #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */ | |
70 | ||
71 | /* Device state. */ | |
72 | struct I6300State { | |
9d472d51 | 73 | PCIDevice dev; |
9dd986cc RJ |
74 | |
75 | int reboot_enabled; /* "Reboot" on timer expiry. The real action | |
76 | * performed depends on the -watchdog-action | |
77 | * param passed on QEMU command line. | |
78 | */ | |
79 | int clock_scale; /* Clock scale. */ | |
80 | #define CLOCK_SCALE_1KHZ 0 | |
81 | #define CLOCK_SCALE_1MHZ 1 | |
82 | ||
83 | int int_type; /* Interrupt type generated. */ | |
84 | #define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */ | |
85 | #define INT_TYPE_SMI 2 | |
86 | #define INT_TYPE_DISABLED 3 | |
87 | ||
88 | int free_run; /* If true, reload timer on expiry. */ | |
89 | int locked; /* If true, enabled field cannot be changed. */ | |
90 | int enabled; /* If true, watchdog is enabled. */ | |
91 | ||
92 | QEMUTimer *timer; /* The actual watchdog timer. */ | |
93 | ||
94 | uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */ | |
95 | uint32_t timer2_preload; | |
96 | int stage; /* Stage (1 or 2). */ | |
97 | ||
98 | int unlock_state; /* Guest writes 0x80, 0x86 to unlock the | |
99 | * registers, and we transition through | |
100 | * states 0 -> 1 -> 2 when this happens. | |
101 | */ | |
102 | ||
103 | int previous_reboot_flag; /* If the watchdog caused the previous | |
104 | * reboot, this flag will be set. | |
105 | */ | |
106 | }; | |
107 | ||
108 | typedef struct I6300State I6300State; | |
109 | ||
110 | /* This function is called when the watchdog has either been enabled | |
111 | * (hence it starts counting down) or has been keep-alived. | |
112 | */ | |
113 | static void i6300esb_restart_timer(I6300State *d, int stage) | |
114 | { | |
115 | int64_t timeout; | |
116 | ||
117 | if (!d->enabled) | |
118 | return; | |
119 | ||
120 | d->stage = stage; | |
121 | ||
122 | if (d->stage <= 1) | |
123 | timeout = d->timer1_preload; | |
124 | else | |
125 | timeout = d->timer2_preload; | |
126 | ||
127 | if (d->clock_scale == CLOCK_SCALE_1KHZ) | |
128 | timeout <<= 15; | |
129 | else | |
130 | timeout <<= 5; | |
131 | ||
132 | /* Get the timeout in units of ticks_per_sec. */ | |
133 | timeout = ticks_per_sec * timeout / 33000000; | |
134 | ||
135 | i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout); | |
136 | ||
137 | qemu_mod_timer(d->timer, qemu_get_clock(vm_clock) + timeout); | |
138 | } | |
139 | ||
140 | /* This is called when the guest disables the watchdog. */ | |
141 | static void i6300esb_disable_timer(I6300State *d) | |
142 | { | |
143 | i6300esb_debug("timer disabled\n"); | |
144 | ||
145 | qemu_del_timer(d->timer); | |
146 | } | |
147 | ||
148 | static void i6300esb_reset(I6300State *d) | |
149 | { | |
150 | /* XXX We should probably reset other parts of the state here, | |
151 | * but we should also reset our state on general machine reset | |
152 | * too. For now just disable the timer so it doesn't fire | |
153 | * again after the reboot. | |
154 | */ | |
155 | i6300esb_disable_timer(d); | |
156 | } | |
157 | ||
158 | /* This function is called when the watchdog expires. Note that | |
159 | * the hardware has two timers, and so expiry happens in two stages. | |
160 | * If d->stage == 1 then we perform the first stage action (usually, | |
161 | * sending an interrupt) and then restart the timer again for the | |
162 | * second stage. If the second stage expires then the watchdog | |
163 | * really has run out. | |
164 | */ | |
165 | static void i6300esb_timer_expired(void *vp) | |
166 | { | |
167 | I6300State *d = (I6300State *) vp; | |
168 | ||
169 | i6300esb_debug("stage %d\n", d->stage); | |
170 | ||
171 | if (d->stage == 1) { | |
172 | /* What to do at the end of stage 1? */ | |
173 | switch (d->int_type) { | |
174 | case INT_TYPE_IRQ: | |
175 | fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n"); | |
176 | break; | |
177 | case INT_TYPE_SMI: | |
178 | fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n"); | |
179 | break; | |
180 | } | |
181 | ||
182 | /* Start the second stage. */ | |
183 | i6300esb_restart_timer(d, 2); | |
184 | } else { | |
185 | /* Second stage expired, reboot for real. */ | |
186 | if (d->reboot_enabled) { | |
187 | d->previous_reboot_flag = 1; | |
188 | watchdog_perform_action(); /* This reboots, exits, etc */ | |
189 | i6300esb_reset(d); | |
190 | } | |
191 | ||
192 | /* In "free running mode" we start stage 1 again. */ | |
193 | if (d->free_run) | |
194 | i6300esb_restart_timer(d, 1); | |
195 | } | |
196 | } | |
197 | ||
198 | static void i6300esb_config_write(PCIDevice *dev, uint32_t addr, | |
199 | uint32_t data, int len) | |
200 | { | |
9d472d51 | 201 | I6300State *d = container_of(dev, I6300State, dev); |
9dd986cc RJ |
202 | int old; |
203 | ||
204 | i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len); | |
205 | ||
206 | if (addr == ESB_CONFIG_REG && len == 2) { | |
207 | d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0; | |
208 | d->clock_scale = | |
209 | (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ; | |
210 | d->int_type = (data & ESB_WDT_INTTYPE); | |
211 | } else if (addr == ESB_LOCK_REG && len == 1) { | |
212 | if (!d->locked) { | |
213 | d->locked = (data & ESB_WDT_LOCK) != 0; | |
214 | d->free_run = (data & ESB_WDT_FUNC) != 0; | |
215 | old = d->enabled; | |
216 | d->enabled = (data & ESB_WDT_ENABLE) != 0; | |
217 | if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */ | |
218 | i6300esb_restart_timer(d, 1); | |
219 | else if (!d->enabled) | |
220 | i6300esb_disable_timer(d); | |
221 | } | |
222 | } else { | |
223 | pci_default_write_config(dev, addr, data, len); | |
224 | } | |
225 | } | |
226 | ||
227 | static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len) | |
228 | { | |
9d472d51 | 229 | I6300State *d = container_of(dev, I6300State, dev); |
9dd986cc RJ |
230 | uint32_t data; |
231 | ||
232 | i6300esb_debug ("addr = %x, len = %d\n", addr, len); | |
233 | ||
234 | if (addr == ESB_CONFIG_REG && len == 2) { | |
235 | data = | |
236 | (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) | | |
237 | (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) | | |
238 | d->int_type; | |
239 | return data; | |
240 | } else if (addr == ESB_LOCK_REG && len == 1) { | |
241 | data = | |
242 | (d->free_run ? ESB_WDT_FUNC : 0) | | |
243 | (d->locked ? ESB_WDT_LOCK : 0) | | |
244 | (d->enabled ? ESB_WDT_ENABLE : 0); | |
245 | return data; | |
246 | } else { | |
247 | return pci_default_read_config(dev, addr, len); | |
248 | } | |
249 | } | |
250 | ||
251 | static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr) | |
252 | { | |
253 | i6300esb_debug ("addr = %x\n", (int) addr); | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
258 | static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr) | |
259 | { | |
260 | uint32_t data = 0; | |
261 | I6300State *d = (I6300State *) vp; | |
262 | ||
263 | i6300esb_debug("addr = %x\n", (int) addr); | |
264 | ||
265 | if (addr == 0xc) { | |
266 | /* The previous reboot flag is really bit 9, but there is | |
267 | * a bug in the Linux driver where it thinks it's bit 12. | |
268 | * Set both. | |
269 | */ | |
270 | data = d->previous_reboot_flag ? 0x1200 : 0; | |
271 | } | |
272 | ||
273 | return data; | |
274 | } | |
275 | ||
276 | static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr) | |
277 | { | |
278 | i6300esb_debug("addr = %x\n", (int) addr); | |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
283 | static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val) | |
284 | { | |
285 | I6300State *d = (I6300State *) vp; | |
286 | ||
287 | i6300esb_debug("addr = %x, val = %x\n", (int) addr, val); | |
288 | ||
289 | if (addr == 0xc && val == 0x80) | |
290 | d->unlock_state = 1; | |
291 | else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) | |
292 | d->unlock_state = 2; | |
293 | } | |
294 | ||
295 | static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val) | |
296 | { | |
297 | I6300State *d = (I6300State *) vp; | |
298 | ||
299 | i6300esb_debug("addr = %x, val = %x\n", (int) addr, val); | |
300 | ||
301 | if (addr == 0xc && val == 0x80) | |
302 | d->unlock_state = 1; | |
303 | else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) | |
304 | d->unlock_state = 2; | |
305 | else { | |
306 | if (d->unlock_state == 2) { | |
307 | if (addr == 0xc) { | |
308 | if ((val & 0x100) != 0) | |
309 | /* This is the "ping" from the userspace watchdog in | |
310 | * the guest ... | |
311 | */ | |
312 | i6300esb_restart_timer(d, 1); | |
313 | ||
314 | /* Setting bit 9 resets the previous reboot flag. | |
315 | * There's a bug in the Linux driver where it sets | |
316 | * bit 12 instead. | |
317 | */ | |
318 | if ((val & 0x200) != 0 || (val & 0x1000) != 0) { | |
319 | d->previous_reboot_flag = 0; | |
320 | } | |
321 | } | |
322 | ||
323 | d->unlock_state = 0; | |
324 | } | |
325 | } | |
326 | } | |
327 | ||
328 | static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val) | |
329 | { | |
330 | I6300State *d = (I6300State *) vp; | |
331 | ||
332 | i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val); | |
333 | ||
334 | if (addr == 0xc && val == 0x80) | |
335 | d->unlock_state = 1; | |
336 | else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) | |
337 | d->unlock_state = 2; | |
338 | else { | |
339 | if (d->unlock_state == 2) { | |
340 | if (addr == 0) | |
341 | d->timer1_preload = val & 0xfffff; | |
342 | else if (addr == 4) | |
343 | d->timer2_preload = val & 0xfffff; | |
344 | ||
345 | d->unlock_state = 0; | |
346 | } | |
347 | } | |
348 | } | |
349 | ||
350 | static void i6300esb_map(PCIDevice *dev, int region_num, | |
351 | uint32_t addr, uint32_t size, int type) | |
352 | { | |
d60efc6b | 353 | static CPUReadMemoryFunc * const mem_read[3] = { |
9dd986cc RJ |
354 | i6300esb_mem_readb, |
355 | i6300esb_mem_readw, | |
356 | i6300esb_mem_readl, | |
357 | }; | |
d60efc6b | 358 | static CPUWriteMemoryFunc * const mem_write[3] = { |
9dd986cc RJ |
359 | i6300esb_mem_writeb, |
360 | i6300esb_mem_writew, | |
361 | i6300esb_mem_writel, | |
362 | }; | |
9d472d51 | 363 | I6300State *d = container_of(dev, I6300State, dev); |
9dd986cc RJ |
364 | int io_mem; |
365 | ||
366 | i6300esb_debug("addr = %x, size = %x, type = %d\n", addr, size, type); | |
367 | ||
1eed09cb | 368 | io_mem = cpu_register_io_memory(mem_read, mem_write, d); |
9dd986cc RJ |
369 | cpu_register_physical_memory (addr, 0x10, io_mem); |
370 | /* qemu_register_coalesced_mmio (addr, 0x10); ? */ | |
371 | } | |
372 | ||
373 | static void i6300esb_save(QEMUFile *f, void *vp) | |
374 | { | |
375 | I6300State *d = (I6300State *) vp; | |
376 | ||
377 | pci_device_save(&d->dev, f); | |
378 | qemu_put_be32(f, d->reboot_enabled); | |
379 | qemu_put_be32(f, d->clock_scale); | |
380 | qemu_put_be32(f, d->int_type); | |
381 | qemu_put_be32(f, d->free_run); | |
382 | qemu_put_be32(f, d->locked); | |
383 | qemu_put_be32(f, d->enabled); | |
384 | qemu_put_timer(f, d->timer); | |
385 | qemu_put_be32(f, d->timer1_preload); | |
386 | qemu_put_be32(f, d->timer2_preload); | |
387 | qemu_put_be32(f, d->stage); | |
388 | qemu_put_be32(f, d->unlock_state); | |
389 | qemu_put_be32(f, d->previous_reboot_flag); | |
390 | } | |
391 | ||
392 | static int i6300esb_load(QEMUFile *f, void *vp, int version) | |
393 | { | |
394 | I6300State *d = (I6300State *) vp; | |
395 | ||
396 | if (version != sizeof (I6300State)) | |
397 | return -EINVAL; | |
398 | ||
399 | pci_device_load(&d->dev, f); | |
400 | d->reboot_enabled = qemu_get_be32(f); | |
401 | d->clock_scale = qemu_get_be32(f); | |
402 | d->int_type = qemu_get_be32(f); | |
403 | d->free_run = qemu_get_be32(f); | |
404 | d->locked = qemu_get_be32(f); | |
405 | d->enabled = qemu_get_be32(f); | |
406 | qemu_get_timer(f, d->timer); | |
407 | d->timer1_preload = qemu_get_be32(f); | |
408 | d->timer2_preload = qemu_get_be32(f); | |
409 | d->stage = qemu_get_be32(f); | |
410 | d->unlock_state = qemu_get_be32(f); | |
411 | d->previous_reboot_flag = qemu_get_be32(f); | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
81a322d4 | 416 | static int i6300esb_init(PCIDevice *dev) |
9dd986cc | 417 | { |
09aaa160 | 418 | I6300State *d = container_of(dev, I6300State, dev); |
9dd986cc RJ |
419 | uint8_t *pci_conf; |
420 | ||
9dd986cc RJ |
421 | d->reboot_enabled = 1; |
422 | d->clock_scale = CLOCK_SCALE_1KHZ; | |
423 | d->int_type = INT_TYPE_IRQ; | |
424 | d->free_run = 0; | |
425 | d->locked = 0; | |
426 | d->enabled = 0; | |
427 | d->timer = qemu_new_timer(vm_clock, i6300esb_timer_expired, d); | |
428 | d->timer1_preload = 0xfffff; | |
429 | d->timer2_preload = 0xfffff; | |
430 | d->stage = 1; | |
431 | d->unlock_state = 0; | |
432 | d->previous_reboot_flag = 0; | |
433 | ||
434 | pci_conf = d->dev.config; | |
435 | pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); | |
436 | pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ESB_9); | |
437 | pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); | |
438 | pci_conf[0x0e] = 0x00; | |
439 | ||
28c2c264 | 440 | pci_register_bar(&d->dev, 0, 0x10, |
9dd986cc RJ |
441 | PCI_ADDRESS_SPACE_MEM, i6300esb_map); |
442 | ||
443 | register_savevm("i6300esb_wdt", -1, sizeof(I6300State), | |
444 | i6300esb_save, i6300esb_load, d); | |
81a322d4 GH |
445 | |
446 | return 0; | |
9dd986cc RJ |
447 | } |
448 | ||
449 | static WatchdogTimerModel model = { | |
450 | .wdt_name = "i6300esb", | |
451 | .wdt_description = "Intel 6300ESB", | |
9dd986cc RJ |
452 | }; |
453 | ||
09aaa160 MA |
454 | static PCIDeviceInfo i6300esb_info = { |
455 | .qdev.name = "i6300esb", | |
456 | .qdev.size = sizeof(I6300State), | |
457 | .config_read = i6300esb_config_read, | |
458 | .config_write = i6300esb_config_write, | |
459 | .init = i6300esb_init, | |
460 | }; | |
461 | ||
462 | static void i6300esb_register_devices(void) | |
9dd986cc RJ |
463 | { |
464 | watchdog_add_model(&model); | |
09aaa160 | 465 | pci_qdev_register(&i6300esb_info); |
9dd986cc | 466 | } |
09aaa160 MA |
467 | |
468 | device_init(i6300esb_register_devices); |