[qemu.git] / hw / xen_platform.c

/*
 * XEN platform pci device, formerly known as the event channel device
 *
 * Copyright (c) 2003-2004 Intel Corp.
 * Copyright (c) 2006 XenSource
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include <assert.h>

#include "hw.h"
#include "pc.h"
#include "pci.h"
#include "irq.h"
#include "xen_common.h"
#include "net.h"
#include "xen_backend.h"
#include "trace.h"
#include "exec-memory.h"

#include <xenguest.h>

//#define DEBUG_PLATFORM

#ifdef DEBUG_PLATFORM
#define DPRINTF(fmt, ...) do { \
    fprintf(stderr, "xen_platform: " fmt, ## __VA_ARGS__); \
} while (0)
#else
#define DPRINTF(fmt, ...) do { } while (0)
#endif

#define PFFLAG_ROM_LOCK 1 /* Sets whether ROM memory area is RW or RO */

typedef struct PCIXenPlatformState {
    PCIDevice  pci_dev;
    MemoryRegion fixed_io;
    MemoryRegion bar;
    MemoryRegion mmio_bar;
    uint8_t flags; /* used only for version_id == 2 */
    int drivers_blacklisted;
    uint16_t driver_product_version;

    /* Log from guest drivers */
    char log_buffer[4096];
    int log_buffer_off;
} PCIXenPlatformState;

#define XEN_PLATFORM_IOPORT 0x10

/* Send bytes to syslog */
static void log_writeb(PCIXenPlatformState *s, char val)
{
    if (val == '\n' || s->log_buffer_off == sizeof(s->log_buffer) - 1) {
        /* Flush buffer */
        s->log_buffer[s->log_buffer_off] = 0;
        trace_xen_platform_log(s->log_buffer);
        s->log_buffer_off = 0;
    } else {
        s->log_buffer[s->log_buffer_off++] = val;
    }
}

/* Xen Platform, Fixed IOPort */
#define UNPLUG_ALL_IDE_DISKS 1
#define UNPLUG_ALL_NICS 2
#define UNPLUG_AUX_IDE_DISKS 4

static void unplug_nic(PCIBus *b, PCIDevice *d)
{
    if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
            PCI_CLASS_NETWORK_ETHERNET) {
        qdev_unplug(&(d->qdev), NULL);
    }
}

static void pci_unplug_nics(PCIBus *bus)
{
    pci_for_each_device(bus, 0, unplug_nic);
}

static void unplug_disks(PCIBus *b, PCIDevice *d)
{
    if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
            PCI_CLASS_STORAGE_IDE) {
        qdev_unplug(&(d->qdev), NULL);
    }
}

static void pci_unplug_disks(PCIBus *bus)
{
    pci_for_each_device(bus, 0, unplug_disks);
}

static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0:
        /* Unplug devices.  Value is a bitmask of which devices to
           unplug, with bit 0 the IDE devices, bit 1 the network
           devices, and bit 2 the non-primary-master IDE devices. */
        if (val & UNPLUG_ALL_IDE_DISKS) {
            DPRINTF("unplug disks\n");
            bdrv_drain_all();
            bdrv_flush_all();
            pci_unplug_disks(s->pci_dev.bus);
        }
        if (val & UNPLUG_ALL_NICS) {
            DPRINTF("unplug nics\n");
            pci_unplug_nics(s->pci_dev.bus);
        }
        if (val & UNPLUG_AUX_IDE_DISKS) {
            DPRINTF("unplug auxiliary disks not supported\n");
        }
        break;
    case 2:
        switch (val) {
        case 1:
            DPRINTF("Citrix Windows PV drivers loaded in guest\n");
            break;
        case 0:
            DPRINTF("Guest claimed to be running PV product 0?\n");
            break;
        default:
            DPRINTF("Unknown PV product %d loaded in guest\n", val);
            break;
        }
        s->driver_product_version = val;
        break;
    }
}

static void platform_fixed_ioport_writel(void *opaque, uint32_t addr,
                                         uint32_t val)
{
    switch (addr) {
    case 0:
        /* PV driver version */
        break;
    }
}

static void platform_fixed_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0: /* Platform flags */ {
        hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
            HVMMEM_ram_ro : HVMMEM_ram_rw;
        if (xc_hvm_set_mem_type(xen_xc, xen_domid, mem_type, 0xc0, 0x40)) {
            DPRINTF("unable to change ro/rw state of ROM memory area!\n");
        } else {
            s->flags = val & PFFLAG_ROM_LOCK;
            DPRINTF("changed ro/rw state of ROM memory area. now is %s state.\n",
                    (mem_type == HVMMEM_ram_ro ? "ro":"rw"));
        }
        break;
    }
    case 2:
        log_writeb(s, val);
        break;
    }
}

static uint32_t platform_fixed_ioport_readw(void *opaque, uint32_t addr)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0:
        if (s->drivers_blacklisted) {
            /* The drivers will recognise this magic number and refuse
             * to do anything. */
            return 0xd249;
        } else {
            /* Magic value so that you can identify the interface. */
            return 0x49d2;
        }
    default:
        return 0xffff;
    }
}

static uint32_t platform_fixed_ioport_readb(void *opaque, uint32_t addr)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0:
        /* Platform flags */
        return s->flags;
    case 2:
        /* Version number */
        return 1;
    default:
        return 0xff;
    }
}

static void platform_fixed_ioport_reset(void *opaque)
{
    PCIXenPlatformState *s = opaque;

    platform_fixed_ioport_writeb(s, 0, 0);
}

const MemoryRegionPortio xen_platform_ioport[] = {
    { 0, 16, 4, .write = platform_fixed_ioport_writel, },
    { 0, 16, 2, .write = platform_fixed_ioport_writew, },
    { 0, 16, 1, .write = platform_fixed_ioport_writeb, },
    { 0, 16, 2, .read = platform_fixed_ioport_readw, },
    { 0, 16, 1, .read = platform_fixed_ioport_readb, },
    PORTIO_END_OF_LIST()
};

static const MemoryRegionOps platform_fixed_io_ops = {
    .old_portio = xen_platform_ioport,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void platform_fixed_ioport_init(PCIXenPlatformState* s)
{
    memory_region_init_io(&s->fixed_io, &platform_fixed_io_ops, s,
                          "xen-fixed", 16);
    memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
                                &s->fixed_io);
}

/* Xen Platform PCI Device */

static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
{
    if (addr == 0) {
        return platform_fixed_ioport_readb(opaque, 0);
    } else {
        return ~0u;
    }
}

static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
{
    PCIXenPlatformState *s = opaque;

    switch (addr) {
    case 0: /* Platform flags */
        platform_fixed_ioport_writeb(opaque, 0, val);
        break;
    case 8:
        log_writeb(s, val);
        break;
    default:
        break;
    }
}

static MemoryRegionPortio xen_pci_portio[] = {
    { 0, 0x100, 1, .read = xen_platform_ioport_readb, },
    { 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
    PORTIO_END_OF_LIST()
};

static const MemoryRegionOps xen_pci_io_ops = {
    .old_portio = xen_pci_portio,
};

static void platform_ioport_bar_setup(PCIXenPlatformState *d)
{
    memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
}

static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
                                   unsigned size)
{
    DPRINTF("Warning: attempted read from physical address "
            "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);

    return 0;
}

static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
                                uint64_t val, unsigned size)
{
    DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
            "address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
            val, addr);
}

static const MemoryRegionOps platform_mmio_handler = {
    .read = &platform_mmio_read,
    .write = &platform_mmio_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void platform_mmio_setup(PCIXenPlatformState *d)
{
    memory_region_init_io(&d->mmio_bar, &platform_mmio_handler, d,
                          "xen-mmio", 0x1000000);
}

static int xen_platform_post_load(void *opaque, int version_id)
{
    PCIXenPlatformState *s = opaque;

    platform_fixed_ioport_writeb(s, 0, s->flags);

    return 0;
}

static const VMStateDescription vmstate_xen_platform = {
    .name = "platform",
    .version_id = 4,
    .minimum_version_id = 4,
    .minimum_version_id_old = 4,
    .post_load = xen_platform_post_load,
    .fields = (VMStateField []) {
        VMSTATE_PCI_DEVICE(pci_dev, PCIXenPlatformState),
        VMSTATE_UINT8(flags, PCIXenPlatformState),
        VMSTATE_END_OF_LIST()
    }
};

static int xen_platform_initfn(PCIDevice *dev)
{
    PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, dev);
    uint8_t *pci_conf;

    pci_conf = d->pci_dev.config;

    pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);

    pci_config_set_prog_interface(pci_conf, 0);

    pci_conf[PCI_INTERRUPT_PIN] = 1;

    platform_ioport_bar_setup(d);
    pci_register_bar(&d->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);

    /* reserve 16MB mmio address for share memory*/
    platform_mmio_setup(d);
    pci_register_bar(&d->pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
                     &d->mmio_bar);

    platform_fixed_ioport_init(d);

    return 0;
}

static void platform_reset(DeviceState *dev)
{
    PCIXenPlatformState *s = DO_UPCAST(PCIXenPlatformState, pci_dev.qdev, dev);

    platform_fixed_ioport_reset(s);
}

static void xen_platform_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);

    k->init = xen_platform_initfn;
    k->vendor_id = PCI_VENDOR_ID_XEN;
    k->device_id = PCI_DEVICE_ID_XEN_PLATFORM;
    k->class_id = PCI_CLASS_OTHERS << 8 | 0x80;
    k->subsystem_vendor_id = PCI_VENDOR_ID_XEN;
    k->subsystem_id = PCI_DEVICE_ID_XEN_PLATFORM;
    k->revision = 1;
    dc->desc = "XEN platform pci device";
    dc->reset = platform_reset;
    dc->vmsd = &vmstate_xen_platform;
}

static TypeInfo xen_platform_info = {
    .name          = "xen-platform",
    .parent        = TYPE_PCI_DEVICE,
    .instance_size = sizeof(PCIXenPlatformState),
    .class_init    = xen_platform_class_init,
};

static void xen_platform_register_types(void)
{
    type_register_static(&xen_platform_info);
}

type_init(xen_platform_register_types)
Commit	Line	Data
01195b73 SS	1	/*
	2	* XEN platform pci device, formerly known as the event channel device
	3	*
	4	* Copyright (c) 2003-2004 Intel Corp.
	5	* Copyright (c) 2006 XenSource
	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
	26	#include <assert.h>
	27
	28	#include "hw.h"
	29	#include "pc.h"
	30	#include "pci.h"
	31	#include "irq.h"
	32	#include "xen_common.h"
	33	#include "net.h"
	34	#include "xen_backend.h"
01195b73	35	#include "trace.h"
de00982e	36	#include "exec-memory.h"
01195b73 SS	37
	38	#include <xenguest.h>
	39
	40	//#define DEBUG_PLATFORM
	41
	42	#ifdef DEBUG_PLATFORM
	43	#define DPRINTF(fmt, ...) do { \
	44	fprintf(stderr, "xen_platform: " fmt, ## __VA_ARGS__); \
	45	} while (0)
	46	#else
	47	#define DPRINTF(fmt, ...) do { } while (0)
	48	#endif
	49
	50	#define PFFLAG_ROM_LOCK 1 /* Sets whether ROM memory area is RW or RO */
	51
	52	typedef struct PCIXenPlatformState {
	53	PCIDevice pci_dev;
de00982e AK	54	MemoryRegion fixed_io;
	55	MemoryRegion bar;
	56	MemoryRegion mmio_bar;
01195b73 SS	57	uint8_t flags; /* used only for version_id == 2 */
	58	int drivers_blacklisted;
	59	uint16_t driver_product_version;
	60
	61	/* Log from guest drivers */
	62	char log_buffer[4096];
	63	int log_buffer_off;
	64	} PCIXenPlatformState;
	65
	66	#define XEN_PLATFORM_IOPORT 0x10
	67
	68	/* Send bytes to syslog */
	69	static void log_writeb(PCIXenPlatformState *s, char val)
	70	{
	71	if (val == '\n' \|\| s->log_buffer_off == sizeof(s->log_buffer) - 1) {
	72	/* Flush buffer */
	73	s->log_buffer[s->log_buffer_off] = 0;
	74	trace_xen_platform_log(s->log_buffer);
	75	s->log_buffer_off = 0;
	76	} else {
	77	s->log_buffer[s->log_buffer_off++] = val;
	78	}
	79	}
	80
	81	/* Xen Platform, Fixed IOPort */
679f4f8b SS	82	#define UNPLUG_ALL_IDE_DISKS 1
	83	#define UNPLUG_ALL_NICS 2
	84	#define UNPLUG_AUX_IDE_DISKS 4
	85
	86	static void unplug_nic(PCIBus b, PCIDevice d)
	87	{
	88	if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
	89	PCI_CLASS_NETWORK_ETHERNET) {
56f9107e	90	qdev_unplug(&(d->qdev), NULL);
679f4f8b SS	91	}
	92	}
	93
	94	static void pci_unplug_nics(PCIBus *bus)
	95	{
	96	pci_for_each_device(bus, 0, unplug_nic);
	97	}
	98
	99	static void unplug_disks(PCIBus b, PCIDevice d)
	100	{
	101	if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
	102	PCI_CLASS_STORAGE_IDE) {
56f9107e	103	qdev_unplug(&(d->qdev), NULL);
679f4f8b SS	104	}
	105	}
	106
	107	static void pci_unplug_disks(PCIBus *bus)
	108	{
	109	pci_for_each_device(bus, 0, unplug_disks);
	110	}
01195b73 SS	111
	112	static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
	113	{
	114	PCIXenPlatformState *s = opaque;
	115
e7b48c97	116	switch (addr) {
01195b73	117	case 0:
01195b73 SS	118	/* Unplug devices. Value is a bitmask of which devices to
	119	unplug, with bit 0 the IDE devices, bit 1 the network
	120	devices, and bit 2 the non-primary-master IDE devices. */
679f4f8b SS	121	if (val & UNPLUG_ALL_IDE_DISKS) {
679f4f8b SS	122	DPRINTF("unplug disks\n");
922453bc	123	bdrv_drain_all();
679f4f8b SS	124	bdrv_flush_all();
	125	pci_unplug_disks(s->pci_dev.bus);
	126	}
	127	if (val & UNPLUG_ALL_NICS) {
	128	DPRINTF("unplug nics\n");
	129	pci_unplug_nics(s->pci_dev.bus);
	130	}
	131	if (val & UNPLUG_AUX_IDE_DISKS) {
	132	DPRINTF("unplug auxiliary disks not supported\n");
	133	}
01195b73 SS	134	break;
	135	case 2:
	136	switch (val) {
	137	case 1:
	138	DPRINTF("Citrix Windows PV drivers loaded in guest\n");
	139	break;
	140	case 0:
	141	DPRINTF("Guest claimed to be running PV product 0?\n");
	142	break;
	143	default:
	144	DPRINTF("Unknown PV product %d loaded in guest\n", val);
	145	break;
	146	}
	147	s->driver_product_version = val;
	148	break;
	149	}
	150	}
	151
	152	static void platform_fixed_ioport_writel(void *opaque, uint32_t addr,
	153	uint32_t val)
	154	{
e7b48c97	155	switch (addr) {
01195b73 SS	156	case 0:
	157	/* PV driver version */
	158	break;
	159	}
	160	}
	161
	162	static void platform_fixed_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
	163	{
	164	PCIXenPlatformState *s = opaque;
	165
e7b48c97	166	switch (addr) {
01195b73 SS	167	case 0: /* Platform flags */ {
	168	hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
	169	HVMMEM_ram_ro : HVMMEM_ram_rw;
	170	if (xc_hvm_set_mem_type(xen_xc, xen_domid, mem_type, 0xc0, 0x40)) {
	171	DPRINTF("unable to change ro/rw state of ROM memory area!\n");
	172	} else {
	173	s->flags = val & PFFLAG_ROM_LOCK;
	174	DPRINTF("changed ro/rw state of ROM memory area. now is %s state.\n",
	175	(mem_type == HVMMEM_ram_ro ? "ro":"rw"));
	176	}
	177	break;
	178	}
	179	case 2:
	180	log_writeb(s, val);
	181	break;
	182	}
	183	}
	184
	185	static uint32_t platform_fixed_ioport_readw(void *opaque, uint32_t addr)
	186	{
	187	PCIXenPlatformState *s = opaque;
	188
e7b48c97	189	switch (addr) {
01195b73 SS	190	case 0:
	191	if (s->drivers_blacklisted) {
	192	/* The drivers will recognise this magic number and refuse
	193	* to do anything. */
	194	return 0xd249;
	195	} else {
	196	/* Magic value so that you can identify the interface. */
	197	return 0x49d2;
	198	}
	199	default:
	200	return 0xffff;
	201	}
	202	}
	203
	204	static uint32_t platform_fixed_ioport_readb(void *opaque, uint32_t addr)
	205	{
	206	PCIXenPlatformState *s = opaque;
	207
e7b48c97	208	switch (addr) {
01195b73 SS	209	case 0:
	210	/* Platform flags */
	211	return s->flags;
	212	case 2:
	213	/* Version number */
	214	return 1;
	215	default:
	216	return 0xff;
	217	}
	218	}
	219
	220	static void platform_fixed_ioport_reset(void *opaque)
	221	{
	222	PCIXenPlatformState *s = opaque;
	223
e7b48c97	224	platform_fixed_ioport_writeb(s, 0, 0);
01195b73 SS	225	}
01195b73 SS	226
de00982e AK	227	const MemoryRegionPortio xen_platform_ioport[] = {
	228	{ 0, 16, 4, .write = platform_fixed_ioport_writel, },
	229	{ 0, 16, 2, .write = platform_fixed_ioport_writew, },
	230	{ 0, 16, 1, .write = platform_fixed_ioport_writeb, },
	231	{ 0, 16, 2, .read = platform_fixed_ioport_readw, },
	232	{ 0, 16, 1, .read = platform_fixed_ioport_readb, },
	233	PORTIO_END_OF_LIST()
	234	};
	235
	236	static const MemoryRegionOps platform_fixed_io_ops = {
	237	.old_portio = xen_platform_ioport,
	238	.endianness = DEVICE_NATIVE_ENDIAN,
	239	};
	240
01195b73 SS	241	static void platform_fixed_ioport_init(PCIXenPlatformState* s)
01195b73 SS	242	{
de00982e AK	243	memory_region_init_io(&s->fixed_io, &platform_fixed_io_ops, s,
	244	"xen-fixed", 16);
	245	memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
	246	&s->fixed_io);
01195b73 SS	247	}
	248
	249	/* Xen Platform PCI Device */
	250
	251	static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
	252	{
01195b73	253	if (addr == 0) {
e7b48c97	254	return platform_fixed_ioport_readb(opaque, 0);
01195b73 SS	255	} else {
	256	return ~0u;
	257	}
	258	}
	259
	260	static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
	261	{
	262	PCIXenPlatformState *s = opaque;
	263
01195b73 SS	264	switch (addr) {
01195b73 SS	265	case 0: /* Platform flags */
e7b48c97	266	platform_fixed_ioport_writeb(opaque, 0, val);
01195b73 SS	267	break;
	268	case 8:
	269	log_writeb(s, val);
	270	break;
	271	default:
	272	break;
	273	}
	274	}
	275
de00982e AK	276	static MemoryRegionPortio xen_pci_portio[] = {
	277	{ 0, 0x100, 1, .read = xen_platform_ioport_readb, },
	278	{ 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
	279	PORTIO_END_OF_LIST()
	280	};
	281
	282	static const MemoryRegionOps xen_pci_io_ops = {
	283	.old_portio = xen_pci_portio,
	284	};
01195b73	285
de00982e AK	286	static void platform_ioport_bar_setup(PCIXenPlatformState *d)
	287	{
	288	memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
01195b73 SS	289	}
01195b73 SS	290
de00982e AK	291	static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
de00982e AK	292	unsigned size)
01195b73 SS	293	{
	294	DPRINTF("Warning: attempted read from physical address "
	295	"0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
	296
	297	return 0;
	298	}
	299
de00982e AK	300	static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
de00982e AK	301	uint64_t val, unsigned size)
01195b73	302	{
de00982e	303	DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
01195b73 SS	304	"address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
	305	val, addr);
	306	}
	307
de00982e	308	static const MemoryRegionOps platform_mmio_handler = {
01195b73 SS	309	.read = &platform_mmio_read,
01195b73 SS	310	.write = &platform_mmio_write,
de00982e	311	.endianness = DEVICE_NATIVE_ENDIAN,
01195b73 SS	312	};
01195b73 SS	313
de00982e	314	static void platform_mmio_setup(PCIXenPlatformState *d)
01195b73	315	{
de00982e AK	316	memory_region_init_io(&d->mmio_bar, &platform_mmio_handler, d,
de00982e AK	317	"xen-mmio", 0x1000000);
01195b73 SS	318	}
	319
	320	static int xen_platform_post_load(void *opaque, int version_id)
	321	{
	322	PCIXenPlatformState *s = opaque;
	323
e7b48c97	324	platform_fixed_ioport_writeb(s, 0, s->flags);
01195b73 SS	325
	326	return 0;
	327	}
	328
	329	static const VMStateDescription vmstate_xen_platform = {
	330	.name = "platform",
	331	.version_id = 4,
	332	.minimum_version_id = 4,
	333	.minimum_version_id_old = 4,
	334	.post_load = xen_platform_post_load,
	335	.fields = (VMStateField []) {
	336	VMSTATE_PCI_DEVICE(pci_dev, PCIXenPlatformState),
	337	VMSTATE_UINT8(flags, PCIXenPlatformState),
	338	VMSTATE_END_OF_LIST()
	339	}
	340	};
	341
	342	static int xen_platform_initfn(PCIDevice *dev)
	343	{
	344	PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, dev);
	345	uint8_t *pci_conf;
	346
	347	pci_conf = d->pci_dev.config;
	348
01195b73 SS	349	pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO \| PCI_COMMAND_MEMORY);
01195b73 SS	350
01195b73 SS	351	pci_config_set_prog_interface(pci_conf, 0);
01195b73 SS	352
01195b73 SS	353	pci_conf[PCI_INTERRUPT_PIN] = 1;
01195b73 SS	354
de00982e	355	platform_ioport_bar_setup(d);
e824b2cc	356	pci_register_bar(&d->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
01195b73 SS	357
01195b73 SS	358	/* reserve 16MB mmio address for share memory*/
de00982e	359	platform_mmio_setup(d);
e824b2cc AK	360	pci_register_bar(&d->pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
e824b2cc AK	361	&d->mmio_bar);
01195b73 SS	362
	363	platform_fixed_ioport_init(d);
	364
	365	return 0;
	366	}
	367
	368	static void platform_reset(DeviceState *dev)
	369	{
	370	PCIXenPlatformState *s = DO_UPCAST(PCIXenPlatformState, pci_dev.qdev, dev);
	371
	372	platform_fixed_ioport_reset(s);
	373	}
	374
40021f08 AL	375	static void xen_platform_class_init(ObjectClass klass, void data)
40021f08 AL	376	{
39bffca2	377	DeviceClass *dc = DEVICE_CLASS(klass);
40021f08 AL	378	PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
	379
	380	k->init = xen_platform_initfn;
	381	k->vendor_id = PCI_VENDOR_ID_XEN;
	382	k->device_id = PCI_DEVICE_ID_XEN_PLATFORM;
	383	k->class_id = PCI_CLASS_OTHERS << 8 \| 0x80;
	384	k->subsystem_vendor_id = PCI_VENDOR_ID_XEN;
	385	k->subsystem_id = PCI_DEVICE_ID_XEN_PLATFORM;
	386	k->revision = 1;
39bffca2 AL	387	dc->desc = "XEN platform pci device";
	388	dc->reset = platform_reset;
	389	dc->vmsd = &vmstate_xen_platform;
40021f08 AL	390	}
40021f08 AL	391
39bffca2 AL	392	static TypeInfo xen_platform_info = {
	393	.name = "xen-platform",
	394	.parent = TYPE_PCI_DEVICE,
	395	.instance_size = sizeof(PCIXenPlatformState),
	396	.class_init = xen_platform_class_init,
01195b73 SS	397	};
01195b73 SS	398
83f7d43a	399	static void xen_platform_register_types(void)
01195b73	400	{
39bffca2	401	type_register_static(&xen_platform_info);
01195b73 SS	402	}
01195b73 SS	403
83f7d43a	404	type_init(xen_platform_register_types)