[qemu.git] / hw / xics.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
 *
 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */

#include "hw.h"
#include "hw/spapr.h"
#include "hw/xics.h"

/*
 * ICP: Presentation layer
 */

struct icp_server_state {
    uint32_t xirr;
    uint8_t pending_priority;
    uint8_t mfrr;
    qemu_irq output;
};

#define XISR_MASK  0x00ffffff
#define CPPR_MASK  0xff000000

#define XISR(ss)   (((ss)->xirr) & XISR_MASK)
#define CPPR(ss)   (((ss)->xirr) >> 24)

struct ics_state;

struct icp_state {
    long nr_servers;
    struct icp_server_state *ss;
    struct ics_state *ics;
};

static void ics_reject(struct ics_state *ics, int nr);
static void ics_resend(struct ics_state *ics);
static void ics_eoi(struct ics_state *ics, int nr);

static void icp_check_ipi(struct icp_state *icp, int server)
{
    struct icp_server_state *ss = icp->ss + server;

    if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
        return;
    }

    if (XISR(ss)) {
        ics_reject(icp->ics, XISR(ss));
    }

    ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
    ss->pending_priority = ss->mfrr;
    qemu_irq_raise(ss->output);
}

static void icp_resend(struct icp_state *icp, int server)
{
    struct icp_server_state *ss = icp->ss + server;

    if (ss->mfrr < CPPR(ss)) {
        icp_check_ipi(icp, server);
    }
    ics_resend(icp->ics);
}

static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
{
    struct icp_server_state *ss = icp->ss + server;
    uint8_t old_cppr;
    uint32_t old_xisr;

    old_cppr = CPPR(ss);
    ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);

    if (cppr < old_cppr) {
        if (XISR(ss) && (cppr <= ss->pending_priority)) {
            old_xisr = XISR(ss);
            ss->xirr &= ~XISR_MASK; /* Clear XISR */
            qemu_irq_lower(ss->output);
            ics_reject(icp->ics, old_xisr);
        }
    } else {
        if (!XISR(ss)) {
            icp_resend(icp, server);
        }
    }
}

static void icp_set_mfrr(struct icp_state *icp, int nr, uint8_t mfrr)
{
    struct icp_server_state *ss = icp->ss + nr;

    ss->mfrr = mfrr;
    if (mfrr < CPPR(ss)) {
        icp_check_ipi(icp, nr);
    }
}

static uint32_t icp_accept(struct icp_server_state *ss)
{
    uint32_t xirr;

    qemu_irq_lower(ss->output);
    xirr = ss->xirr;
    ss->xirr = ss->pending_priority << 24;
    return xirr;
}

static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
{
    struct icp_server_state *ss = icp->ss + server;

    /* Send EOI -> ICS */
    ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
    ics_eoi(icp->ics, xirr & XISR_MASK);
    if (!XISR(ss)) {
        icp_resend(icp, server);
    }
}

static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
{
    struct icp_server_state *ss = icp->ss + server;

    if ((priority >= CPPR(ss))
        || (XISR(ss) && (ss->pending_priority <= priority))) {
        ics_reject(icp->ics, nr);
    } else {
        if (XISR(ss)) {
            ics_reject(icp->ics, XISR(ss));
        }
        ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
        ss->pending_priority = priority;
        qemu_irq_raise(ss->output);
    }
}

/*
 * ICS: Source layer
 */

struct ics_irq_state {
    int server;
    uint8_t priority;
    uint8_t saved_priority;
    enum xics_irq_type type;
    int asserted:1;
    int sent:1;
    int rejected:1;
    int masked_pending:1;
};

struct ics_state {
    int nr_irqs;
    int offset;
    qemu_irq *qirqs;
    struct ics_irq_state *irqs;
    struct icp_state *icp;
};

static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
{
    return (nr >= ics->offset)
        && (nr < (ics->offset + ics->nr_irqs));
}

static void resend_msi(struct ics_state *ics, int srcno)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    /* FIXME: filter by server#? */
    if (irq->rejected) {
        irq->rejected = 0;
        if (irq->priority != 0xff) {
            icp_irq(ics->icp, irq->server, srcno + ics->offset,
                    irq->priority);
        }
    }
}

static void resend_lsi(struct ics_state *ics, int srcno)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    if ((irq->priority != 0xff) && irq->asserted && !irq->sent) {
        irq->sent = 1;
        icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
    }
}

static void set_irq_msi(struct ics_state *ics, int srcno, int val)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (val) {
        if (irq->priority == 0xff) {
            irq->masked_pending = 1;
            /* masked pending */ ;
        } else  {
            icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
        }
    }
}

static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    irq->asserted = val;
    resend_lsi(ics, srcno);
}

static void ics_set_irq(void *opaque, int srcno, int val)
{
    struct ics_state *ics = (struct ics_state *)opaque;
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (irq->type == XICS_LSI) {
        set_irq_lsi(ics, srcno, val);
    } else {
        set_irq_msi(ics, srcno, val);
    }
}

static void write_xive_msi(struct ics_state *ics, int srcno)
{
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (!irq->masked_pending || (irq->priority == 0xff)) {
        return;
    }

    irq->masked_pending = 0;
    icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
}

static void write_xive_lsi(struct ics_state *ics, int srcno)
{
    resend_lsi(ics, srcno);
}

static void ics_write_xive(struct ics_state *ics, int nr, int server,
                           uint8_t priority)
{
    int srcno = nr - ics->offset;
    struct ics_irq_state *irq = ics->irqs + srcno;

    irq->server = server;
    irq->priority = priority;

    if (irq->type == XICS_LSI) {
        write_xive_lsi(ics, srcno);
    } else {
        write_xive_msi(ics, srcno);
    }
}

static void ics_reject(struct ics_state *ics, int nr)
{
    struct ics_irq_state *irq = ics->irqs + nr - ics->offset;

    irq->rejected = 1; /* Irrelevant but harmless for LSI */
    irq->sent = 0; /* Irrelevant but harmless for MSI */
}

static void ics_resend(struct ics_state *ics)
{
    int i;

    for (i = 0; i < ics->nr_irqs; i++) {
        struct ics_irq_state *irq = ics->irqs + i;

        /* FIXME: filter by server#? */
        if (irq->type == XICS_LSI) {
            resend_lsi(ics, i);
        } else {
            resend_msi(ics, i);
        }
    }
}

static void ics_eoi(struct ics_state *ics, int nr)
{
    int srcno = nr - ics->offset;
    struct ics_irq_state *irq = ics->irqs + srcno;

    if (irq->type == XICS_LSI) {
        irq->sent = 0;
    }
}

/*
 * Exported functions
 */

qemu_irq xics_assign_irq(struct icp_state *icp, int irq,
                         enum xics_irq_type type)
{
    if ((irq < icp->ics->offset)
        || (irq >= (icp->ics->offset + icp->ics->nr_irqs))) {
        return NULL;
    }

    assert((type == XICS_MSI) || (type == XICS_LSI));

    icp->ics->irqs[irq - icp->ics->offset].type = type;
    return icp->ics->qirqs[irq - icp->ics->offset];
}

static target_ulong h_cppr(CPUPPCState *env, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    target_ulong cppr = args[0];

    icp_set_cppr(spapr->icp, env->cpu_index, cppr);
    return H_SUCCESS;
}

static target_ulong h_ipi(CPUPPCState *env, sPAPREnvironment *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong server = args[0];
    target_ulong mfrr = args[1];

    if (server >= spapr->icp->nr_servers) {
        return H_PARAMETER;
    }

    icp_set_mfrr(spapr->icp, server, mfrr);
    return H_SUCCESS;

}

static target_ulong h_xirr(CPUPPCState *env, sPAPREnvironment *spapr,
                           target_ulong opcode, target_ulong *args)
{
    uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index);

    args[0] = xirr;
    return H_SUCCESS;
}

static target_ulong h_eoi(CPUPPCState *env, sPAPREnvironment *spapr,
                          target_ulong opcode, target_ulong *args)
{
    target_ulong xirr = args[0];

    icp_eoi(spapr->icp, env->cpu_index, xirr);
    return H_SUCCESS;
}

static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr, server, priority;

    if ((nargs != 3) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);
    server = rtas_ld(args, 1);
    priority = rtas_ld(args, 2);

    if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
        || (priority > 0xff)) {
        rtas_st(rets, 0, -3);
        return;
    }

    ics_write_xive(ics, nr, server, priority);

    rtas_st(rets, 0, 0); /* Success */
}

static void rtas_get_xive(sPAPREnvironment *spapr, uint32_t token,
                          uint32_t nargs, target_ulong args,
                          uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 3)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    rtas_st(rets, 0, 0); /* Success */
    rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
    rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
}

static void rtas_int_off(sPAPREnvironment *spapr, uint32_t token,
                         uint32_t nargs, target_ulong args,
                         uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    /* This is a NOP for now, since the described PAPR semantics don't
     * seem to gel with what Linux does */
#if 0
    struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);

    irq->saved_priority = irq->priority;
    ics_write_xive_msi(xics, nr, irq->server, 0xff);
#endif

    rtas_st(rets, 0, 0); /* Success */
}

static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token,
                        uint32_t nargs, target_ulong args,
                        uint32_t nret, target_ulong rets)
{
    struct ics_state *ics = spapr->icp->ics;
    uint32_t nr;

    if ((nargs != 1) || (nret != 1)) {
        rtas_st(rets, 0, -3);
        return;
    }

    nr = rtas_ld(args, 0);

    if (!ics_valid_irq(ics, nr)) {
        rtas_st(rets, 0, -3);
        return;
    }

    /* This is a NOP for now, since the described PAPR semantics don't
     * seem to gel with what Linux does */
#if 0
    struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);

    ics_write_xive_msi(xics, nr, irq->server, irq->saved_priority);
#endif

    rtas_st(rets, 0, 0); /* Success */
}

struct icp_state *xics_system_init(int nr_irqs)
{
    CPUPPCState *env;
    int max_server_num;
    int i;
    struct icp_state *icp;
    struct ics_state *ics;

    max_server_num = -1;
    for (env = first_cpu; env != NULL; env = env->next_cpu) {
        if (env->cpu_index > max_server_num) {
            max_server_num = env->cpu_index;
        }
    }

    icp = g_malloc0(sizeof(*icp));
    icp->nr_servers = max_server_num + 1;
    icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));

    for (i = 0; i < icp->nr_servers; i++) {
        icp->ss[i].mfrr = 0xff;
    }

    for (env = first_cpu; env != NULL; env = env->next_cpu) {
        struct icp_server_state *ss = &icp->ss[env->cpu_index];

        switch (PPC_INPUT(env)) {
        case PPC_FLAGS_INPUT_POWER7:
            ss->output = env->irq_inputs[POWER7_INPUT_INT];
            break;

        case PPC_FLAGS_INPUT_970:
            ss->output = env->irq_inputs[PPC970_INPUT_INT];
            break;

        default:
            hw_error("XICS interrupt model does not support this CPU bus "
                     "model\n");
            exit(1);
        }
    }

    ics = g_malloc0(sizeof(*ics));
    ics->nr_irqs = nr_irqs;
    ics->offset = 16;
    ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));

    icp->ics = ics;
    ics->icp = icp;

    for (i = 0; i < nr_irqs; i++) {
        ics->irqs[i].priority = 0xff;
        ics->irqs[i].saved_priority = 0xff;
    }

    ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);

    spapr_register_hypercall(H_CPPR, h_cppr);
    spapr_register_hypercall(H_IPI, h_ipi);
    spapr_register_hypercall(H_XIRR, h_xirr);
    spapr_register_hypercall(H_EOI, h_eoi);

    spapr_rtas_register("ibm,set-xive", rtas_set_xive);
    spapr_rtas_register("ibm,get-xive", rtas_get_xive);
    spapr_rtas_register("ibm,int-off", rtas_int_off);
    spapr_rtas_register("ibm,int-on", rtas_int_on);

    return icp;
}
Commit	Line	Data
b5cec4c5 DG	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
	5	*
	6	* Copyright (c) 2010,2011 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27
	28	#include "hw.h"
	29	#include "hw/spapr.h"
	30	#include "hw/xics.h"
	31
b5cec4c5 DG	32	/*
	33	* ICP: Presentation layer
	34	*/
	35
	36	struct icp_server_state {
	37	uint32_t xirr;
	38	uint8_t pending_priority;
	39	uint8_t mfrr;
	40	qemu_irq output;
	41	};
	42
	43	#define XISR_MASK 0x00ffffff
	44	#define CPPR_MASK 0xff000000
	45
	46	#define XISR(ss) (((ss)->xirr) & XISR_MASK)
	47	#define CPPR(ss) (((ss)->xirr) >> 24)
	48
	49	struct ics_state;
	50
	51	struct icp_state {
	52	long nr_servers;
	53	struct icp_server_state *ss;
	54	struct ics_state *ics;
	55	};
	56
	57	static void ics_reject(struct ics_state *ics, int nr);
	58	static void ics_resend(struct ics_state *ics);
	59	static void ics_eoi(struct ics_state *ics, int nr);
	60
	61	static void icp_check_ipi(struct icp_state *icp, int server)
	62	{
	63	struct icp_server_state *ss = icp->ss + server;
	64
	65	if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
	66	return;
	67	}
	68
	69	if (XISR(ss)) {
	70	ics_reject(icp->ics, XISR(ss));
	71	}
	72
	73	ss->xirr = (ss->xirr & ~XISR_MASK) \| XICS_IPI;
	74	ss->pending_priority = ss->mfrr;
	75	qemu_irq_raise(ss->output);
	76	}
	77
	78	static void icp_resend(struct icp_state *icp, int server)
	79	{
	80	struct icp_server_state *ss = icp->ss + server;
	81
	82	if (ss->mfrr < CPPR(ss)) {
	83	icp_check_ipi(icp, server);
	84	}
	85	ics_resend(icp->ics);
	86	}
	87
	88	static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr)
	89	{
	90	struct icp_server_state *ss = icp->ss + server;
	91	uint8_t old_cppr;
	92	uint32_t old_xisr;
	93
	94	old_cppr = CPPR(ss);
	95	ss->xirr = (ss->xirr & ~CPPR_MASK) \| (cppr << 24);
96
97	if (cppr < old_cppr) {
98	if (XISR(ss) && (cppr <= ss->pending_priority)) {
99	old_xisr = XISR(ss);
100	ss->xirr &= ~XISR_MASK; /* Clear XISR */
101	qemu_irq_lower(ss->output);
102	ics_reject(icp->ics, old_xisr);
103	}
104	} else {
105	if (!XISR(ss)) {
106	icp_resend(icp, server);
107	}
108	}
109	}
110
111	static void icp_set_mfrr(struct icp_state *icp, int nr, uint8_t mfrr)
112	{
113	struct icp_server_state *ss = icp->ss + nr;
114
115	ss->mfrr = mfrr;
116	if (mfrr < CPPR(ss)) {
117	icp_check_ipi(icp, nr);
118	}
119	}
120
121	static uint32_t icp_accept(struct icp_server_state *ss)
122	{
123	uint32_t xirr;
124
125	qemu_irq_lower(ss->output);
126	xirr = ss->xirr;
127	ss->xirr = ss->pending_priority << 24;
128	return xirr;
129	}
130
131	static void icp_eoi(struct icp_state *icp, int server, uint32_t xirr)
132	{
133	struct icp_server_state *ss = icp->ss + server;
134
b5cec4c5 DG	135	/* Send EOI -> ICS */
b5cec4c5 DG	136	ss->xirr = (ss->xirr & ~CPPR_MASK) \| (xirr & CPPR_MASK);
d07fee7e	137	ics_eoi(icp->ics, xirr & XISR_MASK);
b5cec4c5 DG	138	if (!XISR(ss)) {
	139	icp_resend(icp, server);
	140	}
	141	}
	142
	143	static void icp_irq(struct icp_state *icp, int server, int nr, uint8_t priority)
	144	{
	145	struct icp_server_state *ss = icp->ss + server;
	146
	147	if ((priority >= CPPR(ss))
	148	\|\| (XISR(ss) && (ss->pending_priority <= priority))) {
	149	ics_reject(icp->ics, nr);
	150	} else {
	151	if (XISR(ss)) {
	152	ics_reject(icp->ics, XISR(ss));
	153	}
	154	ss->xirr = (ss->xirr & ~XISR_MASK) \| (nr & XISR_MASK);
	155	ss->pending_priority = priority;
	156	qemu_irq_raise(ss->output);
	157	}
	158	}
	159
	160	/*
	161	* ICS: Source layer
	162	*/
	163
	164	struct ics_irq_state {
	165	int server;
	166	uint8_t priority;
	167	uint8_t saved_priority;
d07fee7e DG	168	enum xics_irq_type type;
	169	int asserted:1;
	170	int sent:1;
b5cec4c5 DG	171	int rejected:1;
	172	int masked_pending:1;
	173	};
	174
	175	struct ics_state {
	176	int nr_irqs;
	177	int offset;
	178	qemu_irq *qirqs;
	179	struct ics_irq_state *irqs;
	180	struct icp_state *icp;
	181	};
	182
	183	static int ics_valid_irq(struct ics_state *ics, uint32_t nr)
	184	{
	185	return (nr >= ics->offset)
	186	&& (nr < (ics->offset + ics->nr_irqs));
	187	}
	188
d07fee7e DG	189	static void resend_msi(struct ics_state *ics, int srcno)
	190	{
	191	struct ics_irq_state *irq = ics->irqs + srcno;
	192
	193	/* FIXME: filter by server#? */
	194	if (irq->rejected) {
	195	irq->rejected = 0;
	196	if (irq->priority != 0xff) {
	197	icp_irq(ics->icp, irq->server, srcno + ics->offset,
	198	irq->priority);
	199	}
	200	}
	201	}
	202
	203	static void resend_lsi(struct ics_state *ics, int srcno)
	204	{
	205	struct ics_irq_state *irq = ics->irqs + srcno;
	206
	207	if ((irq->priority != 0xff) && irq->asserted && !irq->sent) {
	208	irq->sent = 1;
	209	icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
	210	}
	211	}
	212
	213	static void set_irq_msi(struct ics_state *ics, int srcno, int val)
b5cec4c5	214	{
cc67b9c8	215	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5 DG	216
	217	if (val) {
	218	if (irq->priority == 0xff) {
	219	irq->masked_pending = 1;
	220	/* masked pending */ ;
	221	} else {
cc67b9c8	222	icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
b5cec4c5 DG	223	}
	224	}
	225	}
	226
d07fee7e	227	static void set_irq_lsi(struct ics_state *ics, int srcno, int val)
b5cec4c5	228	{
d07fee7e	229	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5	230
d07fee7e DG	231	irq->asserted = val;
d07fee7e DG	232	resend_lsi(ics, srcno);
b5cec4c5 DG	233	}
b5cec4c5 DG	234
d07fee7e	235	static void ics_set_irq(void *opaque, int srcno, int val)
b5cec4c5	236	{
d07fee7e DG	237	struct ics_state ics = (struct ics_state )opaque;
d07fee7e DG	238	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5	239
d07fee7e DG	240	if (irq->type == XICS_LSI) {
	241	set_irq_lsi(ics, srcno, val);
	242	} else {
	243	set_irq_msi(ics, srcno, val);
	244	}
	245	}
b5cec4c5	246
d07fee7e DG	247	static void write_xive_msi(struct ics_state *ics, int srcno)
	248	{
	249	struct ics_irq_state *irq = ics->irqs + srcno;
	250
	251	if (!irq->masked_pending \|\| (irq->priority == 0xff)) {
	252	return;
b5cec4c5	253	}
d07fee7e DG	254
	255	irq->masked_pending = 0;
	256	icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
b5cec4c5 DG	257	}
b5cec4c5 DG	258
d07fee7e	259	static void write_xive_lsi(struct ics_state *ics, int srcno)
b5cec4c5	260	{
d07fee7e DG	261	resend_lsi(ics, srcno);
	262	}
	263
	264	static void ics_write_xive(struct ics_state *ics, int nr, int server,
	265	uint8_t priority)
	266	{
	267	int srcno = nr - ics->offset;
	268	struct ics_irq_state *irq = ics->irqs + srcno;
b5cec4c5 DG	269
	270	irq->server = server;
	271	irq->priority = priority;
	272
d07fee7e DG	273	if (irq->type == XICS_LSI) {
	274	write_xive_lsi(ics, srcno);
	275	} else {
	276	write_xive_msi(ics, srcno);
b5cec4c5	277	}
b5cec4c5 DG	278	}
	279
	280	static void ics_reject(struct ics_state *ics, int nr)
	281	{
d07fee7e DG	282	struct ics_irq_state *irq = ics->irqs + nr - ics->offset;
	283
	284	irq->rejected = 1; /* Irrelevant but harmless for LSI */
	285	irq->sent = 0; /* Irrelevant but harmless for MSI */
b5cec4c5 DG	286	}
	287
	288	static void ics_resend(struct ics_state *ics)
	289	{
d07fee7e DG	290	int i;
	291
	292	for (i = 0; i < ics->nr_irqs; i++) {
	293	struct ics_irq_state *irq = ics->irqs + i;
	294
	295	/* FIXME: filter by server#? */
	296	if (irq->type == XICS_LSI) {
	297	resend_lsi(ics, i);
	298	} else {
	299	resend_msi(ics, i);
	300	}
	301	}
b5cec4c5 DG	302	}
	303
	304	static void ics_eoi(struct ics_state *ics, int nr)
	305	{
d07fee7e DG	306	int srcno = nr - ics->offset;
	307	struct ics_irq_state *irq = ics->irqs + srcno;
	308
	309	if (irq->type == XICS_LSI) {
	310	irq->sent = 0;
	311	}
b5cec4c5 DG	312	}
	313
	314	/*
	315	* Exported functions
	316	*/
	317
d07fee7e DG	318	qemu_irq xics_assign_irq(struct icp_state *icp, int irq,
d07fee7e DG	319	enum xics_irq_type type)
b5cec4c5 DG	320	{
	321	if ((irq < icp->ics->offset)
	322	\|\| (irq >= (icp->ics->offset + icp->ics->nr_irqs))) {
	323	return NULL;
	324	}
	325
d07fee7e DG	326	assert((type == XICS_MSI) \|\| (type == XICS_LSI));
	327
	328	icp->ics->irqs[irq - icp->ics->offset].type = type;
b5cec4c5 DG	329	return icp->ics->qirqs[irq - icp->ics->offset];
	330	}
	331
e2684c0b	332	static target_ulong h_cppr(CPUPPCState env, sPAPREnvironment spapr,
b5cec4c5 DG	333	target_ulong opcode, target_ulong *args)
	334	{
	335	target_ulong cppr = args[0];
	336
	337	icp_set_cppr(spapr->icp, env->cpu_index, cppr);
	338	return H_SUCCESS;
	339	}
	340
e2684c0b	341	static target_ulong h_ipi(CPUPPCState env, sPAPREnvironment spapr,
b5cec4c5 DG	342	target_ulong opcode, target_ulong *args)
	343	{
	344	target_ulong server = args[0];
	345	target_ulong mfrr = args[1];
	346
	347	if (server >= spapr->icp->nr_servers) {
	348	return H_PARAMETER;
	349	}
	350
	351	icp_set_mfrr(spapr->icp, server, mfrr);
	352	return H_SUCCESS;
	353
	354	}
	355
e2684c0b	356	static target_ulong h_xirr(CPUPPCState env, sPAPREnvironment spapr,
b5cec4c5 DG	357	target_ulong opcode, target_ulong *args)
	358	{
	359	uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index);
	360
	361	args[0] = xirr;
	362	return H_SUCCESS;
	363	}
	364
e2684c0b	365	static target_ulong h_eoi(CPUPPCState env, sPAPREnvironment spapr,
b5cec4c5 DG	366	target_ulong opcode, target_ulong *args)
	367	{
	368	target_ulong xirr = args[0];
	369
	370	icp_eoi(spapr->icp, env->cpu_index, xirr);
	371	return H_SUCCESS;
	372	}
	373
	374	static void rtas_set_xive(sPAPREnvironment *spapr, uint32_t token,
	375	uint32_t nargs, target_ulong args,
	376	uint32_t nret, target_ulong rets)
	377	{
	378	struct ics_state *ics = spapr->icp->ics;
	379	uint32_t nr, server, priority;
	380
	381	if ((nargs != 3) \|\| (nret != 1)) {
	382	rtas_st(rets, 0, -3);
	383	return;
	384	}
	385
	386	nr = rtas_ld(args, 0);
	387	server = rtas_ld(args, 1);
	388	priority = rtas_ld(args, 2);
	389
	390	if (!ics_valid_irq(ics, nr) \|\| (server >= ics->icp->nr_servers)
	391	\|\| (priority > 0xff)) {
	392	rtas_st(rets, 0, -3);
	393	return;
	394	}
	395
d07fee7e	396	ics_write_xive(ics, nr, server, priority);
b5cec4c5 DG	397
	398	rtas_st(rets, 0, 0); /* Success */
	399	}
	400
	401	static void rtas_get_xive(sPAPREnvironment *spapr, uint32_t token,
	402	uint32_t nargs, target_ulong args,
	403	uint32_t nret, target_ulong rets)
	404	{
	405	struct ics_state *ics = spapr->icp->ics;
	406	uint32_t nr;
	407
	408	if ((nargs != 1) \|\| (nret != 3)) {
	409	rtas_st(rets, 0, -3);
	410	return;
	411	}
	412
	413	nr = rtas_ld(args, 0);
	414
	415	if (!ics_valid_irq(ics, nr)) {
	416	rtas_st(rets, 0, -3);
	417	return;
	418	}
	419
	420	rtas_st(rets, 0, 0); /* Success */
	421	rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
	422	rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
	423	}
	424
	425	static void rtas_int_off(sPAPREnvironment *spapr, uint32_t token,
	426	uint32_t nargs, target_ulong args,
	427	uint32_t nret, target_ulong rets)
	428	{
	429	struct ics_state *ics = spapr->icp->ics;
	430	uint32_t nr;
	431
	432	if ((nargs != 1) \|\| (nret != 1)) {
	433	rtas_st(rets, 0, -3);
	434	return;
	435	}
	436
	437	nr = rtas_ld(args, 0);
	438
	439	if (!ics_valid_irq(ics, nr)) {
	440	rtas_st(rets, 0, -3);
	441	return;
	442	}
	443
	444	/* This is a NOP for now, since the described PAPR semantics don't
	445	* seem to gel with what Linux does */
	446	#if 0
	447	struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);
	448
	449	irq->saved_priority = irq->priority;
cc67b9c8	450	ics_write_xive_msi(xics, nr, irq->server, 0xff);
b5cec4c5 DG	451	#endif
	452
	453	rtas_st(rets, 0, 0); /* Success */
	454	}
	455
	456	static void rtas_int_on(sPAPREnvironment *spapr, uint32_t token,
	457	uint32_t nargs, target_ulong args,
	458	uint32_t nret, target_ulong rets)
	459	{
	460	struct ics_state *ics = spapr->icp->ics;
	461	uint32_t nr;
	462
	463	if ((nargs != 1) \|\| (nret != 1)) {
	464	rtas_st(rets, 0, -3);
	465	return;
	466	}
	467
	468	nr = rtas_ld(args, 0);
	469
	470	if (!ics_valid_irq(ics, nr)) {
	471	rtas_st(rets, 0, -3);
	472	return;
	473	}
	474
	475	/* This is a NOP for now, since the described PAPR semantics don't
	476	* seem to gel with what Linux does */
	477	#if 0
	478	struct ics_irq_state *irq = xics->irqs + (nr - xics->offset);
	479
cc67b9c8	480	ics_write_xive_msi(xics, nr, irq->server, irq->saved_priority);
b5cec4c5 DG	481	#endif
	482
	483	rtas_st(rets, 0, 0); /* Success */
	484	}
	485
c7a5c0c9	486	struct icp_state *xics_system_init(int nr_irqs)
b5cec4c5	487	{
e2684c0b	488	CPUPPCState *env;
c7a5c0c9	489	int max_server_num;
b5cec4c5 DG	490	int i;
	491	struct icp_state *icp;
	492	struct ics_state *ics;
	493
c7a5c0c9 DG	494	max_server_num = -1;
	495	for (env = first_cpu; env != NULL; env = env->next_cpu) {
	496	if (env->cpu_index > max_server_num) {
	497	max_server_num = env->cpu_index;
	498	}
	499	}
	500
7267c094	501	icp = g_malloc0(sizeof(*icp));
c7a5c0c9	502	icp->nr_servers = max_server_num + 1;
7267c094	503	icp->ss = g_malloc0(icp->nr_servers*sizeof(struct icp_server_state));
c7a5c0c9 DG	504
	505	for (i = 0; i < icp->nr_servers; i++) {
	506	icp->ss[i].mfrr = 0xff;
	507	}
b5cec4c5	508
c7a5c0c9 DG	509	for (env = first_cpu; env != NULL; env = env->next_cpu) {
c7a5c0c9 DG	510	struct icp_server_state *ss = &icp->ss[env->cpu_index];
b5cec4c5	511
c7a5c0c9	512	switch (PPC_INPUT(env)) {
b5cec4c5	513	case PPC_FLAGS_INPUT_POWER7:
c7a5c0c9	514	ss->output = env->irq_inputs[POWER7_INPUT_INT];
b5cec4c5 DG	515	break;
	516
	517	case PPC_FLAGS_INPUT_970:
c7a5c0c9	518	ss->output = env->irq_inputs[PPC970_INPUT_INT];
b5cec4c5 DG	519	break;
	520
	521	default:
	522	hw_error("XICS interrupt model does not support this CPU bus "
	523	"model\n");
	524	exit(1);
	525	}
b5cec4c5 DG	526	}
b5cec4c5 DG	527
7267c094	528	ics = g_malloc0(sizeof(*ics));
b5cec4c5 DG	529	ics->nr_irqs = nr_irqs;
b5cec4c5 DG	530	ics->offset = 16;
7267c094	531	ics->irqs = g_malloc0(nr_irqs * sizeof(struct ics_irq_state));
b5cec4c5 DG	532
	533	icp->ics = ics;
	534	ics->icp = icp;
	535
	536	for (i = 0; i < nr_irqs; i++) {
	537	ics->irqs[i].priority = 0xff;
	538	ics->irqs[i].saved_priority = 0xff;
	539	}
	540
d07fee7e	541	ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, nr_irqs);
b5cec4c5 DG	542
	543	spapr_register_hypercall(H_CPPR, h_cppr);
	544	spapr_register_hypercall(H_IPI, h_ipi);
	545	spapr_register_hypercall(H_XIRR, h_xirr);
	546	spapr_register_hypercall(H_EOI, h_eoi);
	547
	548	spapr_rtas_register("ibm,set-xive", rtas_set_xive);
	549	spapr_rtas_register("ibm,get-xive", rtas_get_xive);
	550	spapr_rtas_register("ibm,int-off", rtas_int_off);
	551	spapr_rtas_register("ibm,int-on", rtas_int_on);
	552
	553	return icp;
	554	}