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b43848a1 EI |
1 | /* |
2 | * QEMU model of the Xilinx Ethernet Lite MAC. | |
3 | * | |
4 | * Copyright (c) 2009 Edgar E. Iglesias. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "sysbus.h" | |
26 | #include "hw.h" | |
27 | #include "net.h" | |
28 | ||
29 | #define D(x) | |
30 | #define R_TX_BUF0 0 | |
31 | #define R_TX_LEN0 (0x07f4 / 4) | |
32 | #define R_TX_GIE0 (0x07f8 / 4) | |
33 | #define R_TX_CTRL0 (0x07fc / 4) | |
34 | #define R_TX_BUF1 (0x0800 / 4) | |
35 | #define R_TX_LEN1 (0x0ff4 / 4) | |
36 | #define R_TX_CTRL1 (0x0ffc / 4) | |
37 | ||
38 | #define R_RX_BUF0 (0x1000 / 4) | |
39 | #define R_RX_CTRL0 (0x17fc / 4) | |
40 | #define R_RX_BUF1 (0x1800 / 4) | |
41 | #define R_RX_CTRL1 (0x1ffc / 4) | |
42 | #define R_MAX (0x2000 / 4) | |
43 | ||
44 | #define GIE_GIE 0x80000000 | |
45 | ||
46 | #define CTRL_I 0x8 | |
47 | #define CTRL_P 0x2 | |
48 | #define CTRL_S 0x1 | |
49 | ||
50 | struct xlx_ethlite | |
51 | { | |
52 | SysBusDevice busdev; | |
53 | qemu_irq irq; | |
d7539ab4 | 54 | NICState *nic; |
17d1ae3c | 55 | NICConf conf; |
b43848a1 | 56 | |
ee6847d1 GH |
57 | uint32_t c_tx_pingpong; |
58 | uint32_t c_rx_pingpong; | |
b43848a1 EI |
59 | unsigned int txbuf; |
60 | unsigned int rxbuf; | |
61 | ||
b43848a1 EI |
62 | uint32_t regs[R_MAX]; |
63 | }; | |
64 | ||
65 | static inline void eth_pulse_irq(struct xlx_ethlite *s) | |
66 | { | |
67 | /* Only the first gie reg is active. */ | |
68 | if (s->regs[R_TX_GIE0] & GIE_GIE) { | |
69 | qemu_irq_pulse(s->irq); | |
70 | } | |
71 | } | |
72 | ||
c227f099 | 73 | static uint32_t eth_readl (void *opaque, target_phys_addr_t addr) |
b43848a1 EI |
74 | { |
75 | struct xlx_ethlite *s = opaque; | |
76 | uint32_t r = 0; | |
77 | ||
78 | addr >>= 2; | |
79 | ||
80 | switch (addr) | |
81 | { | |
82 | case R_TX_GIE0: | |
83 | case R_TX_LEN0: | |
84 | case R_TX_LEN1: | |
85 | case R_TX_CTRL1: | |
86 | case R_TX_CTRL0: | |
87 | case R_RX_CTRL1: | |
88 | case R_RX_CTRL0: | |
89 | r = s->regs[addr]; | |
90 | D(qemu_log("%s %x=%x\n", __func__, addr * 4, r)); | |
91 | break; | |
92 | ||
b43848a1 | 93 | default: |
d48751ed | 94 | r = tswap32(s->regs[addr]); |
b43848a1 EI |
95 | break; |
96 | } | |
97 | return r; | |
98 | } | |
99 | ||
100 | static void | |
c227f099 | 101 | eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
b43848a1 EI |
102 | { |
103 | struct xlx_ethlite *s = opaque; | |
104 | unsigned int base = 0; | |
105 | ||
106 | addr >>= 2; | |
107 | switch (addr) | |
108 | { | |
109 | case R_TX_CTRL0: | |
110 | case R_TX_CTRL1: | |
111 | if (addr == R_TX_CTRL1) | |
112 | base = 0x800 / 4; | |
113 | ||
114 | D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value)); | |
115 | if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { | |
d7539ab4 | 116 | qemu_send_packet(&s->nic->nc, |
b43848a1 EI |
117 | (void *) &s->regs[base], |
118 | s->regs[base + R_TX_LEN0]); | |
119 | D(qemu_log("eth_tx %d\n", s->regs[base + R_TX_LEN0])); | |
120 | if (s->regs[base + R_TX_CTRL0] & CTRL_I) | |
121 | eth_pulse_irq(s); | |
122 | } else if ((value & (CTRL_P | CTRL_S)) == (CTRL_P | CTRL_S)) { | |
17d1ae3c | 123 | memcpy(&s->conf.macaddr.a[0], &s->regs[base], 6); |
b43848a1 EI |
124 | if (s->regs[base + R_TX_CTRL0] & CTRL_I) |
125 | eth_pulse_irq(s); | |
126 | } | |
127 | ||
128 | /* We are fast and get ready pretty much immediately so | |
129 | we actually never flip the S nor P bits to one. */ | |
130 | s->regs[addr] = value & ~(CTRL_P | CTRL_S); | |
131 | break; | |
132 | ||
133 | /* Keep these native. */ | |
134 | case R_TX_LEN0: | |
135 | case R_TX_LEN1: | |
136 | case R_TX_GIE0: | |
137 | case R_RX_CTRL0: | |
138 | case R_RX_CTRL1: | |
139 | D(qemu_log("%s addr=%x val=%x\n", __func__, addr * 4, value)); | |
140 | s->regs[addr] = value; | |
141 | break; | |
142 | ||
b43848a1 | 143 | default: |
d48751ed | 144 | s->regs[addr] = tswap32(value); |
b43848a1 EI |
145 | break; |
146 | } | |
147 | } | |
148 | ||
d60efc6b | 149 | static CPUReadMemoryFunc * const eth_read[] = { |
b43848a1 EI |
150 | NULL, NULL, ð_readl, |
151 | }; | |
152 | ||
d60efc6b | 153 | static CPUWriteMemoryFunc * const eth_write[] = { |
b43848a1 EI |
154 | NULL, NULL, ð_writel, |
155 | }; | |
156 | ||
d7539ab4 | 157 | static int eth_can_rx(VLANClientState *nc) |
b43848a1 | 158 | { |
d7539ab4 | 159 | struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque; |
b43848a1 EI |
160 | int r; |
161 | r = !(s->regs[R_RX_CTRL0] & CTRL_S); | |
b43848a1 EI |
162 | return r; |
163 | } | |
164 | ||
d7539ab4 | 165 | static ssize_t eth_rx(VLANClientState *nc, const uint8_t *buf, size_t size) |
b43848a1 | 166 | { |
d7539ab4 | 167 | struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque; |
b43848a1 | 168 | unsigned int rxbase = s->rxbuf * (0x800 / 4); |
b43848a1 EI |
169 | |
170 | /* DA filter. */ | |
17d1ae3c | 171 | if (!(buf[0] & 0x80) && memcmp(&s->conf.macaddr.a[0], buf, 6)) |
df12c1f5 | 172 | return size; |
b43848a1 EI |
173 | |
174 | if (s->regs[rxbase + R_RX_CTRL0] & CTRL_S) { | |
175 | D(qemu_log("ethlite lost packet %x\n", s->regs[R_RX_CTRL0])); | |
df12c1f5 | 176 | return -1; |
b43848a1 EI |
177 | } |
178 | ||
179 | D(qemu_log("%s %d rxbase=%x\n", __func__, size, rxbase)); | |
180 | memcpy(&s->regs[rxbase + R_RX_BUF0], buf, size); | |
181 | ||
b43848a1 EI |
182 | s->regs[rxbase + R_RX_CTRL0] |= CTRL_S; |
183 | if (s->regs[rxbase + R_RX_CTRL0] & CTRL_I) | |
184 | eth_pulse_irq(s); | |
185 | ||
186 | /* If c_rx_pingpong was set flip buffers. */ | |
187 | s->rxbuf ^= s->c_rx_pingpong; | |
df12c1f5 | 188 | return size; |
b43848a1 EI |
189 | } |
190 | ||
d7539ab4 | 191 | static void eth_cleanup(VLANClientState *nc) |
b43848a1 | 192 | { |
d7539ab4 | 193 | struct xlx_ethlite *s = DO_UPCAST(NICState, nc, nc)->opaque; |
17d1ae3c | 194 | |
d7539ab4 | 195 | s->nic = NULL; |
b43848a1 EI |
196 | } |
197 | ||
d7539ab4 MM |
198 | static NetClientInfo net_xilinx_ethlite_info = { |
199 | .type = NET_CLIENT_TYPE_NIC, | |
200 | .size = sizeof(NICState), | |
201 | .can_receive = eth_can_rx, | |
202 | .receive = eth_rx, | |
203 | .cleanup = eth_cleanup, | |
204 | }; | |
205 | ||
81a322d4 | 206 | static int xilinx_ethlite_init(SysBusDevice *dev) |
b43848a1 EI |
207 | { |
208 | struct xlx_ethlite *s = FROM_SYSBUS(typeof (*s), dev); | |
209 | int regs; | |
210 | ||
211 | sysbus_init_irq(dev, &s->irq); | |
b43848a1 EI |
212 | s->rxbuf = 0; |
213 | ||
2507c12a | 214 | regs = cpu_register_io_memory(eth_read, eth_write, s, DEVICE_NATIVE_ENDIAN); |
b43848a1 EI |
215 | sysbus_init_mmio(dev, R_MAX * 4, regs); |
216 | ||
17d1ae3c | 217 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
d7539ab4 MM |
218 | s->nic = qemu_new_nic(&net_xilinx_ethlite_info, &s->conf, |
219 | dev->qdev.info->name, dev->qdev.id, s); | |
220 | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); | |
81a322d4 | 221 | return 0; |
b43848a1 EI |
222 | } |
223 | ||
ee6847d1 GH |
224 | static SysBusDeviceInfo xilinx_ethlite_info = { |
225 | .init = xilinx_ethlite_init, | |
226 | .qdev.name = "xilinx,ethlite", | |
227 | .qdev.size = sizeof(struct xlx_ethlite), | |
228 | .qdev.props = (Property[]) { | |
05f02579 GH |
229 | DEFINE_PROP_UINT32("txpingpong", struct xlx_ethlite, c_tx_pingpong, 1), |
230 | DEFINE_PROP_UINT32("rxpingpong", struct xlx_ethlite, c_rx_pingpong, 1), | |
17d1ae3c | 231 | DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf), |
05f02579 | 232 | DEFINE_PROP_END_OF_LIST(), |
ee6847d1 GH |
233 | } |
234 | }; | |
235 | ||
b43848a1 EI |
236 | static void xilinx_ethlite_register(void) |
237 | { | |
ee6847d1 | 238 | sysbus_register_withprop(&xilinx_ethlite_info); |
b43848a1 EI |
239 | } |
240 | ||
241 | device_init(xilinx_ethlite_register) |