[qemu.git] / hw / xilinx_timer.c

/*
 * QEMU model of the Xilinx timer block.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "sysemu.h"
#include "qemu-timer.h"

#define D(x)

#define R_TCSR     0
#define R_TLR      1
#define R_TCR      2
#define R_MAX      4

#define TCSR_MDT        (1<<0)
#define TCSR_UDT        (1<<1)
#define TCSR_GENT       (1<<2)
#define TCSR_CAPT       (1<<3)
#define TCSR_ARHT       (1<<4)
#define TCSR_LOAD       (1<<5)
#define TCSR_ENIT       (1<<6)
#define TCSR_ENT        (1<<7)
#define TCSR_TINT       (1<<8)
#define TCSR_PWMA       (1<<9)
#define TCSR_ENALL      (1<<10)

struct xlx_timer
{
    QEMUBH *bh;
    ptimer_state *ptimer;
    void *parent;
    int nr; /* for debug.  */

    unsigned long timer_div;

    uint32_t regs[R_MAX];
};

struct timerblock
{
    SysBusDevice busdev;
    qemu_irq irq;
    uint32_t nr_timers;
    uint32_t freq_hz;
    struct xlx_timer *timers;
};

static inline unsigned int timer_from_addr(target_phys_addr_t addr)
{
    /* Timers get a 4x32bit control reg area each.  */
    return addr >> 2;
}

static void timer_update_irq(struct timerblock *t)
{
    unsigned int i, irq = 0;
    uint32_t csr;

    for (i = 0; i < t->nr_timers; i++) {
        csr = t->timers[i].regs[R_TCSR];
        irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
    }

    /* All timers within the same slave share a single IRQ line.  */
    qemu_set_irq(t->irq, !!irq);
}

static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
{
    struct timerblock *t = opaque;
    struct xlx_timer *xt;
    uint32_t r = 0;
    unsigned int timer;

    addr >>= 2;
    timer = timer_from_addr(addr);
    xt = &t->timers[timer];
    /* Further decoding to address a specific timers reg.  */
    addr &= 0x3;
    switch (addr)
    {
        case R_TCR:
                r = ptimer_get_count(xt->ptimer);
                if (!(xt->regs[R_TCSR] & TCSR_UDT))
                    r = ~r;
                D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
                         timer, r, xt->regs[R_TCSR] & TCSR_UDT));
            break;
        default:
            if (addr < ARRAY_SIZE(xt->regs))
                r = xt->regs[addr];
            break;

    }
    D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
    return r;
}

static void timer_enable(struct xlx_timer *xt)
{
    uint64_t count;

    D(printf("%s timer=%d down=%d\n", __func__,
              xt->nr, xt->regs[R_TCSR] & TCSR_UDT));

    ptimer_stop(xt->ptimer);

    if (xt->regs[R_TCSR] & TCSR_UDT)
        count = xt->regs[R_TLR];
    else
        count = ~0 - xt->regs[R_TLR];
    ptimer_set_count(xt->ptimer, count);
    ptimer_run(xt->ptimer, 1);
}

static void
timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct timerblock *t = opaque;
    struct xlx_timer *xt;
    unsigned int timer;

    addr >>= 2;
    timer = timer_from_addr(addr);
    xt = &t->timers[timer];
    D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
             __func__, addr * 4, value, timer, addr & 3));
    /* Further decoding to address a specific timers reg.  */
    addr &= 3;
    switch (addr) 
    {
        case R_TCSR:
            if (value & TCSR_TINT)
                value &= ~TCSR_TINT;

            xt->regs[addr] = value;
            if (value & TCSR_ENT)
                timer_enable(xt);
            break;
 
        default:
            if (addr < ARRAY_SIZE(xt->regs))
                xt->regs[addr] = value;
            break;
    }
    timer_update_irq(t);
}

static CPUReadMemoryFunc * const timer_read[] = {
    NULL, NULL,
    &timer_readl,
};

static CPUWriteMemoryFunc * const timer_write[] = {
    NULL, NULL,
    &timer_writel,
};

static void timer_hit(void *opaque)
{
    struct xlx_timer *xt = opaque;
    struct timerblock *t = xt->parent;
    D(printf("%s %d\n", __func__, timer));
    xt->regs[R_TCSR] |= TCSR_TINT;

    if (xt->regs[R_TCSR] & TCSR_ARHT)
        timer_enable(xt);
    timer_update_irq(t);
}

static int xilinx_timer_init(SysBusDevice *dev)
{
    struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
    unsigned int i;
    int timer_regs;

    /* All timers share a single irq line.  */
    sysbus_init_irq(dev, &t->irq);

    /* Init all the ptimers.  */
    t->timers = qemu_mallocz(sizeof t->timers[0] * t->nr_timers);
    for (i = 0; i < t->nr_timers; i++) {
        struct xlx_timer *xt = &t->timers[i];

        xt->parent = t;
        xt->nr = i;
        xt->bh = qemu_bh_new(timer_hit, xt);
        xt->ptimer = ptimer_init(xt->bh);
        ptimer_set_freq(xt->ptimer, t->freq_hz);
    }

    timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
    sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
    return 0;
}

static SysBusDeviceInfo xilinx_timer_info = {
    .init = xilinx_timer_init,
    .qdev.name  = "xilinx,timer",
    .qdev.size  = sizeof(struct timerblock),
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz,   0),
        DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void xilinx_timer_register(void)
{
    sysbus_register_withprop(&xilinx_timer_info);
}

device_init(xilinx_timer_register)
Commit	Line	Data
388f60b1 EI	1	/*
	2	* QEMU model of the Xilinx timer block.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "sysbus.h"
	26	#include "sysemu.h"
	27	#include "qemu-timer.h"
	28
	29	#define D(x)
	30
	31	#define R_TCSR 0
	32	#define R_TLR 1
	33	#define R_TCR 2
	34	#define R_MAX 4
	35
	36	#define TCSR_MDT (1<<0)
	37	#define TCSR_UDT (1<<1)
	38	#define TCSR_GENT (1<<2)
	39	#define TCSR_CAPT (1<<3)
	40	#define TCSR_ARHT (1<<4)
	41	#define TCSR_LOAD (1<<5)
	42	#define TCSR_ENIT (1<<6)
	43	#define TCSR_ENT (1<<7)
	44	#define TCSR_TINT (1<<8)
	45	#define TCSR_PWMA (1<<9)
	46	#define TCSR_ENALL (1<<10)
	47
	48	struct xlx_timer
	49	{
	50	QEMUBH *bh;
	51	ptimer_state *ptimer;
	52	void *parent;
	53	int nr; /* for debug. */
	54
	55	unsigned long timer_div;
	56
	57	uint32_t regs[R_MAX];
	58	};
	59
	60	struct timerblock
	61	{
	62	SysBusDevice busdev;
	63	qemu_irq irq;
ee6847d1 GH	64	uint32_t nr_timers;
ee6847d1 GH	65	uint32_t freq_hz;
388f60b1 EI	66	struct xlx_timer *timers;
	67	};
	68
c227f099	69	static inline unsigned int timer_from_addr(target_phys_addr_t addr)
388f60b1 EI	70	{
	71	/* Timers get a 4x32bit control reg area each. */
	72	return addr >> 2;
	73	}
	74
	75	static void timer_update_irq(struct timerblock *t)
	76	{
	77	unsigned int i, irq = 0;
	78	uint32_t csr;
	79
	80	for (i = 0; i < t->nr_timers; i++) {
	81	csr = t->timers[i].regs[R_TCSR];
	82	irq \|= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
	83	}
	84
	85	/* All timers within the same slave share a single IRQ line. */
	86	qemu_set_irq(t->irq, !!irq);
	87	}
	88
c227f099	89	static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
388f60b1 EI	90	{
	91	struct timerblock *t = opaque;
	92	struct xlx_timer *xt;
	93	uint32_t r = 0;
	94	unsigned int timer;
	95
	96	addr >>= 2;
	97	timer = timer_from_addr(addr);
	98	xt = &t->timers[timer];
	99	/* Further decoding to address a specific timers reg. */
	100	addr &= 0x3;
	101	switch (addr)
	102	{
	103	case R_TCR:
	104	r = ptimer_get_count(xt->ptimer);
	105	if (!(xt->regs[R_TCSR] & TCSR_UDT))
	106	r = ~r;
	107	D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
	108	timer, r, xt->regs[R_TCSR] & TCSR_UDT));
	109	break;
	110	default:
	111	if (addr < ARRAY_SIZE(xt->regs))
	112	r = xt->regs[addr];
	113	break;
	114
	115	}
	116	D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
	117	return r;
	118	}
	119
	120	static void timer_enable(struct xlx_timer *xt)
	121	{
	122	uint64_t count;
	123
	124	D(printf("%s timer=%d down=%d\n", __func__,
	125	xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
	126
	127	ptimer_stop(xt->ptimer);
	128
	129	if (xt->regs[R_TCSR] & TCSR_UDT)
	130	count = xt->regs[R_TLR];
	131	else
	132	count = ~0 - xt->regs[R_TLR];
	133	ptimer_set_count(xt->ptimer, count);
	134	ptimer_run(xt->ptimer, 1);
	135	}
	136
	137	static void
c227f099	138	timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
388f60b1 EI	139	{
	140	struct timerblock *t = opaque;
	141	struct xlx_timer *xt;
	142	unsigned int timer;
	143
	144	addr >>= 2;
	145	timer = timer_from_addr(addr);
	146	xt = &t->timers[timer];
	147	D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
	148	__func__, addr * 4, value, timer, addr & 3));
	149	/* Further decoding to address a specific timers reg. */
	150	addr &= 3;
	151	switch (addr)
	152	{
	153	case R_TCSR:
	154	if (value & TCSR_TINT)
	155	value &= ~TCSR_TINT;
	156
	157	xt->regs[addr] = value;
	158	if (value & TCSR_ENT)
	159	timer_enable(xt);
	160	break;
	161
	162	default:
	163	if (addr < ARRAY_SIZE(xt->regs))
	164	xt->regs[addr] = value;
	165	break;
	166	}
	167	timer_update_irq(t);
	168	}
	169
d60efc6b	170	static CPUReadMemoryFunc * const timer_read[] = {
388f60b1 EI	171	NULL, NULL,
	172	&timer_readl,
	173	};
	174
d60efc6b	175	static CPUWriteMemoryFunc * const timer_write[] = {
388f60b1 EI	176	NULL, NULL,
	177	&timer_writel,
	178	};
	179
	180	static void timer_hit(void *opaque)
	181	{
	182	struct xlx_timer *xt = opaque;
	183	struct timerblock *t = xt->parent;
	184	D(printf("%s %d\n", __func__, timer));
	185	xt->regs[R_TCSR] \|= TCSR_TINT;
	186
	187	if (xt->regs[R_TCSR] & TCSR_ARHT)
	188	timer_enable(xt);
	189	timer_update_irq(t);
	190	}
	191
81a322d4	192	static int xilinx_timer_init(SysBusDevice *dev)
388f60b1 EI	193	{
	194	struct timerblock t = FROM_SYSBUS(typeof (t), dev);
	195	unsigned int i;
ee6847d1	196	int timer_regs;
388f60b1 EI	197
	198	/* All timers share a single irq line. */
	199	sysbus_init_irq(dev, &t->irq);
	200
	201	/* Init all the ptimers. */
388f60b1 EI	202	t->timers = qemu_mallocz(sizeof t->timers[0] * t->nr_timers);
	203	for (i = 0; i < t->nr_timers; i++) {
	204	struct xlx_timer *xt = &t->timers[i];
	205
	206	xt->parent = t;
	207	xt->nr = i;
	208	xt->bh = qemu_bh_new(timer_hit, xt);
	209	xt->ptimer = ptimer_init(xt->bh);
ee6847d1	210	ptimer_set_freq(xt->ptimer, t->freq_hz);
388f60b1 EI	211	}
388f60b1 EI	212
1eed09cb	213	timer_regs = cpu_register_io_memory(timer_read, timer_write, t);
388f60b1	214	sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
81a322d4	215	return 0;
388f60b1 EI	216	}
388f60b1 EI	217
ee6847d1 GH	218	static SysBusDeviceInfo xilinx_timer_info = {
	219	.init = xilinx_timer_init,
	220	.qdev.name = "xilinx,timer",
	221	.qdev.size = sizeof(struct timerblock),
	222	.qdev.props = (Property[]) {
ea2b7271 GH	223	DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz, 0),
	224	DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
	225	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	226	}
	227	};
	228
388f60b1 EI	229	static void xilinx_timer_register(void)
388f60b1 EI	230	{
ee6847d1	231	sysbus_register_withprop(&xilinx_timer_info);
388f60b1 EI	232	}
	233
	234	device_init(xilinx_timer_register)