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1/*
2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
09aae23d 28#include "qemu/osdep.h"
da34e65c 29#include "qapi/error.h"
71e8a915 30#include "sysemu/reset.h"
9c17d615 31#include "sysemu/sysemu.h"
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32#include "hw/boards.h"
33#include "hw/loader.h"
47d05a86 34#include "elf.h"
022c62cb 35#include "exec/memory.h"
8488ab02 36#include "qemu/error-report.h"
e53fa62c 37#include "xtensa_memory.h"
d9e8553b 38#include "xtensa_sim.h"
b68755c1 39
00b941e5 40static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
47d05a86 41{
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42 XtensaCPU *cpu = opaque;
43
44 return cpu_get_phys_page_debug(CPU(cpu), addr);
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45}
46
11e7bfd7 47static void sim_reset(void *opaque)
47d05a86 48{
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49 XtensaCPU *cpu = opaque;
50
51 cpu_reset(CPU(cpu));
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52}
53
d9e8553b 54XtensaCPU *xtensa_sim_common_init(MachineState *machine)
47d05a86 55{
06d26274 56 XtensaCPU *cpu = NULL;
5bfcb36e 57 CPUXtensaState *env = NULL;
3ef96221 58 ram_addr_t ram_size = machine->ram_size;
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59 int n;
60
33decbd2 61 for (n = 0; n < machine->smp.cpus; n++) {
d58eeae3 62 cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
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63 env = &cpu->env;
64
47d05a86 65 env->sregs[PRID] = n;
11e7bfd7 66 qemu_register_reset(sim_reset, cpu);
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67 /* Need MMU initialized prior to ELF loading,
68 * so that ELF gets loaded into virtual addresses
69 */
11e7bfd7 70 sim_reset(cpu);
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71 }
72
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73 if (env) {
74 XtensaMemory sysram = env->config->sysram;
47d05a86 75
b68755c1 76 sysram.location[0].size = ram_size;
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77 xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
78 get_system_memory());
79 xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
80 get_system_memory());
81 xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
82 get_system_memory());
83 xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
84 get_system_memory());
85 xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
86 get_system_memory());
87 xtensa_create_memory_regions(&sysram, "xtensa.sysram",
88 get_system_memory());
b68755c1 89 }
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90 if (serial_hd(0)) {
91 xtensa_sim_open_console(serial_hd(0));
8128b3e0 92 }
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93 return cpu;
94}
95
96void xtensa_sim_load_kernel(XtensaCPU *cpu, MachineState *machine)
97{
98 const char *kernel_filename = machine->kernel_filename;
47d05a86 99#ifdef TARGET_WORDS_BIGENDIAN
d9e8553b 100 int big_endian = true;
47d05a86 101#else
d9e8553b 102 int big_endian = false;
47d05a86 103#endif
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104
105 if (kernel_filename) {
106 uint64_t elf_entry;
d9e8553b 107 int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu,
617160c9 108 &elf_entry, NULL, NULL, NULL, big_endian,
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109 EM_XTENSA, 0, 0);
110
47d05a86 111 if (success > 0) {
d9e8553b 112 cpu->env.pc = elf_entry;
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113 }
114 }
115}
116
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117static void xtensa_sim_init(MachineState *machine)
118{
119 XtensaCPU *cpu = xtensa_sim_common_init(machine);
120
121 xtensa_sim_load_kernel(cpu, machine);
122}
123
e264d29d 124static void xtensa_sim_machine_init(MachineClass *mc)
47d05a86 125{
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126 mc->desc = "sim machine (" XTENSA_DEFAULT_CPU_MODEL ")";
127 mc->is_default = true;
128 mc->init = xtensa_sim_init;
129 mc->max_cpus = 4;
8128b3e0 130 mc->no_serial = 1;
d58eeae3 131 mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
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132}
133
e264d29d 134DEFINE_MACHINE("sim", xtensa_sim_machine_init)