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0200db65 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
9c17d615 | 28 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
29 | #include "hw/boards.h" |
30 | #include "hw/loader.h" | |
0200db65 | 31 | #include "elf.h" |
022c62cb PB |
32 | #include "exec/memory.h" |
33 | #include "exec/address-spaces.h" | |
0d09e41a | 34 | #include "hw/char/serial.h" |
1422e32d | 35 | #include "net/net.h" |
83c9f4ca | 36 | #include "hw/sysbus.h" |
0d09e41a | 37 | #include "hw/block/flash.h" |
fa1d36df | 38 | #include "sysemu/block-backend.h" |
dccfcd0e | 39 | #include "sysemu/char.h" |
996dfe98 | 40 | #include "sysemu/device_tree.h" |
8488ab02 | 41 | #include "qemu/error-report.h" |
b707ab75 | 42 | #include "bootparam.h" |
82b25dc8 MF |
43 | |
44 | typedef struct LxBoardDesc { | |
e0db904d | 45 | hwaddr flash_base; |
82b25dc8 | 46 | size_t flash_size; |
37ed7c4b | 47 | size_t flash_boot_base; |
82b25dc8 MF |
48 | size_t flash_sector_size; |
49 | size_t sram_size; | |
50 | } LxBoardDesc; | |
0200db65 MF |
51 | |
52 | typedef struct Lx60FpgaState { | |
53 | MemoryRegion iomem; | |
54 | uint32_t leds; | |
55 | uint32_t switches; | |
56 | } Lx60FpgaState; | |
57 | ||
58 | static void lx60_fpga_reset(void *opaque) | |
59 | { | |
60 | Lx60FpgaState *s = opaque; | |
61 | ||
62 | s->leds = 0; | |
63 | s->switches = 0; | |
64 | } | |
65 | ||
a8170e5e | 66 | static uint64_t lx60_fpga_read(void *opaque, hwaddr addr, |
0200db65 MF |
67 | unsigned size) |
68 | { | |
69 | Lx60FpgaState *s = opaque; | |
70 | ||
71 | switch (addr) { | |
72 | case 0x0: /*build date code*/ | |
556ba668 | 73 | return 0x09272011; |
0200db65 MF |
74 | |
75 | case 0x4: /*processor clock frequency, Hz*/ | |
76 | return 10000000; | |
77 | ||
78 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
79 | return s->leds; | |
80 | ||
81 | case 0xc: /*DIP switches (off = 0, on = 1)*/ | |
82 | return s->switches; | |
83 | } | |
84 | return 0; | |
85 | } | |
86 | ||
a8170e5e | 87 | static void lx60_fpga_write(void *opaque, hwaddr addr, |
0200db65 MF |
88 | uint64_t val, unsigned size) |
89 | { | |
90 | Lx60FpgaState *s = opaque; | |
91 | ||
92 | switch (addr) { | |
93 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
94 | s->leds = val; | |
95 | break; | |
96 | ||
97 | case 0x10: /*board reset*/ | |
98 | if (val == 0xdead) { | |
99 | qemu_system_reset_request(); | |
100 | } | |
101 | break; | |
102 | } | |
103 | } | |
104 | ||
105 | static const MemoryRegionOps lx60_fpga_ops = { | |
106 | .read = lx60_fpga_read, | |
107 | .write = lx60_fpga_write, | |
108 | .endianness = DEVICE_NATIVE_ENDIAN, | |
109 | }; | |
110 | ||
111 | static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space, | |
a8170e5e | 112 | hwaddr base) |
0200db65 MF |
113 | { |
114 | Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState)); | |
115 | ||
2c9b15ca | 116 | memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s, |
556ba668 | 117 | "lx60.fpga", 0x10000); |
0200db65 MF |
118 | memory_region_add_subregion(address_space, base, &s->iomem); |
119 | lx60_fpga_reset(s); | |
120 | qemu_register_reset(lx60_fpga_reset, s); | |
121 | return s; | |
122 | } | |
123 | ||
124 | static void lx60_net_init(MemoryRegion *address_space, | |
a8170e5e AK |
125 | hwaddr base, |
126 | hwaddr descriptors, | |
127 | hwaddr buffers, | |
0200db65 MF |
128 | qemu_irq irq, NICInfo *nd) |
129 | { | |
130 | DeviceState *dev; | |
131 | SysBusDevice *s; | |
132 | MemoryRegion *ram; | |
133 | ||
134 | dev = qdev_create(NULL, "open_eth"); | |
135 | qdev_set_nic_properties(dev, nd); | |
136 | qdev_init_nofail(dev); | |
137 | ||
1356b98d | 138 | s = SYS_BUS_DEVICE(dev); |
0200db65 MF |
139 | sysbus_connect_irq(s, 0, irq); |
140 | memory_region_add_subregion(address_space, base, | |
141 | sysbus_mmio_get_region(s, 0)); | |
142 | memory_region_add_subregion(address_space, descriptors, | |
143 | sysbus_mmio_get_region(s, 1)); | |
144 | ||
145 | ram = g_malloc(sizeof(*ram)); | |
f8ed85ac MA |
146 | memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384, |
147 | &error_fatal); | |
c5705a77 | 148 | vmstate_register_ram_global(ram); |
0200db65 MF |
149 | memory_region_add_subregion(address_space, buffers, ram); |
150 | } | |
151 | ||
68931a40 MF |
152 | static pflash_t *xtfpga_flash_init(MemoryRegion *address_space, |
153 | const LxBoardDesc *board, | |
154 | DriveInfo *dinfo, int be) | |
155 | { | |
156 | SysBusDevice *s; | |
157 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
158 | ||
159 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), | |
160 | &error_abort); | |
161 | qdev_prop_set_uint32(dev, "num-blocks", | |
162 | board->flash_size / board->flash_sector_size); | |
163 | qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size); | |
164 | qdev_prop_set_uint8(dev, "width", 4); | |
165 | qdev_prop_set_bit(dev, "big-endian", be); | |
166 | qdev_prop_set_string(dev, "name", "lx60.io.flash"); | |
167 | qdev_init_nofail(dev); | |
168 | s = SYS_BUS_DEVICE(dev); | |
169 | memory_region_add_subregion(address_space, board->flash_base, | |
170 | sysbus_mmio_get_region(s, 0)); | |
171 | return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); | |
172 | } | |
173 | ||
00b941e5 | 174 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
0200db65 | 175 | { |
00b941e5 AF |
176 | XtensaCPU *cpu = opaque; |
177 | ||
178 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
0200db65 MF |
179 | } |
180 | ||
1bba0dc9 | 181 | static void lx60_reset(void *opaque) |
0200db65 | 182 | { |
eded1267 | 183 | XtensaCPU *cpu = opaque; |
1bba0dc9 | 184 | |
eded1267 | 185 | cpu_reset(CPU(cpu)); |
0200db65 MF |
186 | } |
187 | ||
8bb3b575 MF |
188 | static uint64_t lx60_io_read(void *opaque, hwaddr addr, |
189 | unsigned size) | |
190 | { | |
191 | return 0; | |
192 | } | |
193 | ||
194 | static void lx60_io_write(void *opaque, hwaddr addr, | |
195 | uint64_t val, unsigned size) | |
196 | { | |
197 | } | |
198 | ||
199 | static const MemoryRegionOps lx60_io_ops = { | |
200 | .read = lx60_io_read, | |
201 | .write = lx60_io_write, | |
202 | .endianness = DEVICE_NATIVE_ENDIAN, | |
203 | }; | |
204 | ||
3ef96221 | 205 | static void lx_init(const LxBoardDesc *board, MachineState *machine) |
0200db65 MF |
206 | { |
207 | #ifdef TARGET_WORDS_BIGENDIAN | |
208 | int be = 1; | |
209 | #else | |
210 | int be = 0; | |
211 | #endif | |
212 | MemoryRegion *system_memory = get_system_memory(); | |
adbb0f75 | 213 | XtensaCPU *cpu = NULL; |
5bfcb36e | 214 | CPUXtensaState *env = NULL; |
0200db65 | 215 | MemoryRegion *ram, *rom, *system_io; |
82b25dc8 MF |
216 | DriveInfo *dinfo; |
217 | pflash_t *flash = NULL; | |
37b259d0 | 218 | QemuOpts *machine_opts = qemu_get_machine_opts(); |
3ef96221 | 219 | const char *cpu_model = machine->cpu_model; |
37b259d0 MF |
220 | const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); |
221 | const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); | |
996dfe98 | 222 | const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); |
f55b32e7 | 223 | const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); |
0200db65 MF |
224 | int n; |
225 | ||
82b25dc8 | 226 | if (!cpu_model) { |
e38077ff | 227 | cpu_model = XTENSA_DEFAULT_CPU_MODEL; |
82b25dc8 MF |
228 | } |
229 | ||
0200db65 | 230 | for (n = 0; n < smp_cpus; n++) { |
adbb0f75 AF |
231 | cpu = cpu_xtensa_init(cpu_model); |
232 | if (cpu == NULL) { | |
ebbb419a | 233 | error_report("unable to find CPU definition '%s'", |
8488ab02 MF |
234 | cpu_model); |
235 | exit(EXIT_FAILURE); | |
0200db65 | 236 | } |
adbb0f75 AF |
237 | env = &cpu->env; |
238 | ||
0200db65 | 239 | env->sregs[PRID] = n; |
eded1267 | 240 | qemu_register_reset(lx60_reset, cpu); |
0200db65 MF |
241 | /* Need MMU initialized prior to ELF loading, |
242 | * so that ELF gets loaded into virtual addresses | |
243 | */ | |
adbb0f75 | 244 | cpu_reset(CPU(cpu)); |
0200db65 MF |
245 | } |
246 | ||
247 | ram = g_malloc(sizeof(*ram)); | |
49946538 | 248 | memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size, |
f8ed85ac | 249 | &error_fatal); |
c5705a77 | 250 | vmstate_register_ram_global(ram); |
0200db65 MF |
251 | memory_region_add_subregion(system_memory, 0, ram); |
252 | ||
0200db65 | 253 | system_io = g_malloc(sizeof(*system_io)); |
8bb3b575 MF |
254 | memory_region_init_io(system_io, NULL, &lx60_io_ops, NULL, "lx60.io", |
255 | 224 * 1024 * 1024); | |
0200db65 MF |
256 | memory_region_add_subregion(system_memory, 0xf0000000, system_io); |
257 | lx60_fpga_init(system_io, 0x0d020000); | |
a005d073 | 258 | if (nd_table[0].used) { |
0200db65 MF |
259 | lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, |
260 | xtensa_get_extint(env, 1), nd_table); | |
261 | } | |
262 | ||
263 | if (!serial_hds[0]) { | |
264 | serial_hds[0] = qemu_chr_new("serial0", "null", NULL); | |
265 | } | |
266 | ||
267 | serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), | |
268 | 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); | |
269 | ||
82b25dc8 MF |
270 | dinfo = drive_get(IF_PFLASH, 0, 0); |
271 | if (dinfo) { | |
68931a40 | 272 | flash = xtfpga_flash_init(system_io, board, dinfo, be); |
82b25dc8 MF |
273 | } |
274 | ||
275 | /* Use presence of kernel file name as 'boot from SRAM' switch. */ | |
0200db65 | 276 | if (kernel_filename) { |
364d4802 | 277 | uint32_t entry_point = env->pc; |
b6edea8b | 278 | size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ |
a9a28591 MF |
279 | uint32_t tagptr = 0xfe000000 + board->sram_size; |
280 | uint32_t cur_tagptr; | |
b6edea8b MF |
281 | BpMemInfo memory_location = { |
282 | .type = tswap32(MEMORY_TYPE_CONVENTIONAL), | |
283 | .start = tswap32(0), | |
284 | .end = tswap32(machine->ram_size), | |
285 | }; | |
996dfe98 MF |
286 | uint32_t lowmem_end = machine->ram_size < 0x08000000 ? |
287 | machine->ram_size : 0x08000000; | |
288 | uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); | |
a9a28591 | 289 | |
292627bb | 290 | rom = g_malloc(sizeof(*rom)); |
49946538 | 291 | memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size, |
f8ed85ac | 292 | &error_fatal); |
c5705a77 | 293 | vmstate_register_ram_global(rom); |
292627bb MF |
294 | memory_region_add_subregion(system_memory, 0xfe000000, rom); |
295 | ||
a9a28591 MF |
296 | if (kernel_cmdline) { |
297 | bp_size += get_tag_size(strlen(kernel_cmdline) + 1); | |
298 | } | |
996dfe98 MF |
299 | if (dtb_filename) { |
300 | bp_size += get_tag_size(sizeof(uint32_t)); | |
301 | } | |
f55b32e7 MF |
302 | if (initrd_filename) { |
303 | bp_size += get_tag_size(sizeof(BpMemInfo)); | |
304 | } | |
a9a28591 | 305 | |
292627bb | 306 | /* Put kernel bootparameters to the end of that SRAM */ |
a9a28591 MF |
307 | tagptr = (tagptr - bp_size) & ~0xff; |
308 | cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); | |
b6edea8b MF |
309 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, |
310 | sizeof(memory_location), &memory_location); | |
a9a28591 | 311 | |
292627bb | 312 | if (kernel_cmdline) { |
a9a28591 MF |
313 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, |
314 | strlen(kernel_cmdline) + 1, kernel_cmdline); | |
292627bb | 315 | } |
996dfe98 MF |
316 | if (dtb_filename) { |
317 | int fdt_size; | |
318 | void *fdt = load_device_tree(dtb_filename, &fdt_size); | |
319 | uint32_t dtb_addr = tswap32(cur_lowmem); | |
320 | ||
321 | if (!fdt) { | |
ebbb419a | 322 | error_report("could not load DTB '%s'", dtb_filename); |
996dfe98 MF |
323 | exit(EXIT_FAILURE); |
324 | } | |
325 | ||
326 | cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); | |
327 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, | |
328 | sizeof(dtb_addr), &dtb_addr); | |
329 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096); | |
330 | } | |
f55b32e7 MF |
331 | if (initrd_filename) { |
332 | BpMemInfo initrd_location = { 0 }; | |
333 | int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, | |
334 | lowmem_end - cur_lowmem); | |
335 | ||
336 | if (initrd_size < 0) { | |
337 | initrd_size = load_image_targphys(initrd_filename, | |
338 | cur_lowmem, | |
339 | lowmem_end - cur_lowmem); | |
340 | } | |
341 | if (initrd_size < 0) { | |
ebbb419a | 342 | error_report("could not load initrd '%s'", initrd_filename); |
f55b32e7 MF |
343 | exit(EXIT_FAILURE); |
344 | } | |
345 | initrd_location.start = tswap32(cur_lowmem); | |
346 | initrd_location.end = tswap32(cur_lowmem + initrd_size); | |
347 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, | |
348 | sizeof(initrd_location), &initrd_location); | |
349 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096); | |
350 | } | |
a9a28591 MF |
351 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); |
352 | env->regs[2] = tagptr; | |
353 | ||
0200db65 MF |
354 | uint64_t elf_entry; |
355 | uint64_t elf_lowaddr; | |
00b941e5 | 356 | int success = load_elf(kernel_filename, translate_phys_addr, cpu, |
943cd387 | 357 | &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0); |
0200db65 | 358 | if (success > 0) { |
364d4802 MF |
359 | entry_point = elf_entry; |
360 | } else { | |
361 | hwaddr ep; | |
362 | int is_linux; | |
25bda50a | 363 | success = load_uimage(kernel_filename, &ep, NULL, &is_linux, |
6d2e4530 | 364 | translate_phys_addr, cpu); |
364d4802 MF |
365 | if (success > 0 && is_linux) { |
366 | entry_point = ep; | |
367 | } else { | |
ebbb419a | 368 | error_report("could not load kernel '%s'", |
364d4802 MF |
369 | kernel_filename); |
370 | exit(EXIT_FAILURE); | |
371 | } | |
372 | } | |
373 | if (entry_point != env->pc) { | |
374 | static const uint8_t jx_a0[] = { | |
375 | #ifdef TARGET_WORDS_BIGENDIAN | |
376 | 0x0a, 0, 0, | |
377 | #else | |
378 | 0xa0, 0, 0, | |
379 | #endif | |
380 | }; | |
381 | env->regs[0] = entry_point; | |
382 | cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0)); | |
0200db65 | 383 | } |
82b25dc8 MF |
384 | } else { |
385 | if (flash) { | |
386 | MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); | |
387 | MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); | |
388 | ||
2c9b15ca | 389 | memory_region_init_alias(flash_io, NULL, "lx60.flash", |
37ed7c4b MF |
390 | flash_mr, board->flash_boot_base, |
391 | board->flash_size - board->flash_boot_base < 0x02000000 ? | |
392 | board->flash_size - board->flash_boot_base : 0x02000000); | |
82b25dc8 MF |
393 | memory_region_add_subregion(system_memory, 0xfe000000, |
394 | flash_io); | |
395 | } | |
0200db65 MF |
396 | } |
397 | } | |
398 | ||
3ef96221 | 399 | static void xtensa_lx60_init(MachineState *machine) |
0200db65 | 400 | { |
82b25dc8 | 401 | static const LxBoardDesc lx60_board = { |
68931a40 | 402 | .flash_base = 0x08000000, |
e0db904d | 403 | .flash_size = 0x00400000, |
82b25dc8 MF |
404 | .flash_sector_size = 0x10000, |
405 | .sram_size = 0x20000, | |
406 | }; | |
3ef96221 | 407 | lx_init(&lx60_board, machine); |
82b25dc8 MF |
408 | } |
409 | ||
3ef96221 | 410 | static void xtensa_lx200_init(MachineState *machine) |
82b25dc8 MF |
411 | { |
412 | static const LxBoardDesc lx200_board = { | |
68931a40 | 413 | .flash_base = 0x08000000, |
e0db904d | 414 | .flash_size = 0x01000000, |
82b25dc8 MF |
415 | .flash_sector_size = 0x20000, |
416 | .sram_size = 0x2000000, | |
417 | }; | |
3ef96221 | 418 | lx_init(&lx200_board, machine); |
0200db65 MF |
419 | } |
420 | ||
3ef96221 | 421 | static void xtensa_ml605_init(MachineState *machine) |
e0db904d MF |
422 | { |
423 | static const LxBoardDesc ml605_board = { | |
68931a40 | 424 | .flash_base = 0x08000000, |
12004c9e | 425 | .flash_size = 0x01000000, |
e0db904d MF |
426 | .flash_sector_size = 0x20000, |
427 | .sram_size = 0x2000000, | |
428 | }; | |
3ef96221 | 429 | lx_init(&ml605_board, machine); |
e0db904d MF |
430 | } |
431 | ||
3ef96221 | 432 | static void xtensa_kc705_init(MachineState *machine) |
e0db904d MF |
433 | { |
434 | static const LxBoardDesc kc705_board = { | |
68931a40 | 435 | .flash_base = 0x00000000, |
e0db904d | 436 | .flash_size = 0x08000000, |
37ed7c4b | 437 | .flash_boot_base = 0x06000000, |
e0db904d MF |
438 | .flash_sector_size = 0x20000, |
439 | .sram_size = 0x2000000, | |
440 | }; | |
3ef96221 | 441 | lx_init(&kc705_board, machine); |
e0db904d MF |
442 | } |
443 | ||
8a661aea | 444 | static void xtensa_lx60_class_init(ObjectClass *oc, void *data) |
e264d29d | 445 | { |
8a661aea AF |
446 | MachineClass *mc = MACHINE_CLASS(oc); |
447 | ||
e264d29d EH |
448 | mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
449 | mc->init = xtensa_lx60_init; | |
450 | mc->max_cpus = 4; | |
451 | } | |
0200db65 | 452 | |
8a661aea AF |
453 | static const TypeInfo xtensa_lx60_type = { |
454 | .name = MACHINE_TYPE_NAME("lx60"), | |
455 | .parent = TYPE_MACHINE, | |
456 | .class_init = xtensa_lx60_class_init, | |
457 | }; | |
82b25dc8 | 458 | |
8a661aea | 459 | static void xtensa_lx200_class_init(ObjectClass *oc, void *data) |
e264d29d | 460 | { |
8a661aea AF |
461 | MachineClass *mc = MACHINE_CLASS(oc); |
462 | ||
e264d29d EH |
463 | mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
464 | mc->init = xtensa_lx200_init; | |
465 | mc->max_cpus = 4; | |
466 | } | |
e0db904d | 467 | |
8a661aea AF |
468 | static const TypeInfo xtensa_lx200_type = { |
469 | .name = MACHINE_TYPE_NAME("lx200"), | |
470 | .parent = TYPE_MACHINE, | |
471 | .class_init = xtensa_lx200_class_init, | |
472 | }; | |
e264d29d | 473 | |
8a661aea | 474 | static void xtensa_ml605_class_init(ObjectClass *oc, void *data) |
e264d29d | 475 | { |
8a661aea AF |
476 | MachineClass *mc = MACHINE_CLASS(oc); |
477 | ||
e264d29d EH |
478 | mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
479 | mc->init = xtensa_ml605_init; | |
480 | mc->max_cpus = 4; | |
481 | } | |
482 | ||
8a661aea AF |
483 | static const TypeInfo xtensa_ml605_type = { |
484 | .name = MACHINE_TYPE_NAME("ml605"), | |
485 | .parent = TYPE_MACHINE, | |
486 | .class_init = xtensa_ml605_class_init, | |
487 | }; | |
e0db904d | 488 | |
8a661aea | 489 | static void xtensa_kc705_class_init(ObjectClass *oc, void *data) |
0200db65 | 490 | { |
8a661aea AF |
491 | MachineClass *mc = MACHINE_CLASS(oc); |
492 | ||
e264d29d EH |
493 | mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
494 | mc->init = xtensa_kc705_init; | |
495 | mc->max_cpus = 4; | |
0200db65 MF |
496 | } |
497 | ||
8a661aea AF |
498 | static const TypeInfo xtensa_kc705_type = { |
499 | .name = MACHINE_TYPE_NAME("kc705"), | |
500 | .parent = TYPE_MACHINE, | |
501 | .class_init = xtensa_kc705_class_init, | |
502 | }; | |
503 | ||
504 | static void xtensa_lx_machines_init(void) | |
505 | { | |
506 | type_register_static(&xtensa_lx60_type); | |
507 | type_register_static(&xtensa_lx200_type); | |
508 | type_register_static(&xtensa_ml605_type); | |
509 | type_register_static(&xtensa_kc705_type); | |
510 | } | |
511 | ||
512 | machine_init(xtensa_lx_machines_init) |