[qemu.git] / hw / zaurus.c

/*
 * Copyright (c) 2006-2008 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 */
#include "hw.h"
#include "pxa.h"
#include "sharpsl.h"

#undef REG_FMT
#if TARGET_PHYS_ADDR_BITS == 32
#define REG_FMT			"0x%02x"
#else
#define REG_FMT			"0x%02lx"
#endif

/* SCOOP devices */

struct scoop_info_s {
    qemu_irq handler[16];
    qemu_irq *in;
    uint16_t status;
    uint16_t power;
    uint32_t gpio_level;
    uint32_t gpio_dir;
    uint32_t prev_level;

    uint16_t mcr;
    uint16_t cdr;
    uint16_t ccr;
    uint16_t irr;
    uint16_t imr;
    uint16_t isr;
};

#define SCOOP_MCR	0x00
#define SCOOP_CDR	0x04
#define SCOOP_CSR	0x08
#define SCOOP_CPR	0x0c
#define SCOOP_CCR	0x10
#define SCOOP_IRR_IRM	0x14
#define SCOOP_IMR	0x18
#define SCOOP_ISR	0x1c
#define SCOOP_GPCR	0x20
#define SCOOP_GPWR	0x24
#define SCOOP_GPRR	0x28

static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
    uint32_t level, diff;
    int bit;
    level = s->gpio_level & s->gpio_dir;

    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
        bit = ffs(diff) - 1;
        qemu_set_irq(s->handler[bit], (level >> bit) & 1);
    }

    s->prev_level = level;
}

static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
{
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;

    switch (addr) {
    case SCOOP_MCR:
        return s->mcr;
    case SCOOP_CDR:
        return s->cdr;
    case SCOOP_CSR:
        return s->status;
    case SCOOP_CPR:
        return s->power;
    case SCOOP_CCR:
        return s->ccr;
    case SCOOP_IRR_IRM:
        return s->irr;
    case SCOOP_IMR:
        return s->imr;
    case SCOOP_ISR:
        return s->isr;
    case SCOOP_GPCR:
        return s->gpio_dir;
    case SCOOP_GPWR:
    case SCOOP_GPRR:
        return s->gpio_level;
    default:
        zaurus_printf("Bad register offset " REG_FMT "\n", addr);
    }

    return 0;
}

static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
    value &= 0xffff;

    switch (addr) {
    case SCOOP_MCR:
        s->mcr = value;
        break;
    case SCOOP_CDR:
        s->cdr = value;
        break;
    case SCOOP_CPR:
        s->power = value;
        if (value & 0x80)
            s->power |= 0x8040;
        break;
    case SCOOP_CCR:
        s->ccr = value;
        break;
    case SCOOP_IRR_IRM:
        s->irr = value;
        break;
    case SCOOP_IMR:
        s->imr = value;
        break;
    case SCOOP_ISR:
        s->isr = value;
        break;
    case SCOOP_GPCR:
        s->gpio_dir = value;
        scoop_gpio_handler_update(s);
        break;
    case SCOOP_GPWR:
    case SCOOP_GPRR:	/* GPRR is probably R/O in real HW */
        s->gpio_level = value & s->gpio_dir;
        scoop_gpio_handler_update(s);
        break;
    default:
        zaurus_printf("Bad register offset " REG_FMT "\n", addr);
    }
}

static CPUReadMemoryFunc *scoop_readfn[] = {
    scoop_readb,
    scoop_readb,
    scoop_readb,
};
static CPUWriteMemoryFunc *scoop_writefn[] = {
    scoop_writeb,
    scoop_writeb,
    scoop_writeb,
};

void scoop_gpio_set(void *opaque, int line, int level)
{
    struct scoop_info_s *s = (struct scoop_info_s *) s;

    if (level)
        s->gpio_level |= (1 << line);
    else
        s->gpio_level &= ~(1 << line);
}

qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
{
    return s->in;
}

void scoop_gpio_out_set(struct scoop_info_s *s, int line,
                qemu_irq handler) {
    if (line >= 16) {
        fprintf(stderr, "No GPIO pin %i\n", line);
        exit(-1);
    }

    s->handler[line] = handler;
}

static void scoop_save(QEMUFile *f, void *opaque)
{
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
    qemu_put_be16s(f, &s->status);
    qemu_put_be16s(f, &s->power);
    qemu_put_be32s(f, &s->gpio_level);
    qemu_put_be32s(f, &s->gpio_dir);
    qemu_put_be32s(f, &s->prev_level);
    qemu_put_be16s(f, &s->mcr);
    qemu_put_be16s(f, &s->cdr);
    qemu_put_be16s(f, &s->ccr);
    qemu_put_be16s(f, &s->irr);
    qemu_put_be16s(f, &s->imr);
    qemu_put_be16s(f, &s->isr);
}

static int scoop_load(QEMUFile *f, void *opaque, int version_id)
{
    uint16_t dummy;
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
    qemu_get_be16s(f, &s->status);
    qemu_get_be16s(f, &s->power);
    qemu_get_be32s(f, &s->gpio_level);
    qemu_get_be32s(f, &s->gpio_dir);
    qemu_get_be32s(f, &s->prev_level);
    qemu_get_be16s(f, &s->mcr);
    qemu_get_be16s(f, &s->cdr);
    qemu_get_be16s(f, &s->ccr);
    qemu_get_be16s(f, &s->irr);
    qemu_get_be16s(f, &s->imr);
    qemu_get_be16s(f, &s->isr);
    if (version_id < 1)
	    qemu_get_be16s(f, &dummy);

    return 0;
}

struct scoop_info_s *scoop_init(struct pxa2xx_state_s *cpu,
		int instance,
		target_phys_addr_t target_base) {
    int iomemtype;
    struct scoop_info_s *s;

    s = (struct scoop_info_s *)
            qemu_mallocz(sizeof(struct scoop_info_s));
    memset(s, 0, sizeof(struct scoop_info_s));

    s->status = 0x02;
    s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
    iomemtype = cpu_register_io_memory(0, scoop_readfn,
                    scoop_writefn, s);
    cpu_register_physical_memory(target_base, 0x1000, iomemtype);
    register_savevm("scoop", instance, 1, scoop_save, scoop_load, s);

    return s;
}

/* Write the bootloader parameters memory area.  */

#define MAGIC_CHG(a, b, c, d)	((d << 24) | (c << 16) | (b << 8) | a)

static struct __attribute__ ((__packed__)) sl_param_info {
    uint32_t comadj_keyword;
    int32_t comadj;

    uint32_t uuid_keyword;
    char uuid[16];

    uint32_t touch_keyword;
    int32_t touch_xp;
    int32_t touch_yp;
    int32_t touch_xd;
    int32_t touch_yd;

    uint32_t adadj_keyword;
    int32_t adadj;

    uint32_t phad_keyword;
    int32_t phadadj;
} zaurus_bootparam = {
    .comadj_keyword	= MAGIC_CHG('C', 'M', 'A', 'D'),
    .comadj		= 125,
    .uuid_keyword	= MAGIC_CHG('U', 'U', 'I', 'D'),
    .uuid		= { -1 },
    .touch_keyword	= MAGIC_CHG('T', 'U', 'C', 'H'),
    .touch_xp		= -1,
    .adadj_keyword	= MAGIC_CHG('B', 'V', 'A', 'D'),
    .adadj		= -1,
    .phad_keyword	= MAGIC_CHG('P', 'H', 'A', 'D'),
    .phadadj		= 0x01,
};

void sl_bootparam_write(target_phys_addr_t ptr)
{
    cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
                              sizeof(struct sl_param_info));
}
Commit	Line	Data
e33d8cdb AZ	1	/*
	2	* Copyright (c) 2006-2008 Openedhand Ltd.
	3	* Written by Andrzej Zaborowski <balrog@zabor.org>
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 or
	8	* (at your option) version 3 of the License.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
fad6cb1a AJ	15	* You should have received a copy of the GNU General Public License along
	16	* with this program; if not, write to the Free Software Foundation, Inc.,
	17	* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
e33d8cdb AZ	18	*/
	19	#include "hw.h"
	20	#include "pxa.h"
	21	#include "sharpsl.h"
	22
e33d8cdb AZ	23	#undef REG_FMT
	24	#if TARGET_PHYS_ADDR_BITS == 32
	25	#define REG_FMT "0x%02x"
	26	#else
	27	#define REG_FMT "0x%02lx"
	28	#endif
	29
	30	/* SCOOP devices */
	31
	32	struct scoop_info_s {
e33d8cdb AZ	33	qemu_irq handler[16];
	34	qemu_irq *in;
	35	uint16_t status;
	36	uint16_t power;
	37	uint32_t gpio_level;
	38	uint32_t gpio_dir;
	39	uint32_t prev_level;
	40
	41	uint16_t mcr;
	42	uint16_t cdr;
	43	uint16_t ccr;
	44	uint16_t irr;
	45	uint16_t imr;
	46	uint16_t isr;
e33d8cdb AZ	47	};
	48
	49	#define SCOOP_MCR 0x00
	50	#define SCOOP_CDR 0x04
	51	#define SCOOP_CSR 0x08
	52	#define SCOOP_CPR 0x0c
	53	#define SCOOP_CCR 0x10
	54	#define SCOOP_IRR_IRM 0x14
	55	#define SCOOP_IMR 0x18
	56	#define SCOOP_ISR 0x1c
	57	#define SCOOP_GPCR 0x20
	58	#define SCOOP_GPWR 0x24
	59	#define SCOOP_GPRR 0x28
	60
	61	static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
	62	uint32_t level, diff;
	63	int bit;
	64	level = s->gpio_level & s->gpio_dir;
	65
	66	for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
	67	bit = ffs(diff) - 1;
	68	qemu_set_irq(s->handler[bit], (level >> bit) & 1);
	69	}
	70
	71	s->prev_level = level;
	72	}
	73
	74	static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
	75	{
	76	struct scoop_info_s s = (struct scoop_info_s ) opaque;
e33d8cdb AZ	77
	78	switch (addr) {
	79	case SCOOP_MCR:
	80	return s->mcr;
	81	case SCOOP_CDR:
	82	return s->cdr;
	83	case SCOOP_CSR:
	84	return s->status;
	85	case SCOOP_CPR:
	86	return s->power;
	87	case SCOOP_CCR:
	88	return s->ccr;
	89	case SCOOP_IRR_IRM:
	90	return s->irr;
	91	case SCOOP_IMR:
	92	return s->imr;
	93	case SCOOP_ISR:
	94	return s->isr;
	95	case SCOOP_GPCR:
	96	return s->gpio_dir;
	97	case SCOOP_GPWR:
e33d8cdb	98	case SCOOP_GPRR:
1f163b14	99	return s->gpio_level;
e33d8cdb AZ	100	default:
	101	zaurus_printf("Bad register offset " REG_FMT "\n", addr);
	102	}
	103
	104	return 0;
	105	}
	106
	107	static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
	108	{
	109	struct scoop_info_s s = (struct scoop_info_s ) opaque;
e33d8cdb AZ	110	value &= 0xffff;
	111
	112	switch (addr) {
	113	case SCOOP_MCR:
	114	s->mcr = value;
	115	break;
	116	case SCOOP_CDR:
	117	s->cdr = value;
	118	break;
	119	case SCOOP_CPR:
	120	s->power = value;
	121	if (value & 0x80)
	122	s->power \|= 0x8040;
	123	break;
	124	case SCOOP_CCR:
	125	s->ccr = value;
	126	break;
	127	case SCOOP_IRR_IRM:
	128	s->irr = value;
	129	break;
	130	case SCOOP_IMR:
	131	s->imr = value;
	132	break;
	133	case SCOOP_ISR:
	134	s->isr = value;
	135	break;
	136	case SCOOP_GPCR:
	137	s->gpio_dir = value;
	138	scoop_gpio_handler_update(s);
	139	break;
	140	case SCOOP_GPWR:
1f163b14	141	case SCOOP_GPRR: /* GPRR is probably R/O in real HW */
e33d8cdb AZ	142	s->gpio_level = value & s->gpio_dir;
	143	scoop_gpio_handler_update(s);
	144	break;
e33d8cdb AZ	145	default:
	146	zaurus_printf("Bad register offset " REG_FMT "\n", addr);
	147	}
	148	}
	149
b1d8e52e	150	static CPUReadMemoryFunc *scoop_readfn[] = {
e33d8cdb AZ	151	scoop_readb,
	152	scoop_readb,
	153	scoop_readb,
	154	};
b1d8e52e	155	static CPUWriteMemoryFunc *scoop_writefn[] = {
e33d8cdb AZ	156	scoop_writeb,
	157	scoop_writeb,
	158	scoop_writeb,
	159	};
	160
	161	void scoop_gpio_set(void *opaque, int line, int level)
	162	{
	163	struct scoop_info_s s = (struct scoop_info_s ) s;
	164
	165	if (level)
	166	s->gpio_level \|= (1 << line);
	167	else
	168	s->gpio_level &= ~(1 << line);
	169	}
	170
	171	qemu_irq scoop_gpio_in_get(struct scoop_info_s s)
	172	{
	173	return s->in;
	174	}
	175
	176	void scoop_gpio_out_set(struct scoop_info_s *s, int line,
	177	qemu_irq handler) {
	178	if (line >= 16) {
	179	fprintf(stderr, "No GPIO pin %i\n", line);
	180	exit(-1);
	181	}
	182
	183	s->handler[line] = handler;
	184	}
	185
	186	static void scoop_save(QEMUFile f, void opaque)
	187	{
	188	struct scoop_info_s s = (struct scoop_info_s ) opaque;
	189	qemu_put_be16s(f, &s->status);
	190	qemu_put_be16s(f, &s->power);
	191	qemu_put_be32s(f, &s->gpio_level);
	192	qemu_put_be32s(f, &s->gpio_dir);
	193	qemu_put_be32s(f, &s->prev_level);
	194	qemu_put_be16s(f, &s->mcr);
	195	qemu_put_be16s(f, &s->cdr);
	196	qemu_put_be16s(f, &s->ccr);
	197	qemu_put_be16s(f, &s->irr);
	198	qemu_put_be16s(f, &s->imr);
	199	qemu_put_be16s(f, &s->isr);
e33d8cdb AZ	200	}
	201
	202	static int scoop_load(QEMUFile f, void opaque, int version_id)
	203	{
1f163b14	204	uint16_t dummy;
e33d8cdb AZ	205	struct scoop_info_s s = (struct scoop_info_s ) opaque;
	206	qemu_get_be16s(f, &s->status);
	207	qemu_get_be16s(f, &s->power);
	208	qemu_get_be32s(f, &s->gpio_level);
	209	qemu_get_be32s(f, &s->gpio_dir);
	210	qemu_get_be32s(f, &s->prev_level);
	211	qemu_get_be16s(f, &s->mcr);
	212	qemu_get_be16s(f, &s->cdr);
	213	qemu_get_be16s(f, &s->ccr);
	214	qemu_get_be16s(f, &s->irr);
	215	qemu_get_be16s(f, &s->imr);
	216	qemu_get_be16s(f, &s->isr);
1f163b14 AZ	217	if (version_id < 1)
1f163b14 AZ	218	qemu_get_be16s(f, &dummy);
e33d8cdb AZ	219
	220	return 0;
	221	}
	222
	223	struct scoop_info_s scoop_init(struct pxa2xx_state_s cpu,
	224	int instance,
	225	target_phys_addr_t target_base) {
	226	int iomemtype;
	227	struct scoop_info_s *s;
	228
	229	s = (struct scoop_info_s *)
	230	qemu_mallocz(sizeof(struct scoop_info_s));
	231	memset(s, 0, sizeof(struct scoop_info_s));
	232
e33d8cdb AZ	233	s->status = 0x02;
	234	s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
	235	iomemtype = cpu_register_io_memory(0, scoop_readfn,
	236	scoop_writefn, s);
8da3ff18	237	cpu_register_physical_memory(target_base, 0x1000, iomemtype);
1f163b14	238	register_savevm("scoop", instance, 1, scoop_save, scoop_load, s);
e33d8cdb AZ	239
	240	return s;
	241	}
	242
	243	/* Write the bootloader parameters memory area. */
	244
	245	#define MAGIC_CHG(a, b, c, d) ((d << 24) \| (c << 16) \| (b << 8) \| a)
	246
b1d8e52e	247	static struct __attribute__ ((__packed__)) sl_param_info {
e33d8cdb AZ	248	uint32_t comadj_keyword;
	249	int32_t comadj;
	250
	251	uint32_t uuid_keyword;
	252	char uuid[16];
	253
	254	uint32_t touch_keyword;
	255	int32_t touch_xp;
	256	int32_t touch_yp;
	257	int32_t touch_xd;
	258	int32_t touch_yd;
	259
	260	uint32_t adadj_keyword;
	261	int32_t adadj;
	262
	263	uint32_t phad_keyword;
	264	int32_t phadadj;
	265	} zaurus_bootparam = {
	266	.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
	267	.comadj = 125,
	268	.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
	269	.uuid = { -1 },
	270	.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
	271	.touch_xp = -1,
	272	.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
	273	.adadj = -1,
	274	.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
	275	.phadadj = 0x01,
	276	};
	277
f78630ab	278	void sl_bootparam_write(target_phys_addr_t ptr)
e33d8cdb	279	{
f78630ab PB	280	cpu_physical_memory_write(ptr, (void *)&zaurus_bootparam,
f78630ab PB	281	sizeof(struct sl_param_info));
e33d8cdb	282	}