[qemu.git] / hw / zaurus.c

/*
 * Copyright (c) 2006-2008 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 or
 * (at your option) version 3 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#include "hw.h"
#include "pxa.h"
#include "sharpsl.h"

#undef REG_FMT
#if TARGET_PHYS_ADDR_BITS == 32
#define REG_FMT			"0x%02x"
#else
#define REG_FMT			"0x%02lx"
#endif

/* SCOOP devices */

struct scoop_info_s {
    target_phys_addr_t target_base;
    qemu_irq handler[16];
    qemu_irq *in;
    uint16_t status;
    uint16_t power;
    uint32_t gpio_level;
    uint32_t gpio_dir;
    uint32_t prev_level;

    uint16_t mcr;
    uint16_t cdr;
    uint16_t ccr;
    uint16_t irr;
    uint16_t imr;
    uint16_t isr;
    uint16_t gprr;
};

#define SCOOP_MCR	0x00
#define SCOOP_CDR	0x04
#define SCOOP_CSR	0x08
#define SCOOP_CPR	0x0c
#define SCOOP_CCR	0x10
#define SCOOP_IRR_IRM	0x14
#define SCOOP_IMR	0x18
#define SCOOP_ISR	0x1c
#define SCOOP_GPCR	0x20
#define SCOOP_GPWR	0x24
#define SCOOP_GPRR	0x28

static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
    uint32_t level, diff;
    int bit;
    level = s->gpio_level & s->gpio_dir;

    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
        bit = ffs(diff) - 1;
        qemu_set_irq(s->handler[bit], (level >> bit) & 1);
    }

    s->prev_level = level;
}

static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
{
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
    addr -= s->target_base;

    switch (addr) {
    case SCOOP_MCR:
        return s->mcr;
    case SCOOP_CDR:
        return s->cdr;
    case SCOOP_CSR:
        return s->status;
    case SCOOP_CPR:
        return s->power;
    case SCOOP_CCR:
        return s->ccr;
    case SCOOP_IRR_IRM:
        return s->irr;
    case SCOOP_IMR:
        return s->imr;
    case SCOOP_ISR:
        return s->isr;
    case SCOOP_GPCR:
        return s->gpio_dir;
    case SCOOP_GPWR:
        return s->gpio_level;
    case SCOOP_GPRR:
        return s->gprr;
    default:
        zaurus_printf("Bad register offset " REG_FMT "\n", addr);
    }

    return 0;
}

static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
    addr -= s->target_base;
    value &= 0xffff;

    switch (addr) {
    case SCOOP_MCR:
        s->mcr = value;
        break;
    case SCOOP_CDR:
        s->cdr = value;
        break;
    case SCOOP_CPR:
        s->power = value;
        if (value & 0x80)
            s->power |= 0x8040;
        break;
    case SCOOP_CCR:
        s->ccr = value;
        break;
    case SCOOP_IRR_IRM:
        s->irr = value;
        break;
    case SCOOP_IMR:
        s->imr = value;
        break;
    case SCOOP_ISR:
        s->isr = value;
        break;
    case SCOOP_GPCR:
        s->gpio_dir = value;
        scoop_gpio_handler_update(s);
        break;
    case SCOOP_GPWR:
        s->gpio_level = value & s->gpio_dir;
        scoop_gpio_handler_update(s);
        break;
    case SCOOP_GPRR:
        s->gprr = value;
        break;
    default:
        zaurus_printf("Bad register offset " REG_FMT "\n", addr);
    }
}

CPUReadMemoryFunc *scoop_readfn[] = {
    scoop_readb,
    scoop_readb,
    scoop_readb,
};
CPUWriteMemoryFunc *scoop_writefn[] = {
    scoop_writeb,
    scoop_writeb,
    scoop_writeb,
};

void scoop_gpio_set(void *opaque, int line, int level)
{
    struct scoop_info_s *s = (struct scoop_info_s *) s;

    if (level)
        s->gpio_level |= (1 << line);
    else
        s->gpio_level &= ~(1 << line);
}

qemu_irq *scoop_gpio_in_get(struct scoop_info_s *s)
{
    return s->in;
}

void scoop_gpio_out_set(struct scoop_info_s *s, int line,
                qemu_irq handler) {
    if (line >= 16) {
        fprintf(stderr, "No GPIO pin %i\n", line);
        exit(-1);
    }

    s->handler[line] = handler;
}

static void scoop_save(QEMUFile *f, void *opaque)
{
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
    qemu_put_be16s(f, &s->status);
    qemu_put_be16s(f, &s->power);
    qemu_put_be32s(f, &s->gpio_level);
    qemu_put_be32s(f, &s->gpio_dir);
    qemu_put_be32s(f, &s->prev_level);
    qemu_put_be16s(f, &s->mcr);
    qemu_put_be16s(f, &s->cdr);
    qemu_put_be16s(f, &s->ccr);
    qemu_put_be16s(f, &s->irr);
    qemu_put_be16s(f, &s->imr);
    qemu_put_be16s(f, &s->isr);
    qemu_put_be16s(f, &s->gprr);
}

static int scoop_load(QEMUFile *f, void *opaque, int version_id)
{
    struct scoop_info_s *s = (struct scoop_info_s *) opaque;
    qemu_get_be16s(f, &s->status);
    qemu_get_be16s(f, &s->power);
    qemu_get_be32s(f, &s->gpio_level);
    qemu_get_be32s(f, &s->gpio_dir);
    qemu_get_be32s(f, &s->prev_level);
    qemu_get_be16s(f, &s->mcr);
    qemu_get_be16s(f, &s->cdr);
    qemu_get_be16s(f, &s->ccr);
    qemu_get_be16s(f, &s->irr);
    qemu_get_be16s(f, &s->imr);
    qemu_get_be16s(f, &s->isr);
    qemu_get_be16s(f, &s->gprr);

    return 0;
}

struct scoop_info_s *scoop_init(struct pxa2xx_state_s *cpu,
		int instance,
		target_phys_addr_t target_base) {
    int iomemtype;
    struct scoop_info_s *s;

    s = (struct scoop_info_s *)
            qemu_mallocz(sizeof(struct scoop_info_s));
    memset(s, 0, sizeof(struct scoop_info_s));

    s->target_base = target_base;
    s->status = 0x02;
    s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
    iomemtype = cpu_register_io_memory(0, scoop_readfn,
                    scoop_writefn, s);
    cpu_register_physical_memory(s->target_base, 0x1000, iomemtype);
    register_savevm("scoop", instance, 0, scoop_save, scoop_load, s);

    return s;
}

/* Write the bootloader parameters memory area.  */

#define MAGIC_CHG(a, b, c, d)	((d << 24) | (c << 16) | (b << 8) | a)

struct __attribute__ ((__packed__)) sl_param_info {
    uint32_t comadj_keyword;
    int32_t comadj;

    uint32_t uuid_keyword;
    char uuid[16];

    uint32_t touch_keyword;
    int32_t touch_xp;
    int32_t touch_yp;
    int32_t touch_xd;
    int32_t touch_yd;

    uint32_t adadj_keyword;
    int32_t adadj;

    uint32_t phad_keyword;
    int32_t phadadj;
} zaurus_bootparam = {
    .comadj_keyword	= MAGIC_CHG('C', 'M', 'A', 'D'),
    .comadj		= 125,
    .uuid_keyword	= MAGIC_CHG('U', 'U', 'I', 'D'),
    .uuid		= { -1 },
    .touch_keyword	= MAGIC_CHG('T', 'U', 'C', 'H'),
    .touch_xp		= -1,
    .adadj_keyword	= MAGIC_CHG('B', 'V', 'A', 'D'),
    .adadj		= -1,
    .phad_keyword	= MAGIC_CHG('P', 'H', 'A', 'D'),
    .phadadj		= 0x01,
};

void sl_bootparam_write(uint32_t ptr)
{
    memcpy(phys_ram_base + ptr, &zaurus_bootparam,
                    sizeof(struct sl_param_info));
}
Commit	Line	Data
e33d8cdb AZ	1	/*
	2	* Copyright (c) 2006-2008 Openedhand Ltd.
	3	* Written by Andrzej Zaborowski <balrog@zabor.org>
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 or
	8	* (at your option) version 3 of the License.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*/
	20	#include "hw.h"
	21	#include "pxa.h"
	22	#include "sharpsl.h"
	23
e33d8cdb AZ	24	#undef REG_FMT
	25	#if TARGET_PHYS_ADDR_BITS == 32
	26	#define REG_FMT "0x%02x"
	27	#else
	28	#define REG_FMT "0x%02lx"
	29	#endif
	30
	31	/* SCOOP devices */
	32
	33	struct scoop_info_s {
	34	target_phys_addr_t target_base;
	35	qemu_irq handler[16];
	36	qemu_irq *in;
	37	uint16_t status;
	38	uint16_t power;
	39	uint32_t gpio_level;
	40	uint32_t gpio_dir;
	41	uint32_t prev_level;
	42
	43	uint16_t mcr;
	44	uint16_t cdr;
	45	uint16_t ccr;
	46	uint16_t irr;
	47	uint16_t imr;
	48	uint16_t isr;
	49	uint16_t gprr;
	50	};
	51
	52	#define SCOOP_MCR 0x00
	53	#define SCOOP_CDR 0x04
	54	#define SCOOP_CSR 0x08
	55	#define SCOOP_CPR 0x0c
	56	#define SCOOP_CCR 0x10
	57	#define SCOOP_IRR_IRM 0x14
	58	#define SCOOP_IMR 0x18
	59	#define SCOOP_ISR 0x1c
	60	#define SCOOP_GPCR 0x20
	61	#define SCOOP_GPWR 0x24
	62	#define SCOOP_GPRR 0x28
	63
	64	static inline void scoop_gpio_handler_update(struct scoop_info_s *s) {
	65	uint32_t level, diff;
	66	int bit;
	67	level = s->gpio_level & s->gpio_dir;
	68
	69	for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
	70	bit = ffs(diff) - 1;
	71	qemu_set_irq(s->handler[bit], (level >> bit) & 1);
	72	}
	73
	74	s->prev_level = level;
	75	}
	76
	77	static uint32_t scoop_readb(void *opaque, target_phys_addr_t addr)
	78	{
	79	struct scoop_info_s s = (struct scoop_info_s ) opaque;
	80	addr -= s->target_base;
	81
	82	switch (addr) {
	83	case SCOOP_MCR:
	84	return s->mcr;
	85	case SCOOP_CDR:
	86	return s->cdr;
	87	case SCOOP_CSR:
88	return s->status;
89	case SCOOP_CPR:
90	return s->power;
91	case SCOOP_CCR:
92	return s->ccr;
93	case SCOOP_IRR_IRM:
94	return s->irr;
95	case SCOOP_IMR:
96	return s->imr;
97	case SCOOP_ISR:
98	return s->isr;
99	case SCOOP_GPCR:
100	return s->gpio_dir;
101	case SCOOP_GPWR:
102	return s->gpio_level;
103	case SCOOP_GPRR:
104	return s->gprr;
105	default:
106	zaurus_printf("Bad register offset " REG_FMT "\n", addr);
107	}
108
109	return 0;
110	}
111
112	static void scoop_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
113	{
114	struct scoop_info_s s = (struct scoop_info_s ) opaque;
115	addr -= s->target_base;
116	value &= 0xffff;
117
118	switch (addr) {
119	case SCOOP_MCR:
120	s->mcr = value;
121	break;
122	case SCOOP_CDR:
123	s->cdr = value;
124	break;
125	case SCOOP_CPR:
126	s->power = value;
127	if (value & 0x80)
128	s->power \|= 0x8040;
129	break;
130	case SCOOP_CCR:
131	s->ccr = value;
132	break;
133	case SCOOP_IRR_IRM:
134	s->irr = value;
135	break;
136	case SCOOP_IMR:
137	s->imr = value;
138	break;
139	case SCOOP_ISR:
140	s->isr = value;
141	break;
142	case SCOOP_GPCR:
143	s->gpio_dir = value;
144	scoop_gpio_handler_update(s);
145	break;
146	case SCOOP_GPWR:
147	s->gpio_level = value & s->gpio_dir;
148	scoop_gpio_handler_update(s);
149	break;
150	case SCOOP_GPRR:
151	s->gprr = value;
152	break;
153	default:
154	zaurus_printf("Bad register offset " REG_FMT "\n", addr);
155	}
156	}
157
158	CPUReadMemoryFunc *scoop_readfn[] = {
159	scoop_readb,
160	scoop_readb,
161	scoop_readb,
162	};
163	CPUWriteMemoryFunc *scoop_writefn[] = {
164	scoop_writeb,
165	scoop_writeb,
166	scoop_writeb,
167	};
168
169	void scoop_gpio_set(void *opaque, int line, int level)
170	{
171	struct scoop_info_s s = (struct scoop_info_s ) s;
172
173	if (level)
174	s->gpio_level \|= (1 << line);
175	else
176	s->gpio_level &= ~(1 << line);
177	}
178
179	qemu_irq scoop_gpio_in_get(struct scoop_info_s s)
180	{
181	return s->in;
182	}
183
184	void scoop_gpio_out_set(struct scoop_info_s *s, int line,
185	qemu_irq handler) {
186	if (line >= 16) {
187	fprintf(stderr, "No GPIO pin %i\n", line);
188	exit(-1);
189	}
190
191	s->handler[line] = handler;
192	}
193
194	static void scoop_save(QEMUFile f, void opaque)
195	{
196	struct scoop_info_s s = (struct scoop_info_s ) opaque;
197	qemu_put_be16s(f, &s->status);
198	qemu_put_be16s(f, &s->power);
199	qemu_put_be32s(f, &s->gpio_level);
200	qemu_put_be32s(f, &s->gpio_dir);
201	qemu_put_be32s(f, &s->prev_level);
202	qemu_put_be16s(f, &s->mcr);
203	qemu_put_be16s(f, &s->cdr);
204	qemu_put_be16s(f, &s->ccr);
205	qemu_put_be16s(f, &s->irr);
206	qemu_put_be16s(f, &s->imr);
207	qemu_put_be16s(f, &s->isr);
208	qemu_put_be16s(f, &s->gprr);
209	}
210
211	static int scoop_load(QEMUFile f, void opaque, int version_id)
212	{
213	struct scoop_info_s s = (struct scoop_info_s ) opaque;
214	qemu_get_be16s(f, &s->status);
215	qemu_get_be16s(f, &s->power);
216	qemu_get_be32s(f, &s->gpio_level);
217	qemu_get_be32s(f, &s->gpio_dir);
218	qemu_get_be32s(f, &s->prev_level);
219	qemu_get_be16s(f, &s->mcr);
220	qemu_get_be16s(f, &s->cdr);
221	qemu_get_be16s(f, &s->ccr);
222	qemu_get_be16s(f, &s->irr);
223	qemu_get_be16s(f, &s->imr);
224	qemu_get_be16s(f, &s->isr);
225	qemu_get_be16s(f, &s->gprr);
226
227	return 0;
228	}
229
230	struct scoop_info_s scoop_init(struct pxa2xx_state_s cpu,
231	int instance,
232	target_phys_addr_t target_base) {
233	int iomemtype;
234	struct scoop_info_s *s;
235
236	s = (struct scoop_info_s *)
237	qemu_mallocz(sizeof(struct scoop_info_s));
238	memset(s, 0, sizeof(struct scoop_info_s));
239
240	s->target_base = target_base;
241	s->status = 0x02;
242	s->in = qemu_allocate_irqs(scoop_gpio_set, s, 16);
243	iomemtype = cpu_register_io_memory(0, scoop_readfn,
244	scoop_writefn, s);
245	cpu_register_physical_memory(s->target_base, 0x1000, iomemtype);
246	register_savevm("scoop", instance, 0, scoop_save, scoop_load, s);
247
248	return s;
249	}
250
251	/* Write the bootloader parameters memory area. */
252
253	#define MAGIC_CHG(a, b, c, d) ((d << 24) \| (c << 16) \| (b << 8) \| a)
254
255	struct __attribute__ ((__packed__)) sl_param_info {
256	uint32_t comadj_keyword;
257	int32_t comadj;
258
259	uint32_t uuid_keyword;
260	char uuid[16];
261
262	uint32_t touch_keyword;
263	int32_t touch_xp;
264	int32_t touch_yp;
265	int32_t touch_xd;
266	int32_t touch_yd;
267
268	uint32_t adadj_keyword;
269	int32_t adadj;
270
271	uint32_t phad_keyword;
272	int32_t phadadj;
273	} zaurus_bootparam = {
274	.comadj_keyword = MAGIC_CHG('C', 'M', 'A', 'D'),
275	.comadj = 125,
276	.uuid_keyword = MAGIC_CHG('U', 'U', 'I', 'D'),
277	.uuid = { -1 },
278	.touch_keyword = MAGIC_CHG('T', 'U', 'C', 'H'),
279	.touch_xp = -1,
280	.adadj_keyword = MAGIC_CHG('B', 'V', 'A', 'D'),
281	.adadj = -1,
282	.phad_keyword = MAGIC_CHG('P', 'H', 'A', 'D'),
283	.phadadj = 0x01,
284	};
285
286	void sl_bootparam_write(uint32_t ptr)
287	{
288	memcpy(phys_ram_base + ptr, &zaurus_bootparam,
289	sizeof(struct sl_param_info));
290	}