[qemu.git] / include / exec / cpu-all.h

/*
 * defines common to all virtual CPUs
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#ifndef CPU_ALL_H
#define CPU_ALL_H

#include "qemu-common.h"
#include "exec/cpu-common.h"
#include "qemu/thread.h"
#include "qom/cpu.h"

/* some important defines:
 *
 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
 * memory accesses.
 *
 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
 * otherwise little endian.
 *
 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
 *
 * TARGET_WORDS_BIGENDIAN : same for target cpu
 */

#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
#define BSWAP_NEEDED
#endif

#ifdef BSWAP_NEEDED

static inline uint16_t tswap16(uint16_t s)
{
    return bswap16(s);
}

static inline uint32_t tswap32(uint32_t s)
{
    return bswap32(s);
}

static inline uint64_t tswap64(uint64_t s)
{
    return bswap64(s);
}

static inline void tswap16s(uint16_t *s)
{
    *s = bswap16(*s);
}

static inline void tswap32s(uint32_t *s)
{
    *s = bswap32(*s);
}

static inline void tswap64s(uint64_t *s)
{
    *s = bswap64(*s);
}

#else

static inline uint16_t tswap16(uint16_t s)
{
    return s;
}

static inline uint32_t tswap32(uint32_t s)
{
    return s;
}

static inline uint64_t tswap64(uint64_t s)
{
    return s;
}

static inline void tswap16s(uint16_t *s)
{
}

static inline void tswap32s(uint32_t *s)
{
}

static inline void tswap64s(uint64_t *s)
{
}

#endif

#if TARGET_LONG_SIZE == 4
#define tswapl(s) tswap32(s)
#define tswapls(s) tswap32s((uint32_t *)(s))
#define bswaptls(s) bswap32s(s)
#else
#define tswapl(s) tswap64(s)
#define tswapls(s) tswap64s((uint64_t *)(s))
#define bswaptls(s) bswap64s(s)
#endif

/* CPU memory access without any memory or io remapping */

/*
 * the generic syntax for the memory accesses is:
 *
 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
 *
 * store: st{type}{size}{endian}_{access_type}(ptr, val)
 *
 * type is:
 * (empty): integer access
 *   f    : float access
 *
 * sign is:
 * (empty): for floats or 32 bit size
 *   u    : unsigned
 *   s    : signed
 *
 * size is:
 *   b: 8 bits
 *   w: 16 bits
 *   l: 32 bits
 *   q: 64 bits
 *
 * endian is:
 * (empty): target cpu endianness or 8 bit access
 *   r    : reversed target cpu endianness (not implemented yet)
 *   be   : big endian (not implemented yet)
 *   le   : little endian (not implemented yet)
 *
 * access_type is:
 *   raw    : host memory access
 *   user   : user mode access using soft MMU
 *   kernel : kernel mode access using soft MMU
 */

/* target-endianness CPU memory access functions */
#if defined(TARGET_WORDS_BIGENDIAN)
#define lduw_p(p) lduw_be_p(p)
#define ldsw_p(p) ldsw_be_p(p)
#define ldl_p(p) ldl_be_p(p)
#define ldq_p(p) ldq_be_p(p)
#define ldfl_p(p) ldfl_be_p(p)
#define ldfq_p(p) ldfq_be_p(p)
#define stw_p(p, v) stw_be_p(p, v)
#define stl_p(p, v) stl_be_p(p, v)
#define stq_p(p, v) stq_be_p(p, v)
#define stfl_p(p, v) stfl_be_p(p, v)
#define stfq_p(p, v) stfq_be_p(p, v)
#else
#define lduw_p(p) lduw_le_p(p)
#define ldsw_p(p) ldsw_le_p(p)
#define ldl_p(p) ldl_le_p(p)
#define ldq_p(p) ldq_le_p(p)
#define ldfl_p(p) ldfl_le_p(p)
#define ldfq_p(p) ldfq_le_p(p)
#define stw_p(p, v) stw_le_p(p, v)
#define stl_p(p, v) stl_le_p(p, v)
#define stq_p(p, v) stq_le_p(p, v)
#define stfl_p(p, v) stfl_le_p(p, v)
#define stfq_p(p, v) stfq_le_p(p, v)
#endif

/* MMU memory access macros */

#if defined(CONFIG_USER_ONLY)
#include <assert.h>
#include "exec/user/abitypes.h"

/* On some host systems the guest address space is reserved on the host.
 * This allows the guest address space to be offset to a convenient location.
 */
#if defined(CONFIG_USE_GUEST_BASE)
extern unsigned long guest_base;
extern int have_guest_base;
extern unsigned long reserved_va;
#define GUEST_BASE guest_base
#define RESERVED_VA reserved_va
#else
#define GUEST_BASE 0ul
#define RESERVED_VA 0ul
#endif

/* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))

#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
#define h2g_valid(x) 1
#else
#define h2g_valid(x) ({ \
    unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
    (__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
    (!RESERVED_VA || (__guest < RESERVED_VA)); \
})
#endif

#define h2g_nocheck(x) ({ \
    unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
    (abi_ulong)__ret; \
})

#define h2g(x) ({ \
    /* Check if given address fits target address space */ \
    assert(h2g_valid(x)); \
    h2g_nocheck(x); \
})

#define saddr(x) g2h(x)
#define laddr(x) g2h(x)

#else /* !CONFIG_USER_ONLY */
/* NOTE: we use double casts if pointers and target_ulong have
   different sizes */
#define saddr(x) (uint8_t *)(intptr_t)(x)
#define laddr(x) (uint8_t *)(intptr_t)(x)
#endif

#define ldub_raw(p) ldub_p(laddr((p)))
#define ldsb_raw(p) ldsb_p(laddr((p)))
#define lduw_raw(p) lduw_p(laddr((p)))
#define ldsw_raw(p) ldsw_p(laddr((p)))
#define ldl_raw(p) ldl_p(laddr((p)))
#define ldq_raw(p) ldq_p(laddr((p)))
#define ldfl_raw(p) ldfl_p(laddr((p)))
#define ldfq_raw(p) ldfq_p(laddr((p)))
#define stb_raw(p, v) stb_p(saddr((p)), v)
#define stw_raw(p, v) stw_p(saddr((p)), v)
#define stl_raw(p, v) stl_p(saddr((p)), v)
#define stq_raw(p, v) stq_p(saddr((p)), v)
#define stfl_raw(p, v) stfl_p(saddr((p)), v)
#define stfq_raw(p, v) stfq_p(saddr((p)), v)


#if defined(CONFIG_USER_ONLY)

/* if user mode, no other memory access functions */
#define ldub(p) ldub_raw(p)
#define ldsb(p) ldsb_raw(p)
#define lduw(p) lduw_raw(p)
#define ldsw(p) ldsw_raw(p)
#define ldl(p) ldl_raw(p)
#define ldq(p) ldq_raw(p)
#define ldfl(p) ldfl_raw(p)
#define ldfq(p) ldfq_raw(p)
#define stb(p, v) stb_raw(p, v)
#define stw(p, v) stw_raw(p, v)
#define stl(p, v) stl_raw(p, v)
#define stq(p, v) stq_raw(p, v)
#define stfl(p, v) stfl_raw(p, v)
#define stfq(p, v) stfq_raw(p, v)

#define cpu_ldub_code(env1, p) ldub_raw(p)
#define cpu_ldsb_code(env1, p) ldsb_raw(p)
#define cpu_lduw_code(env1, p) lduw_raw(p)
#define cpu_ldsw_code(env1, p) ldsw_raw(p)
#define cpu_ldl_code(env1, p) ldl_raw(p)
#define cpu_ldq_code(env1, p) ldq_raw(p)

#define cpu_ldub_data(env, addr) ldub_raw(addr)
#define cpu_lduw_data(env, addr) lduw_raw(addr)
#define cpu_ldsw_data(env, addr) ldsw_raw(addr)
#define cpu_ldl_data(env, addr) ldl_raw(addr)
#define cpu_ldq_data(env, addr) ldq_raw(addr)

#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
#define cpu_stq_data(env, addr, data) stq_raw(addr, data)

#define cpu_ldub_kernel(env, addr) ldub_raw(addr)
#define cpu_lduw_kernel(env, addr) lduw_raw(addr)
#define cpu_ldsw_kernel(env, addr) ldsw_raw(addr)
#define cpu_ldl_kernel(env, addr) ldl_raw(addr)
#define cpu_ldq_kernel(env, addr) ldq_raw(addr)

#define cpu_stb_kernel(env, addr, data) stb_raw(addr, data)
#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)

#define ldub_kernel(p) ldub_raw(p)
#define ldsb_kernel(p) ldsb_raw(p)
#define lduw_kernel(p) lduw_raw(p)
#define ldsw_kernel(p) ldsw_raw(p)
#define ldl_kernel(p) ldl_raw(p)
#define ldq_kernel(p) ldq_raw(p)
#define ldfl_kernel(p) ldfl_raw(p)
#define ldfq_kernel(p) ldfq_raw(p)
#define stb_kernel(p, v) stb_raw(p, v)
#define stw_kernel(p, v) stw_raw(p, v)
#define stl_kernel(p, v) stl_raw(p, v)
#define stq_kernel(p, v) stq_raw(p, v)
#define stfl_kernel(p, v) stfl_raw(p, v)
#define stfq_kernel(p, vt) stfq_raw(p, v)

#define cpu_ldub_data(env, addr) ldub_raw(addr)
#define cpu_lduw_data(env, addr) lduw_raw(addr)
#define cpu_ldl_data(env, addr) ldl_raw(addr)

#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
#endif /* defined(CONFIG_USER_ONLY) */

/* page related stuff */

#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)

/* ??? These should be the larger of uintptr_t and target_ulong.  */
extern uintptr_t qemu_real_host_page_size;
extern uintptr_t qemu_host_page_size;
extern uintptr_t qemu_host_page_mask;

#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)

/* same as PROT_xxx */
#define PAGE_READ      0x0001
#define PAGE_WRITE     0x0002
#define PAGE_EXEC      0x0004
#define PAGE_BITS      (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
#define PAGE_VALID     0x0008
/* original state of the write flag (used when tracking self-modifying
   code */
#define PAGE_WRITE_ORG 0x0010
#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
/* FIXME: Code that sets/uses this is broken and needs to go away.  */
#define PAGE_RESERVED  0x0020
#endif

#if defined(CONFIG_USER_ONLY)
void page_dump(FILE *f);

typedef int (*walk_memory_regions_fn)(void *, abi_ulong,
                                      abi_ulong, unsigned long);
int walk_memory_regions(void *, walk_memory_regions_fn);

int page_get_flags(target_ulong address);
void page_set_flags(target_ulong start, target_ulong end, int flags);
int page_check_range(target_ulong start, target_ulong len, int flags);
#endif

CPUArchState *cpu_copy(CPUArchState *env);

void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
    GCC_FMT_ATTR(2, 3);

/* Flags for use in ENV->INTERRUPT_PENDING.

   The numbers assigned here are non-sequential in order to preserve
   binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
   previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
   the vmstate dump.  */

/* External hardware interrupt pending.  This is typically used for
   interrupts from devices.  */
#define CPU_INTERRUPT_HARD        0x0002

/* Exit the current TB.  This is typically used when some system-level device
   makes some change to the memory mapping.  E.g. the a20 line change.  */
#define CPU_INTERRUPT_EXITTB      0x0004

/* Halt the CPU.  */
#define CPU_INTERRUPT_HALT        0x0020

/* Debug event pending.  */
#define CPU_INTERRUPT_DEBUG       0x0080

/* Several target-specific external hardware interrupts.  Each target/cpu.h
   should define proper names based on these defines.  */
#define CPU_INTERRUPT_TGT_EXT_0   0x0008
#define CPU_INTERRUPT_TGT_EXT_1   0x0010
#define CPU_INTERRUPT_TGT_EXT_2   0x0040
#define CPU_INTERRUPT_TGT_EXT_3   0x0200
#define CPU_INTERRUPT_TGT_EXT_4   0x1000

/* Several target-specific internal interrupts.  These differ from the
   preceding target-specific interrupts in that they are intended to
   originate from within the cpu itself, typically in response to some
   instruction being executed.  These, therefore, are not masked while
   single-stepping within the debugger.  */
#define CPU_INTERRUPT_TGT_INT_0   0x0100
#define CPU_INTERRUPT_TGT_INT_1   0x0400
#define CPU_INTERRUPT_TGT_INT_2   0x0800
#define CPU_INTERRUPT_TGT_INT_3   0x2000

/* First unused bit: 0x4000.  */

/* The set of all bits that should be masked when single-stepping.  */
#define CPU_INTERRUPT_SSTEP_MASK \
    (CPU_INTERRUPT_HARD          \
     | CPU_INTERRUPT_TGT_EXT_0   \
     | CPU_INTERRUPT_TGT_EXT_1   \
     | CPU_INTERRUPT_TGT_EXT_2   \
     | CPU_INTERRUPT_TGT_EXT_3   \
     | CPU_INTERRUPT_TGT_EXT_4)

/* Breakpoint/watchpoint flags */
#define BP_MEM_READ           0x01
#define BP_MEM_WRITE          0x02
#define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
#define BP_STOP_BEFORE_ACCESS 0x04
#define BP_WATCHPOINT_HIT     0x08
#define BP_GDB                0x10
#define BP_CPU                0x20

int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
                          CPUBreakpoint **breakpoint);
int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
                          int flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
                          target_ulong len, int flags);
void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
void cpu_watchpoint_remove_all(CPUArchState *env, int mask);

#if !defined(CONFIG_USER_ONLY)

/* memory API */

extern ram_addr_t ram_size;

/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
#define RAM_PREALLOC_MASK   (1 << 0)

typedef struct RAMBlock {
    struct MemoryRegion *mr;
    uint8_t *host;
    ram_addr_t offset;
    ram_addr_t length;
    uint32_t flags;
    char idstr[256];
    /* Reads can take either the iothread or the ramlist lock.
     * Writes must take both locks.
     */
    QTAILQ_ENTRY(RAMBlock) next;
    int fd;
} RAMBlock;

typedef struct RAMList {
    QemuMutex mutex;
    /* Protected by the iothread lock.  */
    uint8_t *phys_dirty;
    RAMBlock *mru_block;
    /* Protected by the ramlist lock.  */
    QTAILQ_HEAD(, RAMBlock) blocks;
    uint32_t version;
} RAMList;
extern RAMList ram_list;

extern const char *mem_path;
extern int mem_prealloc;

/* Flags stored in the low bits of the TLB virtual address.  These are
   defined so that fast path ram access is all zeros.  */
/* Zero if TLB entry is valid.  */
#define TLB_INVALID_MASK   (1 << 3)
/* Set if TLB entry references a clean RAM page.  The iotlb entry will
   contain the page physical address.  */
#define TLB_NOTDIRTY    (1 << 4)
/* Set if TLB entry is an IO callback.  */
#define TLB_MMIO        (1 << 5)

void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
ram_addr_t last_ram_offset(void);
void qemu_mutex_lock_ramlist(void);
void qemu_mutex_unlock_ramlist(void);
#endif /* !CONFIG_USER_ONLY */

int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
                        uint8_t *buf, int len, int is_write);

#endif /* CPU_ALL_H */
Commit	Line	Data
5a9fdfec FB	1	/*
5a9fdfec FB	2	* defines common to all virtual CPUs
5fafdf24	3	*
5a9fdfec FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
5a9fdfec FB	18	*/
	19	#ifndef CPU_ALL_H
	20	#define CPU_ALL_H
	21
7d99a001	22	#include "qemu-common.h"
022c62cb	23	#include "exec/cpu-common.h"
b2a8658e	24	#include "qemu/thread.h"
f17ec444	25	#include "qom/cpu.h"
0ac4bd56	26
5fafdf24 TS	27	/* some important defines:
5fafdf24 TS	28	*
0ac4bd56 FB	29	* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
0ac4bd56 FB	30	* memory accesses.
5fafdf24	31	*
e2542fe2	32	* HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
0ac4bd56	33	* otherwise little endian.
5fafdf24	34	*
0ac4bd56	35	* (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
5fafdf24	36	*
0ac4bd56 FB	37	* TARGET_WORDS_BIGENDIAN : same for target cpu
	38	*/
	39
e2542fe2	40	#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
f193c797 FB	41	#define BSWAP_NEEDED
	42	#endif
	43
	44	#ifdef BSWAP_NEEDED
	45
	46	static inline uint16_t tswap16(uint16_t s)
	47	{
	48	return bswap16(s);
	49	}
	50
	51	static inline uint32_t tswap32(uint32_t s)
	52	{
	53	return bswap32(s);
	54	}
	55
	56	static inline uint64_t tswap64(uint64_t s)
	57	{
	58	return bswap64(s);
	59	}
	60
	61	static inline void tswap16s(uint16_t *s)
	62	{
	63	s = bswap16(s);
	64	}
	65
	66	static inline void tswap32s(uint32_t *s)
	67	{
	68	s = bswap32(s);
	69	}
	70
	71	static inline void tswap64s(uint64_t *s)
	72	{
	73	s = bswap64(s);
	74	}
	75
	76	#else
	77
	78	static inline uint16_t tswap16(uint16_t s)
	79	{
	80	return s;
	81	}
	82
	83	static inline uint32_t tswap32(uint32_t s)
	84	{
	85	return s;
	86	}
	87
	88	static inline uint64_t tswap64(uint64_t s)
	89	{
	90	return s;
	91	}
	92
	93	static inline void tswap16s(uint16_t *s)
	94	{
	95	}
	96
	97	static inline void tswap32s(uint32_t *s)
	98	{
	99	}
	100
	101	static inline void tswap64s(uint64_t *s)
	102	{
	103	}
	104
105	#endif
106
107	#if TARGET_LONG_SIZE == 4
108	#define tswapl(s) tswap32(s)
109	#define tswapls(s) tswap32s((uint32_t *)(s))
0a962c02	110	#define bswaptls(s) bswap32s(s)
f193c797 FB	111	#else
	112	#define tswapl(s) tswap64(s)
	113	#define tswapls(s) tswap64s((uint64_t *)(s))
0a962c02	114	#define bswaptls(s) bswap64s(s)
f193c797 FB	115	#endif
f193c797 FB	116
61382a50 FB	117	/* CPU memory access without any memory or io remapping */
61382a50 FB	118
83d73968 FB	119	/*
	120	* the generic syntax for the memory accesses is:
	121	*
	122	* load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
	123	*
	124	* store: st{type}{size}{endian}_{access_type}(ptr, val)
	125	*
	126	* type is:
	127	* (empty): integer access
	128	* f : float access
5fafdf24	129	*
83d73968 FB	130	* sign is:
	131	* (empty): for floats or 32 bit size
	132	* u : unsigned
	133	* s : signed
	134	*
	135	* size is:
	136	* b: 8 bits
	137	* w: 16 bits
	138	* l: 32 bits
	139	* q: 64 bits
5fafdf24	140	*
83d73968 FB	141	* endian is:
	142	* (empty): target cpu endianness or 8 bit access
	143	* r : reversed target cpu endianness (not implemented yet)
	144	* be : big endian (not implemented yet)
	145	* le : little endian (not implemented yet)
	146	*
	147	* access_type is:
	148	* raw : host memory access
	149	* user : user mode access using soft MMU
	150	* kernel : kernel mode access using soft MMU
	151	*/
2df3b95d	152
cbbab922	153	/* target-endianness CPU memory access functions */
2df3b95d FB	154	#if defined(TARGET_WORDS_BIGENDIAN)
	155	#define lduw_p(p) lduw_be_p(p)
	156	#define ldsw_p(p) ldsw_be_p(p)
	157	#define ldl_p(p) ldl_be_p(p)
	158	#define ldq_p(p) ldq_be_p(p)
	159	#define ldfl_p(p) ldfl_be_p(p)
	160	#define ldfq_p(p) ldfq_be_p(p)
	161	#define stw_p(p, v) stw_be_p(p, v)
	162	#define stl_p(p, v) stl_be_p(p, v)
	163	#define stq_p(p, v) stq_be_p(p, v)
	164	#define stfl_p(p, v) stfl_be_p(p, v)
	165	#define stfq_p(p, v) stfq_be_p(p, v)
	166	#else
	167	#define lduw_p(p) lduw_le_p(p)
	168	#define ldsw_p(p) ldsw_le_p(p)
	169	#define ldl_p(p) ldl_le_p(p)
	170	#define ldq_p(p) ldq_le_p(p)
	171	#define ldfl_p(p) ldfl_le_p(p)
	172	#define ldfq_p(p) ldfq_le_p(p)
	173	#define stw_p(p, v) stw_le_p(p, v)
	174	#define stl_p(p, v) stl_le_p(p, v)
	175	#define stq_p(p, v) stq_le_p(p, v)
	176	#define stfl_p(p, v) stfl_le_p(p, v)
	177	#define stfq_p(p, v) stfq_le_p(p, v)
5a9fdfec FB	178	#endif
5a9fdfec FB	179
61382a50 FB	180	/* MMU memory access macros */
61382a50 FB	181
53a5960a	182	#if defined(CONFIG_USER_ONLY)
0e62fd79	183	#include <assert.h>
022c62cb	184	#include "exec/user/abitypes.h"
0e62fd79	185
53a5960a PB	186	/* On some host systems the guest address space is reserved on the host.
	187	* This allows the guest address space to be offset to a convenient location.
	188	*/
379f6698 PB	189	#if defined(CONFIG_USE_GUEST_BASE)
	190	extern unsigned long guest_base;
	191	extern int have_guest_base;
68a1c816	192	extern unsigned long reserved_va;
379f6698	193	#define GUEST_BASE guest_base
18e9ea8a	194	#define RESERVED_VA reserved_va
379f6698 PB	195	#else
379f6698 PB	196	#define GUEST_BASE 0ul
18e9ea8a	197	#define RESERVED_VA 0ul
379f6698	198	#endif
53a5960a PB	199
53a5960a PB	200	/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
8d9dde94	201	#define g2h(x) ((void *)((unsigned long)(target_ulong)(x) + GUEST_BASE))
b9f83121 RH	202
	203	#if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
	204	#define h2g_valid(x) 1
	205	#else
	206	#define h2g_valid(x) ({ \
	207	unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
39879bbb AG	208	(__guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS)) && \
39879bbb AG	209	(!RESERVED_VA \|\| (__guest < RESERVED_VA)); \
b9f83121 RH	210	})
	211	#endif
	212
732f9e89	213	#define h2g_nocheck(x) ({ \
0e62fd79	214	unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
732f9e89 AG	215	(abi_ulong)__ret; \
	216	})
	217
	218	#define h2g(x) ({ \
0e62fd79	219	/* Check if given address fits target address space */ \
b9f83121	220	assert(h2g_valid(x)); \
732f9e89	221	h2g_nocheck(x); \
0e62fd79	222	})
53a5960a PB	223
	224	#define saddr(x) g2h(x)
	225	#define laddr(x) g2h(x)
	226
	227	#else /* !CONFIG_USER_ONLY */
c27004ec FB	228	/* NOTE: we use double casts if pointers and target_ulong have
c27004ec FB	229	different sizes */
27b0dc16 SW	230	#define saddr(x) (uint8_t *)(intptr_t)(x)
27b0dc16 SW	231	#define laddr(x) (uint8_t *)(intptr_t)(x)
53a5960a PB	232	#endif
	233
	234	#define ldub_raw(p) ldub_p(laddr((p)))
	235	#define ldsb_raw(p) ldsb_p(laddr((p)))
	236	#define lduw_raw(p) lduw_p(laddr((p)))
	237	#define ldsw_raw(p) ldsw_p(laddr((p)))
	238	#define ldl_raw(p) ldl_p(laddr((p)))
	239	#define ldq_raw(p) ldq_p(laddr((p)))
	240	#define ldfl_raw(p) ldfl_p(laddr((p)))
	241	#define ldfq_raw(p) ldfq_p(laddr((p)))
	242	#define stb_raw(p, v) stb_p(saddr((p)), v)
	243	#define stw_raw(p, v) stw_p(saddr((p)), v)
	244	#define stl_raw(p, v) stl_p(saddr((p)), v)
	245	#define stq_raw(p, v) stq_p(saddr((p)), v)
	246	#define stfl_raw(p, v) stfl_p(saddr((p)), v)
	247	#define stfq_raw(p, v) stfq_p(saddr((p)), v)
c27004ec FB	248
c27004ec FB	249
5fafdf24	250	#if defined(CONFIG_USER_ONLY)
61382a50 FB	251
	252	/* if user mode, no other memory access functions */
	253	#define ldub(p) ldub_raw(p)
	254	#define ldsb(p) ldsb_raw(p)
	255	#define lduw(p) lduw_raw(p)
	256	#define ldsw(p) ldsw_raw(p)
	257	#define ldl(p) ldl_raw(p)
	258	#define ldq(p) ldq_raw(p)
	259	#define ldfl(p) ldfl_raw(p)
	260	#define ldfq(p) ldfq_raw(p)
	261	#define stb(p, v) stb_raw(p, v)
	262	#define stw(p, v) stw_raw(p, v)
	263	#define stl(p, v) stl_raw(p, v)
	264	#define stq(p, v) stq_raw(p, v)
	265	#define stfl(p, v) stfl_raw(p, v)
	266	#define stfq(p, v) stfq_raw(p, v)
	267
e141ab52 BS	268	#define cpu_ldub_code(env1, p) ldub_raw(p)
	269	#define cpu_ldsb_code(env1, p) ldsb_raw(p)
	270	#define cpu_lduw_code(env1, p) lduw_raw(p)
	271	#define cpu_ldsw_code(env1, p) ldsw_raw(p)
	272	#define cpu_ldl_code(env1, p) ldl_raw(p)
	273	#define cpu_ldq_code(env1, p) ldq_raw(p)
92fc4b58 BS	274
	275	#define cpu_ldub_data(env, addr) ldub_raw(addr)
	276	#define cpu_lduw_data(env, addr) lduw_raw(addr)
	277	#define cpu_ldsw_data(env, addr) ldsw_raw(addr)
	278	#define cpu_ldl_data(env, addr) ldl_raw(addr)
	279	#define cpu_ldq_data(env, addr) ldq_raw(addr)
	280
	281	#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
	282	#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
	283	#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
	284	#define cpu_stq_data(env, addr, data) stq_raw(addr, data)
	285
	286	#define cpu_ldub_kernel(env, addr) ldub_raw(addr)
	287	#define cpu_lduw_kernel(env, addr) lduw_raw(addr)
	288	#define cpu_ldsw_kernel(env, addr) ldsw_raw(addr)
	289	#define cpu_ldl_kernel(env, addr) ldl_raw(addr)
	290	#define cpu_ldq_kernel(env, addr) ldq_raw(addr)
	291
	292	#define cpu_stb_kernel(env, addr, data) stb_raw(addr, data)
	293	#define cpu_stw_kernel(env, addr, data) stw_raw(addr, data)
	294	#define cpu_stl_kernel(env, addr, data) stl_raw(addr, data)
	295	#define cpu_stq_kernel(env, addr, data) stq_raw(addr, data)
61382a50 FB	296
	297	#define ldub_kernel(p) ldub_raw(p)
	298	#define ldsb_kernel(p) ldsb_raw(p)
	299	#define lduw_kernel(p) lduw_raw(p)
	300	#define ldsw_kernel(p) ldsw_raw(p)
	301	#define ldl_kernel(p) ldl_raw(p)
bc98a7ef	302	#define ldq_kernel(p) ldq_raw(p)
0ac4bd56 FB	303	#define ldfl_kernel(p) ldfl_raw(p)
0ac4bd56 FB	304	#define ldfq_kernel(p) ldfq_raw(p)
61382a50 FB	305	#define stb_kernel(p, v) stb_raw(p, v)
	306	#define stw_kernel(p, v) stw_raw(p, v)
	307	#define stl_kernel(p, v) stl_raw(p, v)
	308	#define stq_kernel(p, v) stq_raw(p, v)
0ac4bd56 FB	309	#define stfl_kernel(p, v) stfl_raw(p, v)
0ac4bd56 FB	310	#define stfq_kernel(p, vt) stfq_raw(p, v)
61382a50	311
2f5a189c BS	312	#define cpu_ldub_data(env, addr) ldub_raw(addr)
	313	#define cpu_lduw_data(env, addr) lduw_raw(addr)
	314	#define cpu_ldl_data(env, addr) ldl_raw(addr)
	315
	316	#define cpu_stb_data(env, addr, data) stb_raw(addr, data)
	317	#define cpu_stw_data(env, addr, data) stw_raw(addr, data)
	318	#define cpu_stl_data(env, addr, data) stl_raw(addr, data)
61382a50 FB	319	#endif /* defined(CONFIG_USER_ONLY) */
61382a50 FB	320
5a9fdfec FB	321	/* page related stuff */
5a9fdfec FB	322
03875444	323	#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
5a9fdfec FB	324	#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
	325	#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
	326
c6d50674 SW	327	/* ??? These should be the larger of uintptr_t and target_ulong. */
	328	extern uintptr_t qemu_real_host_page_size;
	329	extern uintptr_t qemu_host_page_size;
	330	extern uintptr_t qemu_host_page_mask;
5a9fdfec	331
83fb7adf	332	#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
5a9fdfec FB	333
	334	/* same as PROT_xxx */
	335	#define PAGE_READ 0x0001
	336	#define PAGE_WRITE 0x0002
	337	#define PAGE_EXEC 0x0004
	338	#define PAGE_BITS (PAGE_READ \| PAGE_WRITE \| PAGE_EXEC)
	339	#define PAGE_VALID 0x0008
	340	/* original state of the write flag (used when tracking self-modifying
	341	code */
5fafdf24	342	#define PAGE_WRITE_ORG 0x0010
2e9a5713 PB	343	#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
2e9a5713 PB	344	/* FIXME: Code that sets/uses this is broken and needs to go away. */
50a9569b	345	#define PAGE_RESERVED 0x0020
2e9a5713	346	#endif
5a9fdfec	347
b480d9b7	348	#if defined(CONFIG_USER_ONLY)
5a9fdfec	349	void page_dump(FILE *f);
5cd2c5b6	350
b480d9b7 PB	351	typedef int (walk_memory_regions_fn)(void , abi_ulong,
b480d9b7 PB	352	abi_ulong, unsigned long);
5cd2c5b6 RH	353	int walk_memory_regions(void *, walk_memory_regions_fn);
5cd2c5b6 RH	354
53a5960a PB	355	int page_get_flags(target_ulong address);
53a5960a PB	356	void page_set_flags(target_ulong start, target_ulong end, int flags);
3d97b40b	357	int page_check_range(target_ulong start, target_ulong len, int flags);
b480d9b7	358	#endif
5a9fdfec	359
9349b4f9	360	CPUArchState cpu_copy(CPUArchState env);
c5be9f08	361
9349b4f9	362	void QEMU_NORETURN cpu_abort(CPUArchState env, const char fmt, ...)
2c80e423	363	GCC_FMT_ATTR(2, 3);
db1a4972	364
9c76219e RH	365	/* Flags for use in ENV->INTERRUPT_PENDING.
	366
	367	The numbers assigned here are non-sequential in order to preserve
	368	binary compatibility with the vmstate dump. Bit 0 (0x0001) was
	369	previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
	370	the vmstate dump. */
	371
	372	/* External hardware interrupt pending. This is typically used for
	373	interrupts from devices. */
	374	#define CPU_INTERRUPT_HARD 0x0002
	375
	376	/* Exit the current TB. This is typically used when some system-level device
	377	makes some change to the memory mapping. E.g. the a20 line change. */
	378	#define CPU_INTERRUPT_EXITTB 0x0004
	379
	380	/* Halt the CPU. */
	381	#define CPU_INTERRUPT_HALT 0x0020
	382
	383	/* Debug event pending. */
	384	#define CPU_INTERRUPT_DEBUG 0x0080
	385
	386	/* Several target-specific external hardware interrupts. Each target/cpu.h
	387	should define proper names based on these defines. */
	388	#define CPU_INTERRUPT_TGT_EXT_0 0x0008
	389	#define CPU_INTERRUPT_TGT_EXT_1 0x0010
	390	#define CPU_INTERRUPT_TGT_EXT_2 0x0040
	391	#define CPU_INTERRUPT_TGT_EXT_3 0x0200
	392	#define CPU_INTERRUPT_TGT_EXT_4 0x1000
	393
	394	/* Several target-specific internal interrupts. These differ from the
07f35073	395	preceding target-specific interrupts in that they are intended to
9c76219e RH	396	originate from within the cpu itself, typically in response to some
	397	instruction being executed. These, therefore, are not masked while
	398	single-stepping within the debugger. */
	399	#define CPU_INTERRUPT_TGT_INT_0 0x0100
	400	#define CPU_INTERRUPT_TGT_INT_1 0x0400
	401	#define CPU_INTERRUPT_TGT_INT_2 0x0800
d362e757	402	#define CPU_INTERRUPT_TGT_INT_3 0x2000
9c76219e	403
d362e757	404	/* First unused bit: 0x4000. */
9c76219e	405
3125f763 RH	406	/* The set of all bits that should be masked when single-stepping. */
	407	#define CPU_INTERRUPT_SSTEP_MASK \
	408	(CPU_INTERRUPT_HARD \
	409	\| CPU_INTERRUPT_TGT_EXT_0 \
	410	\| CPU_INTERRUPT_TGT_EXT_1 \
	411	\| CPU_INTERRUPT_TGT_EXT_2 \
	412	\| CPU_INTERRUPT_TGT_EXT_3 \
	413	\| CPU_INTERRUPT_TGT_EXT_4)
98699967	414
a1d1bb31 AL	415	/* Breakpoint/watchpoint flags */
	416	#define BP_MEM_READ 0x01
	417	#define BP_MEM_WRITE 0x02
	418	#define BP_MEM_ACCESS (BP_MEM_READ \| BP_MEM_WRITE)
06d55cc1	419	#define BP_STOP_BEFORE_ACCESS 0x04
6e140f28	420	#define BP_WATCHPOINT_HIT 0x08
a1d1bb31	421	#define BP_GDB 0x10
2dc9f411	422	#define BP_CPU 0x20
a1d1bb31	423
9349b4f9	424	int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
a1d1bb31	425	CPUBreakpoint **breakpoint);
9349b4f9 AF	426	int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
	427	void cpu_breakpoint_remove_by_ref(CPUArchState env, CPUBreakpoint breakpoint);
	428	void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
	429	int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
a1d1bb31	430	int flags, CPUWatchpoint **watchpoint);
9349b4f9	431	int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
a1d1bb31	432	target_ulong len, int flags);
9349b4f9 AF	433	void cpu_watchpoint_remove_by_ref(CPUArchState env, CPUWatchpoint watchpoint);
9349b4f9 AF	434	void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
60897d36	435
b3755a91 PB	436	#if !defined(CONFIG_USER_ONLY)
b3755a91 PB	437
33417e70 FB	438	/* memory API */
33417e70 FB	439
c227f099	440	extern ram_addr_t ram_size;
f471a17e	441
cd19cfa2 HY	442	/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
	443	#define RAM_PREALLOC_MASK (1 << 0)
	444
f471a17e	445	typedef struct RAMBlock {
7c637366	446	struct MemoryRegion *mr;
f471a17e AW	447	uint8_t *host;
	448	ram_addr_t offset;
	449	ram_addr_t length;
cd19cfa2	450	uint32_t flags;
cc9e98cb	451	char idstr[256];
b2a8658e UD	452	/* Reads can take either the iothread or the ramlist lock.
	453	* Writes must take both locks.
	454	*/
a3161038	455	QTAILQ_ENTRY(RAMBlock) next;
04b16653	456	int fd;
f471a17e AW	457	} RAMBlock;
	458
	459	typedef struct RAMList {
b2a8658e UD	460	QemuMutex mutex;
b2a8658e UD	461	/* Protected by the iothread lock. */
f471a17e	462	uint8_t *phys_dirty;
0d6d3c87	463	RAMBlock *mru_block;
b2a8658e	464	/* Protected by the ramlist lock. */
a3161038	465	QTAILQ_HEAD(, RAMBlock) blocks;
f798b07f	466	uint32_t version;
f471a17e AW	467	} RAMList;
f471a17e AW	468	extern RAMList ram_list;
edf75d59	469
c902760f MT	470	extern const char *mem_path;
	471	extern int mem_prealloc;
	472
0f459d16 PB	473	/* Flags stored in the low bits of the TLB virtual address. These are
	474	defined so that fast path ram access is all zeros. */
	475	/* Zero if TLB entry is valid. */
	476	#define TLB_INVALID_MASK (1 << 3)
	477	/* Set if TLB entry references a clean RAM page. The iotlb entry will
	478	contain the page physical address. */
	479	#define TLB_NOTDIRTY (1 << 4)
	480	/* Set if TLB entry is an IO callback. */
	481	#define TLB_MMIO (1 << 5)
	482
055403b2	483	void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
652d7ec2	484	ram_addr_t last_ram_offset(void);
b2a8658e UD	485	void qemu_mutex_lock_ramlist(void);
b2a8658e UD	486	void qemu_mutex_unlock_ramlist(void);
b3755a91 PB	487	#endif /* !CONFIG_USER_ONLY */
b3755a91 PB	488
f17ec444	489	int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
b3755a91 PB	490	uint8_t *buf, int len, int is_write);
b3755a91 PB	491
5a9fdfec	492	#endif /* CPU_ALL_H */