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ab93bbe2 FB |
1 | /* |
2 | * common defines for all CPUs | |
5fafdf24 | 3 | * |
ab93bbe2 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
d6ea4236 | 9 | * version 2.1 of the License, or (at your option) any later version. |
ab93bbe2 FB |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
ab93bbe2 FB |
18 | */ |
19 | #ifndef CPU_DEFS_H | |
20 | #define CPU_DEFS_H | |
21 | ||
87ecb68b PB |
22 | #ifndef NEED_CPU_H |
23 | #error cpu.h included from common code | |
24 | #endif | |
25 | ||
87776ab7 | 26 | #include "qemu/host-utils.h" |
71aec354 | 27 | #include "qemu/thread.h" |
ce927ed9 | 28 | #ifndef CONFIG_USER_ONLY |
022c62cb | 29 | #include "exec/hwaddr.h" |
ce927ed9 | 30 | #endif |
fadc1cbe | 31 | #include "exec/memattrs.h" |
2e5b09fd | 32 | #include "hw/core/cpu.h" |
ab93bbe2 | 33 | |
74433bf0 RH |
34 | #include "cpu-param.h" |
35 | ||
35b66fc4 | 36 | #ifndef TARGET_LONG_BITS |
74433bf0 RH |
37 | # error TARGET_LONG_BITS must be defined in cpu-param.h |
38 | #endif | |
39 | #ifndef NB_MMU_MODES | |
40 | # error NB_MMU_MODES must be defined in cpu-param.h | |
41 | #endif | |
42 | #ifndef TARGET_PHYS_ADDR_SPACE_BITS | |
43 | # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h | |
44 | #endif | |
45 | #ifndef TARGET_VIRT_ADDR_SPACE_BITS | |
46 | # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h | |
47 | #endif | |
48 | #ifndef TARGET_PAGE_BITS | |
49 | # ifdef TARGET_PAGE_BITS_VARY | |
50 | # ifndef TARGET_PAGE_BITS_MIN | |
51 | # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h | |
52 | # endif | |
53 | # else | |
54 | # error TARGET_PAGE_BITS must be defined in cpu-param.h | |
55 | # endif | |
35b66fc4 FB |
56 | #endif |
57 | ||
4692a86f | 58 | #include "exec/target_long.h" |
35b66fc4 | 59 | |
b11ec7f2 | 60 | #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) |
a40ec84e | 61 | |
88e89a57 XT |
62 | /* use a fully associative victim tlb of 8 entries */ |
63 | #define CPU_VTLB_SIZE 8 | |
ab93bbe2 | 64 | |
355b1943 | 65 | #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 |
d656469f FB |
66 | #define CPU_TLB_ENTRY_BITS 4 |
67 | #else | |
68 | #define CPU_TLB_ENTRY_BITS 5 | |
69 | #endif | |
70 | ||
86e1eff8 EC |
71 | #define CPU_TLB_DYN_MIN_BITS 6 |
72 | #define CPU_TLB_DYN_DEFAULT_BITS 8 | |
73 | ||
86e1eff8 EC |
74 | # if HOST_LONG_BITS == 32 |
75 | /* Make sure we do not require a double-word shift for the TLB load */ | |
76 | # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) | |
77 | # else /* HOST_LONG_BITS == 64 */ | |
78 | /* | |
79 | * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == | |
80 | * 2**34 == 16G of address space. This is roughly what one would expect a | |
81 | * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel | |
82 | * Skylake's Level-2 STLB has 16 1G entries. | |
83 | * Also, make sure we do not size the TLB past the guest's address space. | |
84 | */ | |
f9919116 EB |
85 | # ifdef TARGET_PAGE_BITS_VARY |
86 | # define CPU_TLB_DYN_MAX_BITS \ | |
86e1eff8 | 87 | MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) |
f9919116 EB |
88 | # else |
89 | # define CPU_TLB_DYN_MAX_BITS \ | |
90 | MIN_CONST(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) | |
91 | # endif | |
86e1eff8 EC |
92 | # endif |
93 | ||
25d3ec58 | 94 | /* Minimalized TLB entry for use by TCG fast path. */ |
ab93bbe2 | 95 | typedef struct CPUTLBEntry { |
0f459d16 PB |
96 | /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address |
97 | bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not | |
98 | go directly to ram. | |
db8d7466 FB |
99 | bit 3 : indicates that the entry is invalid |
100 | bit 2..0 : zero | |
101 | */ | |
b4a4b8d0 PC |
102 | union { |
103 | struct { | |
104 | target_ulong addr_read; | |
105 | target_ulong addr_write; | |
106 | target_ulong addr_code; | |
107 | /* Addend to virtual address to get host address. IO accesses | |
108 | use the corresponding iotlb value. */ | |
109 | uintptr_t addend; | |
110 | }; | |
111 | /* padding to get a power of two size */ | |
112 | uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; | |
113 | }; | |
ab93bbe2 FB |
114 | } CPUTLBEntry; |
115 | ||
e85ef538 | 116 | QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); |
355b1943 | 117 | |
4cb884e9 FR |
118 | |
119 | #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ | |
120 | ||
121 | #if !defined(CONFIG_USER_ONLY) | |
25d3ec58 RH |
122 | /* |
123 | * The full TLB entry, which is not accessed by generated TCG code, | |
124 | * so the layout is not as critical as that of CPUTLBEntry. This is | |
125 | * also why we don't want to combine the two structs. | |
e469b22f | 126 | */ |
25d3ec58 | 127 | typedef struct CPUTLBEntryFull { |
ace41090 | 128 | /* |
25d3ec58 | 129 | * @xlat_section contains: |
ace41090 PM |
130 | * - in the lower TARGET_PAGE_BITS, a physical section number |
131 | * - with the lower TARGET_PAGE_BITS masked off, an offset which | |
132 | * must be added to the virtual address to obtain: | |
133 | * + the ram_addr_t of the target RAM (if the physical section | |
134 | * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) | |
135 | * + the offset within the target MemoryRegion (otherwise) | |
136 | */ | |
25d3ec58 | 137 | hwaddr xlat_section; |
40473689 RH |
138 | |
139 | /* | |
140 | * @phys_addr contains the physical address in the address space | |
141 | * given by cpu_asidx_from_attrs(cpu, @attrs). | |
142 | */ | |
143 | hwaddr phys_addr; | |
144 | ||
145 | /* @attrs contains the memory transaction attributes for the page. */ | |
fadc1cbe | 146 | MemTxAttrs attrs; |
40473689 RH |
147 | |
148 | /* @prot contains the complete protections for the page. */ | |
149 | uint8_t prot; | |
150 | ||
151 | /* @lg_page_size contains the log2 of the page size. */ | |
152 | uint8_t lg_page_size; | |
8c6953cf RH |
153 | |
154 | /* | |
155 | * Allow target-specific additions to this structure. | |
156 | * This may be used to cache items from the guest cpu | |
157 | * page tables for later use by the implementation. | |
158 | */ | |
159 | #ifdef TARGET_PAGE_ENTRY_EXTRA | |
160 | TARGET_PAGE_ENTRY_EXTRA | |
161 | #endif | |
25d3ec58 | 162 | } CPUTLBEntryFull; |
4cb884e9 | 163 | #endif /* !CONFIG_USER_ONLY */ |
e469b22f | 164 | |
4cb884e9 | 165 | #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) |
a40ec84e RH |
166 | /* |
167 | * Data elements that are per MMU mode, minus the bits accessed by | |
168 | * the TCG fast path. | |
169 | */ | |
1308e026 RH |
170 | typedef struct CPUTLBDesc { |
171 | /* | |
172 | * Describe a region covering all of the large pages allocated | |
173 | * into the tlb. When any page within this region is flushed, | |
174 | * we must flush the entire tlb. The region is matched if | |
175 | * (addr & large_page_mask) == large_page_addr. | |
176 | */ | |
177 | target_ulong large_page_addr; | |
178 | target_ulong large_page_mask; | |
79e42085 RH |
179 | /* host time (in ns) at the beginning of the time window */ |
180 | int64_t window_begin_ns; | |
181 | /* maximum number of entries observed in the window */ | |
182 | size_t window_max_entries; | |
a40ec84e | 183 | size_t n_used_entries; |
d5363e58 RH |
184 | /* The next index to use in the tlb victim table. */ |
185 | size_t vindex; | |
a40ec84e RH |
186 | /* The tlb victim table, in two parts. */ |
187 | CPUTLBEntry vtable[CPU_VTLB_SIZE]; | |
25d3ec58 RH |
188 | CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; |
189 | CPUTLBEntryFull *fulltlb; | |
1308e026 RH |
190 | } CPUTLBDesc; |
191 | ||
a40ec84e RH |
192 | /* |
193 | * Data elements that are per MMU mode, accessed by the fast path. | |
269bd5d8 | 194 | * The structure is aligned to aid loading the pair with one insn. |
a40ec84e RH |
195 | */ |
196 | typedef struct CPUTLBDescFast { | |
197 | /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ | |
198 | uintptr_t mask; | |
199 | /* The array of tlb entries itself. */ | |
200 | CPUTLBEntry *table; | |
269bd5d8 | 201 | } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); |
a40ec84e | 202 | |
53d28455 RH |
203 | /* |
204 | * Data elements that are shared between all MMU modes. | |
205 | */ | |
206 | typedef struct CPUTLBCommon { | |
a40ec84e | 207 | /* Serialize updates to f.table and d.vtable, and others as noted. */ |
53d28455 | 208 | QemuSpin lock; |
3d1523ce RH |
209 | /* |
210 | * Within dirty, for each bit N, modifications have been made to | |
211 | * mmu_idx N since the last time that mmu_idx was flushed. | |
212 | * Protected by tlb_c.lock. | |
213 | */ | |
214 | uint16_t dirty; | |
e09de0a2 RH |
215 | /* |
216 | * Statistics. These are not lock protected, but are read and | |
217 | * written atomically. This allows the monitor to print a snapshot | |
218 | * of the stats without interfering with the cpu. | |
219 | */ | |
220 | size_t full_flush_count; | |
221 | size_t part_flush_count; | |
222 | size_t elide_flush_count; | |
53d28455 RH |
223 | } CPUTLBCommon; |
224 | ||
225 | /* | |
a40ec84e | 226 | * The entire softmmu tlb, for all MMU modes. |
53d28455 | 227 | * The meaning of each of the MMU modes is defined in the target code. |
269bd5d8 RH |
228 | * Since this is placed within CPUNegativeOffsetState, the smallest |
229 | * negative offsets are at the end of the struct. | |
53d28455 | 230 | */ |
e6d86bed | 231 | |
a40ec84e | 232 | typedef struct CPUTLB { |
a40ec84e | 233 | CPUTLBCommon c; |
269bd5d8 RH |
234 | CPUTLBDesc d[NB_MMU_MODES]; |
235 | CPUTLBDescFast f[NB_MMU_MODES]; | |
a40ec84e | 236 | } CPUTLB; |
20cb400d | 237 | |
269bd5d8 RH |
238 | /* This will be used by TCG backends to compute offsets. */ |
239 | #define TLB_MASK_TABLE_OFS(IDX) \ | |
240 | ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) | |
20cb400d | 241 | |
a40ec84e | 242 | #else |
20cb400d | 243 | |
269bd5d8 | 244 | typedef struct CPUTLB { } CPUTLB; |
20cb400d | 245 | |
a40ec84e | 246 | #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ |
a316d335 | 247 | |
5b146dc7 | 248 | /* |
1eb21c42 | 249 | * This structure must be placed in ArchCPU immediately |
5b146dc7 RH |
250 | * before CPUArchState, as a field named "neg". |
251 | */ | |
252 | typedef struct CPUNegativeOffsetState { | |
269bd5d8 | 253 | CPUTLB tlb; |
5e140196 | 254 | IcountDecr icount_decr; |
5b146dc7 RH |
255 | } CPUNegativeOffsetState; |
256 | ||
ab93bbe2 | 257 | #endif |