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ab93bbe2 FB |
1 | /* |
2 | * common defines for all CPUs | |
5fafdf24 | 3 | * |
ab93bbe2 FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
ab93bbe2 FB |
18 | */ |
19 | #ifndef CPU_DEFS_H | |
20 | #define CPU_DEFS_H | |
21 | ||
87ecb68b PB |
22 | #ifndef NEED_CPU_H |
23 | #error cpu.h included from common code | |
24 | #endif | |
25 | ||
ab93bbe2 FB |
26 | #include "config.h" |
27 | #include <setjmp.h> | |
ed1c0bcb | 28 | #include <inttypes.h> |
1de7afc9 PB |
29 | #include "qemu/osdep.h" |
30 | #include "qemu/queue.h" | |
ce927ed9 | 31 | #ifndef CONFIG_USER_ONLY |
022c62cb | 32 | #include "exec/hwaddr.h" |
ce927ed9 | 33 | #endif |
ab93bbe2 | 34 | |
35b66fc4 FB |
35 | #ifndef TARGET_LONG_BITS |
36 | #error TARGET_LONG_BITS must be defined before including this header | |
37 | #endif | |
38 | ||
39 | #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) | |
40 | ||
ab6d960f | 41 | /* target_ulong is the type of a virtual address */ |
35b66fc4 | 42 | #if TARGET_LONG_SIZE == 4 |
6cfd9b52 PB |
43 | typedef int32_t target_long; |
44 | typedef uint32_t target_ulong; | |
c27004ec | 45 | #define TARGET_FMT_lx "%08x" |
b62b461b | 46 | #define TARGET_FMT_ld "%d" |
71c8b8fd | 47 | #define TARGET_FMT_lu "%u" |
35b66fc4 | 48 | #elif TARGET_LONG_SIZE == 8 |
6cfd9b52 PB |
49 | typedef int64_t target_long; |
50 | typedef uint64_t target_ulong; | |
26a76461 | 51 | #define TARGET_FMT_lx "%016" PRIx64 |
b62b461b | 52 | #define TARGET_FMT_ld "%" PRId64 |
71c8b8fd | 53 | #define TARGET_FMT_lu "%" PRIu64 |
35b66fc4 FB |
54 | #else |
55 | #error TARGET_LONG_SIZE undefined | |
56 | #endif | |
57 | ||
2be0071f FB |
58 | #define EXCP_INTERRUPT 0x10000 /* async interruption */ |
59 | #define EXCP_HLT 0x10001 /* hlt instruction reached */ | |
60 | #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ | |
5a1e3cfc | 61 | #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ |
72c1d3af | 62 | #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ |
ab93bbe2 | 63 | |
a316d335 FB |
64 | #define TB_JMP_CACHE_BITS 12 |
65 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
66 | ||
b362e5e0 PB |
67 | /* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for |
68 | addresses on the same page. The top bits are the same. This allows | |
69 | TLB invalidation to quickly clear a subset of the hash table. */ | |
70 | #define TB_JMP_PAGE_BITS (TB_JMP_CACHE_BITS / 2) | |
71 | #define TB_JMP_PAGE_SIZE (1 << TB_JMP_PAGE_BITS) | |
72 | #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) | |
73 | #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) | |
74 | ||
20cb400d | 75 | #if !defined(CONFIG_USER_ONLY) |
84b7b8e7 FB |
76 | #define CPU_TLB_BITS 8 |
77 | #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) | |
ab93bbe2 | 78 | |
355b1943 | 79 | #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 |
d656469f FB |
80 | #define CPU_TLB_ENTRY_BITS 4 |
81 | #else | |
82 | #define CPU_TLB_ENTRY_BITS 5 | |
83 | #endif | |
84 | ||
ab93bbe2 | 85 | typedef struct CPUTLBEntry { |
0f459d16 PB |
86 | /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address |
87 | bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not | |
88 | go directly to ram. | |
db8d7466 FB |
89 | bit 3 : indicates that the entry is invalid |
90 | bit 2..0 : zero | |
91 | */ | |
5fafdf24 TS |
92 | target_ulong addr_read; |
93 | target_ulong addr_write; | |
94 | target_ulong addr_code; | |
355b1943 | 95 | /* Addend to virtual address to get host address. IO accesses |
ee50add9 | 96 | use the corresponding iotlb value. */ |
3b2992e4 | 97 | uintptr_t addend; |
d656469f | 98 | /* padding to get a power of two size */ |
3b2992e4 SW |
99 | uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - |
100 | (sizeof(target_ulong) * 3 + | |
101 | ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + | |
102 | sizeof(uintptr_t))]; | |
ab93bbe2 FB |
103 | } CPUTLBEntry; |
104 | ||
e85ef538 | 105 | QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); |
355b1943 | 106 | |
20cb400d PB |
107 | #define CPU_COMMON_TLB \ |
108 | /* The meaning of the MMU modes is defined in the target code. */ \ | |
109 | CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ | |
a8170e5e | 110 | hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ |
d4c430a8 PB |
111 | target_ulong tlb_flush_addr; \ |
112 | target_ulong tlb_flush_mask; | |
20cb400d PB |
113 | |
114 | #else | |
115 | ||
116 | #define CPU_COMMON_TLB | |
117 | ||
118 | #endif | |
119 | ||
120 | ||
e2542fe2 | 121 | #ifdef HOST_WORDS_BIGENDIAN |
2e70f6ef PB |
122 | typedef struct icount_decr_u16 { |
123 | uint16_t high; | |
124 | uint16_t low; | |
125 | } icount_decr_u16; | |
126 | #else | |
127 | typedef struct icount_decr_u16 { | |
128 | uint16_t low; | |
129 | uint16_t high; | |
130 | } icount_decr_u16; | |
131 | #endif | |
132 | ||
a1d1bb31 AL |
133 | typedef struct CPUBreakpoint { |
134 | target_ulong pc; | |
135 | int flags; /* BP_* */ | |
72cf2d4f | 136 | QTAILQ_ENTRY(CPUBreakpoint) entry; |
a1d1bb31 AL |
137 | } CPUBreakpoint; |
138 | ||
139 | typedef struct CPUWatchpoint { | |
140 | target_ulong vaddr; | |
141 | target_ulong len_mask; | |
142 | int flags; /* BP_* */ | |
72cf2d4f | 143 | QTAILQ_ENTRY(CPUWatchpoint) entry; |
a1d1bb31 AL |
144 | } CPUWatchpoint; |
145 | ||
a20e31dc | 146 | #define CPU_TEMP_BUF_NLONGS 128 |
a316d335 | 147 | #define CPU_COMMON \ |
a316d335 | 148 | /* soft mmu support */ \ |
20cb400d | 149 | CPU_COMMON_TLB \ |
a316d335 FB |
150 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ |
151 | \ | |
2e70f6ef PB |
152 | int64_t icount_extra; /* Instructions until next timer event. */ \ |
153 | /* Number of cycles left, with interrupt flag in high bit. \ | |
154 | This allows a single read-compare-cbranch-write sequence to test \ | |
155 | for both decrementer underflow and exceptions. */ \ | |
156 | union { \ | |
157 | uint32_t u32; \ | |
158 | icount_decr_u16 u16; \ | |
159 | } icount_decr; \ | |
160 | uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ | |
161 | \ | |
a316d335 FB |
162 | /* from this point: preserved by CPU reset */ \ |
163 | /* ice debug support */ \ | |
72cf2d4f | 164 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ |
a316d335 | 165 | \ |
72cf2d4f | 166 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ |
a1d1bb31 | 167 | CPUWatchpoint *watchpoint_hit; \ |
56aebc89 | 168 | \ |
9133e39b | 169 | /* Core interrupt code */ \ |
6ab7e546 | 170 | sigjmp_buf jmp_env; \ |
acb6685f | 171 | int exception_index; \ |
9133e39b | 172 | \ |
a316d335 | 173 | /* user data */ \ |
01ba9816 | 174 | void *opaque; \ |
a316d335 | 175 | |
ab93bbe2 | 176 | #endif |