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Commit | Line | Data |
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43e3346e | 1 | /* |
ff90606f | 2 | * ASPEED SoC family |
43e3346e AJ |
3 | * |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * | |
6 | * Copyright 2016 IBM Corp. | |
7 | * | |
8 | * This code is licensed under the GPL version 2 or later. See | |
9 | * the COPYING file in the top-level directory. | |
10 | */ | |
11 | ||
ff90606f CLG |
12 | #ifndef ASPEED_SOC_H |
13 | #define ASPEED_SOC_H | |
43e3346e | 14 | |
f25c0ae1 | 15 | #include "hw/cpu/a15mpcore.h" |
356b230e | 16 | #include "hw/arm/armv7m.h" |
43e3346e | 17 | #include "hw/intc/aspeed_vic.h" |
334973bb | 18 | #include "hw/misc/aspeed_scu.h" |
199fd623 | 19 | #include "hw/adc/aspeed_adc.h" |
c2da8a8b | 20 | #include "hw/misc/aspeed_sdmc.h" |
118c82e7 | 21 | #include "hw/misc/aspeed_xdma.h" |
43e3346e | 22 | #include "hw/timer/aspeed_timer.h" |
ea5dcf4e | 23 | #include "hw/rtc/aspeed_rtc.h" |
16020011 | 24 | #include "hw/i2c/aspeed_i2c.h" |
3222165d | 25 | #include "hw/misc/aspeed_i3c.h" |
7c1c69bc | 26 | #include "hw/ssi/aspeed_smc.h" |
a3888d75 | 27 | #include "hw/misc/aspeed_hace.h" |
e1acf581 | 28 | #include "hw/misc/aspeed_sbc.h" |
013befe1 | 29 | #include "hw/watchdog/wdt_aspeed.h" |
ea337c65 | 30 | #include "hw/net/ftgmac100.h" |
ec150c7e | 31 | #include "target/arm/cpu.h" |
fdcc7c06 | 32 | #include "hw/gpio/aspeed_gpio.h" |
2bea128c | 33 | #include "hw/sd/aspeed_sdhci.h" |
bfdd34f1 | 34 | #include "hw/usb/hcd-ehci.h" |
db1015e9 | 35 | #include "qom/object.h" |
2ecf1726 | 36 | #include "hw/misc/aspeed_lpc.h" |
80beb085 | 37 | #include "hw/misc/unimp.h" |
55c57023 | 38 | #include "hw/misc/aspeed_peci.h" |
d2b3eaef | 39 | #include "hw/char/serial.h" |
43e3346e | 40 | |
dbcabeeb | 41 | #define ASPEED_SPIS_NUM 2 |
bfdd34f1 | 42 | #define ASPEED_EHCIS_NUM 2 |
6b2b2a70 | 43 | #define ASPEED_WDTS_NUM 4 |
ece09bee | 44 | #define ASPEED_CPUS_NUM 2 |
d300db02 | 45 | #define ASPEED_MACS_NUM 4 |
d2b3eaef | 46 | #define ASPEED_UARTS_NUM 13 |
72006c61 | 47 | #define ASPEED_JTAG_NUM 2 |
dbcabeeb | 48 | |
db1015e9 | 49 | struct AspeedSoCState { |
43e3346e AJ |
50 | /*< private >*/ |
51 | DeviceState parent; | |
52 | ||
53 | /*< public >*/ | |
ece09bee | 54 | ARMCPU cpu[ASPEED_CPUS_NUM]; |
f25c0ae1 | 55 | A15MPPrivState a7mpcore; |
356b230e | 56 | ARMv7MState armv7m; |
4dd9d554 | 57 | MemoryRegion *memory; |
95b56e17 | 58 | MemoryRegion *dram_mr; |
346160cb | 59 | MemoryRegion dram_container; |
74af4eec | 60 | MemoryRegion sram; |
43e3346e | 61 | AspeedVICState vic; |
75fb4577 | 62 | AspeedRtcState rtc; |
43e3346e | 63 | AspeedTimerCtrlState timerctrl; |
16020011 | 64 | AspeedI2CState i2c; |
3222165d | 65 | AspeedI3CState i3c; |
334973bb | 66 | AspeedSCUState scu; |
a3888d75 | 67 | AspeedHACEState hace; |
118c82e7 | 68 | AspeedXDMAState xdma; |
199fd623 | 69 | AspeedADCState adc; |
0e5803df | 70 | AspeedSMCState fmc; |
dbcabeeb | 71 | AspeedSMCState spi[ASPEED_SPIS_NUM]; |
bfdd34f1 | 72 | EHCISysBusState ehci[ASPEED_EHCIS_NUM]; |
e1acf581 | 73 | AspeedSBCState sbc; |
80beb085 | 74 | UnimplementedDeviceState sbc_unimplemented; |
c2da8a8b | 75 | AspeedSDMCState sdmc; |
f986ee1d | 76 | AspeedWDTState wdt[ASPEED_WDTS_NUM]; |
67340990 | 77 | FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; |
289251b0 | 78 | AspeedMiiState mii[ASPEED_MACS_NUM]; |
fdcc7c06 | 79 | AspeedGPIOState gpio; |
f25c0ae1 | 80 | AspeedGPIOState gpio_1_8v; |
2bea128c | 81 | AspeedSDHCIState sdhci; |
a29e3e12 | 82 | AspeedSDHCIState emmc; |
2ecf1726 | 83 | AspeedLPCState lpc; |
55c57023 | 84 | AspeedPECIState peci; |
d2b3eaef | 85 | SerialMM uart[ASPEED_UARTS_NUM]; |
356b230e | 86 | Clock *sysclk; |
80beb085 PD |
87 | UnimplementedDeviceState iomem; |
88 | UnimplementedDeviceState video; | |
89 | UnimplementedDeviceState emmc_boot_controller; | |
90 | UnimplementedDeviceState dpmcu; | |
72006c61 PMD |
91 | UnimplementedDeviceState pwm; |
92 | UnimplementedDeviceState espi; | |
93 | UnimplementedDeviceState udc; | |
94 | UnimplementedDeviceState sgpiom; | |
95 | UnimplementedDeviceState jtag[ASPEED_JTAG_NUM]; | |
db1015e9 | 96 | }; |
43e3346e | 97 | |
ff90606f | 98 | #define TYPE_ASPEED_SOC "aspeed-soc" |
a489d195 | 99 | OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC) |
43e3346e | 100 | |
db1015e9 | 101 | struct AspeedSoCClass { |
54ecafb7 CLG |
102 | DeviceClass parent_class; |
103 | ||
b033271f | 104 | const char *name; |
ba1ba5cc | 105 | const char *cpu_type; |
b033271f | 106 | uint32_t silicon_rev; |
74af4eec | 107 | uint64_t sram_size; |
dbcabeeb | 108 | int spis_num; |
bfdd34f1 | 109 | int ehcis_num; |
f986ee1d | 110 | int wdts_num; |
d300db02 | 111 | int macs_num; |
c5e1bdb9 | 112 | int uarts_num; |
b456b113 | 113 | const int *irqmap; |
d783d1fe | 114 | const hwaddr *memmap; |
ece09bee | 115 | uint32_t num_cpus; |
699db715 | 116 | qemu_irq (*get_irq)(AspeedSoCState *s, int dev); |
db1015e9 | 117 | }; |
b033271f | 118 | |
43e3346e | 119 | |
b456b113 | 120 | enum { |
347df6f8 EH |
121 | ASPEED_DEV_IOMEM, |
122 | ASPEED_DEV_UART1, | |
123 | ASPEED_DEV_UART2, | |
124 | ASPEED_DEV_UART3, | |
125 | ASPEED_DEV_UART4, | |
126 | ASPEED_DEV_UART5, | |
ab5e8605 PD |
127 | ASPEED_DEV_UART6, |
128 | ASPEED_DEV_UART7, | |
129 | ASPEED_DEV_UART8, | |
130 | ASPEED_DEV_UART9, | |
131 | ASPEED_DEV_UART10, | |
132 | ASPEED_DEV_UART11, | |
133 | ASPEED_DEV_UART12, | |
134 | ASPEED_DEV_UART13, | |
347df6f8 EH |
135 | ASPEED_DEV_VUART, |
136 | ASPEED_DEV_FMC, | |
137 | ASPEED_DEV_SPI1, | |
138 | ASPEED_DEV_SPI2, | |
139 | ASPEED_DEV_EHCI1, | |
140 | ASPEED_DEV_EHCI2, | |
141 | ASPEED_DEV_VIC, | |
142 | ASPEED_DEV_SDMC, | |
143 | ASPEED_DEV_SCU, | |
144 | ASPEED_DEV_ADC, | |
e1acf581 | 145 | ASPEED_DEV_SBC, |
fe31a2ec | 146 | ASPEED_DEV_EMMC_BC, |
347df6f8 EH |
147 | ASPEED_DEV_VIDEO, |
148 | ASPEED_DEV_SRAM, | |
149 | ASPEED_DEV_SDHCI, | |
150 | ASPEED_DEV_GPIO, | |
151 | ASPEED_DEV_GPIO_1_8V, | |
152 | ASPEED_DEV_RTC, | |
153 | ASPEED_DEV_TIMER1, | |
154 | ASPEED_DEV_TIMER2, | |
155 | ASPEED_DEV_TIMER3, | |
156 | ASPEED_DEV_TIMER4, | |
157 | ASPEED_DEV_TIMER5, | |
158 | ASPEED_DEV_TIMER6, | |
159 | ASPEED_DEV_TIMER7, | |
160 | ASPEED_DEV_TIMER8, | |
161 | ASPEED_DEV_WDT, | |
162 | ASPEED_DEV_PWM, | |
163 | ASPEED_DEV_LPC, | |
164 | ASPEED_DEV_IBT, | |
165 | ASPEED_DEV_I2C, | |
55c57023 | 166 | ASPEED_DEV_PECI, |
347df6f8 EH |
167 | ASPEED_DEV_ETH1, |
168 | ASPEED_DEV_ETH2, | |
169 | ASPEED_DEV_ETH3, | |
170 | ASPEED_DEV_ETH4, | |
171 | ASPEED_DEV_MII1, | |
172 | ASPEED_DEV_MII2, | |
173 | ASPEED_DEV_MII3, | |
174 | ASPEED_DEV_MII4, | |
175 | ASPEED_DEV_SDRAM, | |
176 | ASPEED_DEV_XDMA, | |
177 | ASPEED_DEV_EMMC, | |
c59f781e | 178 | ASPEED_DEV_KCS, |
a3888d75 | 179 | ASPEED_DEV_HACE, |
d9e9cd59 TL |
180 | ASPEED_DEV_DPMCU, |
181 | ASPEED_DEV_DP, | |
3222165d | 182 | ASPEED_DEV_I3C, |
72006c61 PMD |
183 | ASPEED_DEV_ESPI, |
184 | ASPEED_DEV_UDC, | |
185 | ASPEED_DEV_SGPIOM, | |
186 | ASPEED_DEV_JTAG0, | |
187 | ASPEED_DEV_JTAG1, | |
b456b113 CLG |
188 | }; |
189 | ||
699db715 | 190 | qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); |
d2b3eaef PD |
191 | bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp); |
192 | void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr); | |
346160cb | 193 | bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp); |
5bfcbda7 | 194 | void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr); |
80beb085 PD |
195 | void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev, |
196 | const char *name, hwaddr addr, | |
197 | uint64_t size); | |
1099ad10 PD |
198 | void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, |
199 | unsigned int count, int unit0); | |
699db715 | 200 | |
ff90606f | 201 | #endif /* ASPEED_SOC_H */ |