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a7d2d98c AF |
1 | /* |
2 | * QEMU lowRISC Ibex UART device | |
3 | * | |
4 | * Copyright (c) 2020 Western Digital | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef HW_IBEX_UART_H | |
26 | #define HW_IBEX_UART_H | |
27 | ||
28 | #include "hw/sysbus.h" | |
59093cc4 | 29 | #include "hw/registerfields.h" |
a7d2d98c AF |
30 | #include "chardev/char-fe.h" |
31 | #include "qemu/timer.h" | |
db1015e9 | 32 | #include "qom/object.h" |
a7d2d98c | 33 | |
59093cc4 AF |
34 | REG32(INTR_STATE, 0x00) |
35 | FIELD(INTR_STATE, TX_WATERMARK, 0, 1) | |
36 | FIELD(INTR_STATE, RX_WATERMARK, 1, 1) | |
37 | FIELD(INTR_STATE, TX_EMPTY, 2, 1) | |
38 | FIELD(INTR_STATE, RX_OVERFLOW, 3, 1) | |
39 | REG32(INTR_ENABLE, 0x04) | |
40 | REG32(INTR_TEST, 0x08) | |
41 | REG32(CTRL, 0x0C) | |
42 | FIELD(CTRL, TX_ENABLE, 0, 1) | |
43 | FIELD(CTRL, RX_ENABLE, 1, 1) | |
44 | FIELD(CTRL, NF, 2, 1) | |
45 | FIELD(CTRL, SLPBK, 4, 1) | |
46 | FIELD(CTRL, LLPBK, 5, 1) | |
47 | FIELD(CTRL, PARITY_EN, 6, 1) | |
48 | FIELD(CTRL, PARITY_ODD, 7, 1) | |
49 | FIELD(CTRL, RXBLVL, 8, 2) | |
50 | FIELD(CTRL, NCO, 16, 16) | |
51 | REG32(STATUS, 0x10) | |
52 | FIELD(STATUS, TXFULL, 0, 1) | |
53 | FIELD(STATUS, RXFULL, 1, 1) | |
54 | FIELD(STATUS, TXEMPTY, 2, 1) | |
55 | FIELD(STATUS, RXIDLE, 4, 1) | |
56 | FIELD(STATUS, RXEMPTY, 5, 1) | |
57 | REG32(RDATA, 0x14) | |
58 | REG32(WDATA, 0x18) | |
59 | REG32(FIFO_CTRL, 0x1c) | |
60 | FIELD(FIFO_CTRL, RXRST, 0, 1) | |
61 | FIELD(FIFO_CTRL, TXRST, 1, 1) | |
62 | FIELD(FIFO_CTRL, RXILVL, 2, 3) | |
63 | FIELD(FIFO_CTRL, TXILVL, 5, 2) | |
64 | REG32(FIFO_STATUS, 0x20) | |
65 | REG32(OVRD, 0x24) | |
66 | REG32(VAL, 0x28) | |
67 | REG32(TIMEOUT_CTRL, 0x2c) | |
a7d2d98c AF |
68 | |
69 | #define IBEX_UART_TX_FIFO_SIZE 16 | |
940aabb9 | 70 | #define IBEX_UART_CLOCK 50000000 /* 50MHz clock */ |
a7d2d98c AF |
71 | |
72 | #define TYPE_IBEX_UART "ibex-uart" | |
8063396b | 73 | OBJECT_DECLARE_SIMPLE_TYPE(IbexUartState, IBEX_UART) |
a7d2d98c | 74 | |
db1015e9 | 75 | struct IbexUartState { |
a7d2d98c AF |
76 | /* <private> */ |
77 | SysBusDevice parent_obj; | |
78 | ||
79 | /* <public> */ | |
80 | MemoryRegion mmio; | |
81 | ||
82 | uint8_t tx_fifo[IBEX_UART_TX_FIFO_SIZE]; | |
83 | uint32_t tx_level; | |
84 | ||
85 | QEMUTimer *fifo_trigger_handle; | |
86 | uint64_t char_tx_time; | |
87 | ||
88 | uint32_t uart_intr_state; | |
89 | uint32_t uart_intr_enable; | |
90 | uint32_t uart_ctrl; | |
91 | uint32_t uart_status; | |
92 | uint32_t uart_rdata; | |
93 | uint32_t uart_fifo_ctrl; | |
94 | uint32_t uart_fifo_status; | |
95 | uint32_t uart_ovrd; | |
96 | uint32_t uart_val; | |
97 | uint32_t uart_timeout_ctrl; | |
98 | ||
940aabb9 AF |
99 | Clock *f_clk; |
100 | ||
a7d2d98c AF |
101 | CharBackend chr; |
102 | qemu_irq tx_watermark; | |
103 | qemu_irq rx_watermark; | |
104 | qemu_irq tx_empty; | |
105 | qemu_irq rx_overflow; | |
db1015e9 | 106 | }; |
a7d2d98c | 107 | #endif /* HW_IBEX_UART_H */ |