[mirror_qemu.git] / include / hw / i386 / pc.h

#ifndef HW_PC_H
#define HW_PC_H

#include "qemu-common.h"
#include "exec/memory.h"
#include "hw/isa/isa.h"
#include "hw/block/fdc.h"
#include "net/net.h"
#include "hw/i386/ioapic.h"

#include "qemu/range.h"
#include "qemu/bitmap.h"
#include "sysemu/sysemu.h"
#include "hw/pci/pci.h"

/* PC-style peripherals (also used by other machines).  */

typedef struct PcPciInfo {
    Range w32;
    Range w64;
} PcPciInfo;

#define ACPI_PM_PROP_S3_DISABLED "disable_s3"
#define ACPI_PM_PROP_S4_DISABLED "disable_s4"
#define ACPI_PM_PROP_S4_VAL "s4_val"
#define ACPI_PM_PROP_SCI_INT "sci_int"
#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"

struct PcGuestInfo {
    bool has_pci_info;
    bool isapc_ram_fw;
    hwaddr ram_size;
    unsigned apic_id_limit;
    bool apic_xrupt_override;
    uint64_t numa_nodes;
    uint64_t *node_mem;
    uint64_t *node_cpu;
    FWCfgState *fw_cfg;
};

/* parallel.c */
static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
{
    DeviceState *dev;
    ISADevice *isadev;

    isadev = isa_try_create(bus, "isa-parallel");
    if (!isadev) {
        return false;
    }
    dev = DEVICE(isadev);
    qdev_prop_set_uint32(dev, "index", index);
    qdev_prop_set_chr(dev, "chardev", chr);
    if (qdev_init(dev) < 0) {
        return false;
    }
    return true;
}

bool parallel_mm_init(MemoryRegion *address_space,
                      hwaddr base, int it_shift, qemu_irq irq,
                      CharDriverState *chr);

/* i8259.c */

extern DeviceState *isa_pic;
qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
qemu_irq *kvm_i8259_init(ISABus *bus);
int pic_read_irq(DeviceState *d);
int pic_get_output(DeviceState *d);
void pic_info(Monitor *mon, const QDict *qdict);
void irq_info(Monitor *mon, const QDict *qdict);

/* Global System Interrupts */

#define GSI_NUM_PINS IOAPIC_NUM_PINS

typedef struct GSIState {
    qemu_irq i8259_irq[ISA_NUM_IRQS];
    qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
} GSIState;

void gsi_handler(void *opaque, int n, int level);

/* vmport.c */
typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);

static inline void vmport_init(ISABus *bus)
{
    isa_create_simple(bus, "vmport");
}

void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
void vmmouse_get_data(uint32_t *data);
void vmmouse_set_data(const uint32_t *data);

/* pckbd.c */

void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
                   MemoryRegion *region, ram_addr_t size,
                   hwaddr mask);
void i8042_isa_mouse_fake_event(void *opaque);
void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);

/* pc.c */
extern int fd_bootchk;

void pc_register_ferr_irq(qemu_irq irq);
void pc_acpi_smi_interrupt(void *opaque, int irq, int level);

void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
void pc_hot_add_cpu(const int64_t id, Error **errp);
void pc_acpi_init(const char *default_dsdt);

PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
                                ram_addr_t above_4g_mem_size);

#define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
#define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
#define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
#define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)

static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
{
    if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
        return 1ULL << 62;
    } else {
        return pci_hole64_size;
    }
}

void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
                        uint64_t pci_hole64_size);

FWCfgState *pc_memory_init(MemoryRegion *system_memory,
                           const char *kernel_filename,
                           const char *kernel_cmdline,
                           const char *initrd_filename,
                           ram_addr_t below_4g_mem_size,
                           ram_addr_t above_4g_mem_size,
                           MemoryRegion *rom_memory,
                           MemoryRegion **ram_memory,
                           PcGuestInfo *guest_info);
qemu_irq *pc_allocate_cpu_irq(void);
DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
                          ISADevice **rtc_state,
                          ISADevice **floppy,
                          bool no_vmport);
void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
                  const char *boot_device,
                  ISADevice *floppy, BusState *ide0, BusState *ide1,
                  ISADevice *s);
void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_pci_device_init(PCIBus *pci_bus);

typedef void (*cpu_set_smm_t)(int smm, void *arg);
void cpu_smm_register(cpu_set_smm_t callback, void *arg);

void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);

/* acpi_piix.c */

i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                       qemu_irq sci_irq, qemu_irq smi_irq,
                       int kvm_enabled, FWCfgState *fw_cfg);
void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);

/* hpet.c */
extern int no_hpet;

/* piix_pci.c */
struct PCII440FXState;
typedef struct PCII440FXState PCII440FXState;

PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
                    ISABus **isa_bus, qemu_irq *pic,
                    MemoryRegion *address_space_mem,
                    MemoryRegion *address_space_io,
                    ram_addr_t ram_size,
                    hwaddr pci_hole_start,
                    hwaddr pci_hole_size,
                    ram_addr_t above_4g_mem_size,
                    MemoryRegion *pci_memory,
                    MemoryRegion *ram_memory);

PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);

/* vga.c */
enum vga_retrace_method {
    VGA_RETRACE_DUMB,
    VGA_RETRACE_PRECISE
};

extern enum vga_retrace_method vga_retrace_method;

int isa_vga_mm_init(hwaddr vram_base,
                    hwaddr ctrl_base, int it_shift,
                    MemoryRegion *address_space);

/* ne2000.c */
static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
{
    DeviceState *dev;
    ISADevice *isadev;

    qemu_check_nic_model(nd, "ne2k_isa");

    isadev = isa_try_create(bus, "ne2k_isa");
    if (!isadev) {
        return false;
    }
    dev = DEVICE(isadev);
    qdev_prop_set_uint32(dev, "iobase", base);
    qdev_prop_set_uint32(dev, "irq",    irq);
    qdev_set_nic_properties(dev, nd);
    qdev_init_nofail(dev);
    return true;
}

/* pc_sysfw.c */
void pc_system_firmware_init(MemoryRegion *rom_memory,
                             bool isapc_ram_fw);

/* pvpanic.c */
void pvpanic_init(ISABus *bus);

/* e820 types */
#define E820_RAM        1
#define E820_RESERVED   2
#define E820_ACPI       3
#define E820_NVS        4
#define E820_UNUSABLE   5

int e820_add_entry(uint64_t, uint64_t, uint32_t);

#define PC_COMPAT_1_6 \
        {\
            .driver   = "e1000",\
            .property = "mitigation",\
            .value    = "off",\
        }

#define PC_COMPAT_1_5 \
        PC_COMPAT_1_6, \
        {\
            .driver   = "Conroe-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "Conroe-" TYPE_X86_CPU,\
            .property = "level",\
            .value    = stringify(2),\
        },{\
            .driver   = "Penryn-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "Penryn-" TYPE_X86_CPU,\
            .property = "level",\
            .value    = stringify(2),\
        },{\
            .driver   = "Nehalem-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(2),\
        },{\
            .driver   = "Nehalem-" TYPE_X86_CPU,\
            .property = "level",\
            .value    = stringify(2),\
        },{\
            .driver   = "virtio-net-pci",\
            .property = "any_layout",\
            .value    = "off",\
        },{\
            .driver = TYPE_X86_CPU,\
            .property = "pmu",\
            .value = "on",\
        }

#define PC_COMPAT_1_4 \
        PC_COMPAT_1_5, \
        {\
            .driver   = "scsi-hd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "scsi-cd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "scsi-disk",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "ide-hd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "ide-cd",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "ide-drive",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
        },{\
            .driver   = "virtio-blk-pci",\
            .property = "discard_granularity",\
            .value    = stringify(0),\
	},{\
            .driver   = "virtio-serial-pci",\
            .property = "vectors",\
            /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
            .value    = stringify(0xFFFFFFFF),\
        },{ \
            .driver   = "virtio-net-pci", \
            .property = "ctrl_guest_offloads", \
            .value    = "off", \
        },{\
            .driver   = "e1000",\
            .property = "romfile",\
            .value    = "pxe-e1000.rom",\
        },{\
            .driver   = "ne2k_pci",\
            .property = "romfile",\
            .value    = "pxe-ne2k_pci.rom",\
        },{\
            .driver   = "pcnet",\
            .property = "romfile",\
            .value    = "pxe-pcnet.rom",\
        },{\
            .driver   = "rtl8139",\
            .property = "romfile",\
            .value    = "pxe-rtl8139.rom",\
        },{\
            .driver   = "virtio-net-pci",\
            .property = "romfile",\
            .value    = "pxe-virtio.rom",\
        },{\
            .driver   = "486-" TYPE_X86_CPU,\
            .property = "model",\
            .value    = stringify(0),\
        }

#define PC_COMMON_MACHINE_OPTIONS \
    .default_boot_order = "cad"

#define PC_DEFAULT_MACHINE_OPTIONS \
    PC_COMMON_MACHINE_OPTIONS, \
    .hot_add_cpu = pc_hot_add_cpu, \
    .max_cpus = 255

#endif
Commit	Line	Data
87ecb68b PB	1	#ifndef HW_PC_H
87ecb68b PB	2	#define HW_PC_H
376253ec AL	3
376253ec AL	4	#include "qemu-common.h"
022c62cb	5	#include "exec/memory.h"
0d09e41a PB	6	#include "hw/isa/isa.h"
0d09e41a PB	7	#include "hw/block/fdc.h"
1422e32d	8	#include "net/net.h"
0d09e41a	9	#include "hw/i386/ioapic.h"
376253ec	10
3459a625	11	#include "qemu/range.h"
b20c9bd5 MT	12	#include "qemu/bitmap.h"
	13	#include "sysemu/sysemu.h"
	14	#include "hw/pci/pci.h"
3459a625	15
87ecb68b PB	16	/* PC-style peripherals (also used by other machines). */
87ecb68b PB	17
3459a625 MT	18	typedef struct PcPciInfo {
	19	Range w32;
	20	Range w64;
	21	} PcPciInfo;
	22
f854ecc7 MT	23	#define ACPI_PM_PROP_S3_DISABLED "disable_s3"
	24	#define ACPI_PM_PROP_S4_DISABLED "disable_s4"
	25	#define ACPI_PM_PROP_S4_VAL "s4_val"
	26	#define ACPI_PM_PROP_SCI_INT "sci_int"
	27	#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
	28	#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
	29	#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
	30	#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
	31	#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
	32
3459a625	33	struct PcGuestInfo {
f8c457b8	34	bool has_pci_info;
6dd2a5c9	35	bool isapc_ram_fw;
b20c9bd5 MT	36	hwaddr ram_size;
	37	unsigned apic_id_limit;
	38	bool apic_xrupt_override;
	39	uint64_t numa_nodes;
	40	uint64_t *node_mem;
	41	uint64_t *node_cpu;
3459a625 MT	42	FWCfgState *fw_cfg;
	43	};
	44
87ecb68b	45	/* parallel.c */
48a18b3c	46	static inline bool parallel_init(ISABus bus, int index, CharDriverState chr)
defdb20e	47	{
4a17cc4f AF	48	DeviceState *dev;
4a17cc4f AF	49	ISADevice *isadev;
defdb20e	50
4a17cc4f AF	51	isadev = isa_try_create(bus, "isa-parallel");
4a17cc4f AF	52	if (!isadev) {
73531538 BS	53	return false;
73531538 BS	54	}
4a17cc4f AF	55	dev = DEVICE(isadev);
	56	qdev_prop_set_uint32(dev, "index", index);
	57	qdev_prop_set_chr(dev, "chardev", chr);
	58	if (qdev_init(dev) < 0) {
defdb20e BS	59	return false;
	60	}
	61	return true;
	62	}
	63
63858cd9	64	bool parallel_mm_init(MemoryRegion *address_space,
a8170e5e	65	hwaddr base, int it_shift, qemu_irq irq,
defdb20e	66	CharDriverState *chr);
87ecb68b PB	67
	68	/* i8259.c */
	69
9aa78c42	70	extern DeviceState *isa_pic;
48a18b3c	71	qemu_irq i8259_init(ISABus bus, qemu_irq parent_irq);
10b61882	72	qemu_irq kvm_i8259_init(ISABus bus);
9aa78c42 JK	73	int pic_read_irq(DeviceState *d);
9aa78c42 JK	74	int pic_get_output(DeviceState *d);
84f2d0ea WX	75	void pic_info(Monitor mon, const QDict qdict);
84f2d0ea WX	76	void irq_info(Monitor mon, const QDict qdict);
87ecb68b	77
b881fbe9	78	/* Global System Interrupts */
96051119	79
b881fbe9	80	#define GSI_NUM_PINS IOAPIC_NUM_PINS
845773ab	81
b881fbe9	82	typedef struct GSIState {
43a0db35	83	qemu_irq i8259_irq[ISA_NUM_IRQS];
b881fbe9 JK	84	qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
	85	} GSIState;
	86
	87	void gsi_handler(void *opaque, int n, int level);
845773ab	88
87ecb68b	89	/* vmport.c */
d67f679d JK	90	typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
d67f679d JK	91
48a18b3c	92	static inline void vmport_init(ISABus *bus)
6872ef61	93	{
48a18b3c	94	isa_create_simple(bus, "vmport");
6872ef61	95	}
d67f679d JK	96
d67f679d JK	97	void vmport_register(unsigned char command, VMPortReadFunc func, void opaque);
86d86414 BS	98	void vmmouse_get_data(uint32_t *data);
86d86414 BS	99	void vmmouse_set_data(const uint32_t *data);
87ecb68b	100
87ecb68b PB	101	/* pckbd.c */
	102
	103	void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
	104	void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
dbff76ac	105	MemoryRegion *region, ram_addr_t size,
a8170e5e	106	hwaddr mask);
956a3e6b BS	107	void i8042_isa_mouse_fake_event(void *opaque);
956a3e6b BS	108	void i8042_setup_a20_line(ISADevice dev, qemu_irq a20_out);
87ecb68b	109
87ecb68b PB	110	/* pc.c */
	111	extern int fd_bootchk;
	112
8e78eb28	113	void pc_register_ferr_irq(qemu_irq irq);
845773ab IY	114	void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
845773ab IY	115
62fc403f	116	void pc_cpus_init(const char cpu_model, DeviceState icc_bridge);
c649983b	117	void pc_hot_add_cpu(const int64_t id, Error **errp);
f7e4dd6c	118	void pc_acpi_init(const char *default_dsdt);
3459a625 MT	119
	120	PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
	121	ram_addr_t above_4g_mem_size);
	122
39848901 IM	123	#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
	124	#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
	125	#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
	126	#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
	127	#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
1466cef3 MT	128	#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
	129
	130	static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
	131	{
	132	if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
	133	return 1ULL << 62;
	134	} else {
	135	return pci_hole64_size;
	136	}
	137	}
39848901 IM	138
	139	void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
	140	uint64_t pci_hole64_size);
	141
a88b362c LE	142	FWCfgState pc_memory_init(MemoryRegion system_memory,
	143	const char *kernel_filename,
	144	const char *kernel_cmdline,
	145	const char *initrd_filename,
	146	ram_addr_t below_4g_mem_size,
	147	ram_addr_t above_4g_mem_size,
	148	MemoryRegion *rom_memory,
3459a625 MT	149	MemoryRegion **ram_memory,
3459a625 MT	150	PcGuestInfo *guest_info);
845773ab	151	qemu_irq *pc_allocate_cpu_irq(void);
48a18b3c HP	152	DeviceState pc_vga_init(ISABus isa_bus, PCIBus *pci_bus);
48a18b3c HP	153	void pc_basic_device_init(ISABus isa_bus, qemu_irq gsi,
1611977c	154	ISADevice **rtc_state,
34d4260e	155	ISADevice **floppy,
1611977c	156	bool no_vmport);
48a18b3c	157	void pc_init_ne2k_isa(ISABus bus, NICInfo nd);
845773ab	158	void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
c0897e0c	159	const char *boot_device,
34d4260e	160	ISADevice floppy, BusState ide0, BusState *ide1,
63ffb564	161	ISADevice *s);
9011a1a7	162	void pc_nic_init(ISABus isa_bus, PCIBus pci_bus);
845773ab	163	void pc_pci_device_init(PCIBus *pci_bus);
8e78eb28	164
f885f1ea IY	165	typedef void (cpu_set_smm_t)(int smm, void arg);
	166	void cpu_smm_register(cpu_set_smm_t callback, void *arg);
	167
a39e3564 JB	168	void ioapic_init_gsi(GSIState gsi_state, const char parent_name);
a39e3564 JB	169
9d5e77a2	170	/* acpi_piix.c */
53b67b30	171
cf7a2fe2	172	i2c_bus piix4_pm_init(PCIBus bus, int devfn, uint32_t smb_io_base,
da98c8eb	173	qemu_irq sci_irq, qemu_irq smi_irq,
a88b362c	174	int kvm_enabled, FWCfgState *fw_cfg);
87ecb68b	175	void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
87ecb68b	176
16b29ae1 AL	177	/* hpet.c */
	178	extern int no_hpet;
	179
87ecb68b	180	/* piix_pci.c */
0a3bacf3 JQ	181	struct PCII440FXState;
	182	typedef struct PCII440FXState PCII440FXState;
	183
1e39101c	184	PCIBus i440fx_init(PCII440FXState pi440fx_state, int piix_devfn,
60573079	185	ISABus *isa_bus, qemu_irq pic,
aee97b84 AK	186	MemoryRegion *address_space_mem,
aee97b84 AK	187	MemoryRegion *address_space_io,
ae0a5466	188	ram_addr_t ram_size,
a8170e5e AK	189	hwaddr pci_hole_start,
a8170e5e AK	190	hwaddr pci_hole_size,
39848901	191	ram_addr_t above_4g_mem_size,
ae0a5466 AK	192	MemoryRegion *pci_memory,
ae0a5466 AK	193	MemoryRegion *ram_memory);
87ecb68b	194
277e9340	195	PCIBus *find_i440fx(void);
823e675a	196	/* piix4.c */
b1d8e52e	197	extern PCIDevice *piix4_dev;
142e9787	198	int piix4_init(PCIBus bus, ISABus *isa_bus, int devfn);
87ecb68b PB	199
87ecb68b PB	200	/* vga.c */
cb5a7aa8	201	enum vga_retrace_method {
	202	VGA_RETRACE_DUMB,
	203	VGA_RETRACE_PRECISE
	204	};
	205
	206	extern enum vga_retrace_method vga_retrace_method;
87ecb68b	207
a8170e5e AK	208	int isa_vga_mm_init(hwaddr vram_base,
a8170e5e AK	209	hwaddr ctrl_base, int it_shift,
be20f9e9	210	MemoryRegion *address_space);
87ecb68b	211
87ecb68b	212	/* ne2000.c */
48a18b3c	213	static inline bool isa_ne2000_init(ISABus bus, int base, int irq, NICInfo nd)
60a14ad3	214	{
4a17cc4f AF	215	DeviceState *dev;
4a17cc4f AF	216	ISADevice *isadev;
87ecb68b	217
60a14ad3 BS	218	qemu_check_nic_model(nd, "ne2k_isa");
60a14ad3 BS	219
4a17cc4f AF	220	isadev = isa_try_create(bus, "ne2k_isa");
4a17cc4f AF	221	if (!isadev) {
cd1b8a8b BS	222	return false;
cd1b8a8b BS	223	}
4a17cc4f AF	224	dev = DEVICE(isadev);
	225	qdev_prop_set_uint32(dev, "iobase", base);
	226	qdev_prop_set_uint32(dev, "irq", irq);
	227	qdev_set_nic_properties(dev, nd);
	228	qdev_init_nofail(dev);
cd1b8a8b	229	return true;
60a14ad3	230	}
87ecb68b	231
cbc5b5f3	232	/* pc_sysfw.c */
6dd2a5c9 PB	233	void pc_system_firmware_init(MemoryRegion *rom_memory,
6dd2a5c9 PB	234	bool isapc_ram_fw);
cbc5b5f3	235
3ab135f3	236	/* pvpanic.c */
bc3e6a0d	237	void pvpanic_init(ISABus *bus);
3ab135f3	238
4c5b10b7 JS	239	/* e820 types */
	240	#define E820_RAM 1
	241	#define E820_RESERVED 2
	242	#define E820_ACPI 3
	243	#define E820_NVS 4
	244	#define E820_UNUSABLE 5
	245
	246	int e820_add_entry(uint64_t, uint64_t, uint32_t);
	247
e9845f09 VM	248	#define PC_COMPAT_1_6 \
	249	{\
	250	.driver = "e1000",\
	251	.property = "mitigation",\
	252	.value = "off",\
	253	}
	254
ffce9ebb	255	#define PC_COMPAT_1_5 \
e9845f09	256	PC_COMPAT_1_6, \
ffce9ebb EH	257	{\
	258	.driver = "Conroe-" TYPE_X86_CPU,\
	259	.property = "model",\
	260	.value = stringify(2),\
6b11322e EH	261	},{\
	262	.driver = "Conroe-" TYPE_X86_CPU,\
	263	.property = "level",\
	264	.value = stringify(2),\
ffce9ebb EH	265	},{\
	266	.driver = "Penryn-" TYPE_X86_CPU,\
	267	.property = "model",\
	268	.value = stringify(2),\
6b11322e EH	269	},{\
	270	.driver = "Penryn-" TYPE_X86_CPU,\
	271	.property = "level",\
	272	.value = stringify(2),\
ffce9ebb EH	273	},{\
	274	.driver = "Nehalem-" TYPE_X86_CPU,\
	275	.property = "model",\
	276	.value = stringify(2),\
6b11322e EH	277	},{\
	278	.driver = "Nehalem-" TYPE_X86_CPU,\
	279	.property = "level",\
	280	.value = stringify(2),\
488f069b MT	281	},{\
	282	.driver = "virtio-net-pci",\
	283	.property = "any_layout",\
	284	.value = "off",\
9337e3b6 EH	285	},{\
	286	.driver = TYPE_X86_CPU,\
	287	.property = "pmu",\
	288	.value = "on",\
ffce9ebb EH	289	}
ffce9ebb EH	290
bf3caa3d	291	#define PC_COMPAT_1_4 \
ffce9ebb	292	PC_COMPAT_1_5, \
bf3caa3d PB	293	{\
	294	.driver = "scsi-hd",\
	295	.property = "discard_granularity",\
	296	.value = stringify(0),\
	297	},{\
	298	.driver = "scsi-cd",\
	299	.property = "discard_granularity",\
	300	.value = stringify(0),\
	301	},{\
	302	.driver = "scsi-disk",\
	303	.property = "discard_granularity",\
	304	.value = stringify(0),\
	305	},{\
	306	.driver = "ide-hd",\
	307	.property = "discard_granularity",\
	308	.value = stringify(0),\
	309	},{\
	310	.driver = "ide-cd",\
	311	.property = "discard_granularity",\
	312	.value = stringify(0),\
	313	},{\
	314	.driver = "ide-drive",\
	315	.property = "discard_granularity",\
	316	.value = stringify(0),\
c45e5b5b	317	},{\
bf3caa3d PB	318	.driver = "virtio-blk-pci",\
	319	.property = "discard_granularity",\
	320	.value = stringify(0),\
554f1997 GH	321	},{\
	322	.driver = "virtio-serial-pci",\
	323	.property = "vectors",\
	324	/* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
	325	.value = stringify(0xFFFFFFFF),\
644c9858 DF	326	},{ \
	327	.driver = "virtio-net-pci", \
	328	.property = "ctrl_guest_offloads", \
	329	.value = "off", \
c45e5b5b GH	330	},{\
	331	.driver = "e1000",\
	332	.property = "romfile",\
	333	.value = "pxe-e1000.rom",\
	334	},{\
	335	.driver = "ne2k_pci",\
	336	.property = "romfile",\
	337	.value = "pxe-ne2k_pci.rom",\
	338	},{\
	339	.driver = "pcnet",\
	340	.property = "romfile",\
	341	.value = "pxe-pcnet.rom",\
	342	},{\
	343	.driver = "rtl8139",\
	344	.property = "romfile",\
	345	.value = "pxe-rtl8139.rom",\
	346	},{\
	347	.driver = "virtio-net-pci",\
	348	.property = "romfile",\
	349	.value = "pxe-virtio.rom",\
b2a856d9 AF	350	},{\
	351	.driver = "486-" TYPE_X86_CPU,\
	352	.property = "model",\
	353	.value = stringify(0),\
c45e5b5b	354	}
bf3caa3d	355
a0dba644 MT	356	#define PC_COMMON_MACHINE_OPTIONS \
	357	.default_boot_order = "cad"
	358
	359	#define PC_DEFAULT_MACHINE_OPTIONS \
	360	PC_COMMON_MACHINE_OPTIONS, \
	361	.hot_add_cpu = pc_hot_add_cpu, \
	362	.max_cpus = 255
	363
87ecb68b	364	#endif